stats: Bump stats for fixes, mostly TLB and WriteInvalidate

54 files changed, 57981 insertions, 56981 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 85db7b5af..d1ad31617 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,108 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.883224                       # Number of seconds simulated
-sim_ticks                                1883224346500                       # Number of ticks simulated
-final_tick                               1883224346500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.884241                       # Number of seconds simulated
+sim_ticks                                1884241273000                       # Number of ticks simulated
+final_tick                               1884241273000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 279379                       # Simulator instruction rate (inst/s)
-host_op_rate                                   279379                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9375076807                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311380                       # Number of bytes of host memory used
-host_seconds                                   200.88                       # Real time elapsed on the host
-sim_insts                                    56120453                       # Number of instructions simulated
-sim_ops                                      56120453                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 193195                       # Simulator instruction rate (inst/s)
+host_op_rate                                   193195                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6486085343                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317148                       # Number of bytes of host memory used
+host_seconds                                   290.51                       # Real time elapsed on the host
+sim_insts                                    56124126                       # Number of instructions simulated
+sim_ops                                      56124126                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          25931648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          25914944                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25932608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1052800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1052800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4903936                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7563264                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             405182                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25915904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1052928                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1052928                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7561408                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7561408                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             404921                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                405197                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           76624                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118176                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             13769813                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13770323                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          559041                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             559041                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2604011                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1412114                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4016125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2604011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            13769813                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1412624                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17786448                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        405197                       # Number of read requests accepted
-system.physmem.writeReqs                       118176                       # Number of write requests accepted
-system.physmem.readBursts                      405197                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118176                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25920704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7562112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25932608                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7563264                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      186                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            154                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25484                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25740                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25857                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25788                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25237                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24959                       # Per bank write bursts
+system.physmem.num_reads::total                404936                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118147                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118147                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             13753517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13754026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          558807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             558807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4012972                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4012972                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4012972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            13753517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17766999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404936                       # Number of read requests accepted
+system.physmem.writeReqs                       159699                       # Number of write requests accepted
+system.physmem.readBursts                      404936                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     159699                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25909568                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6336                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10083392                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25915904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10220736                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       99                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2126                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            153                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25482                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25742                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25842                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25776                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25226                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24953                       # Per bank write bursts
 system.physmem.perBankRdBursts::6               24814                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24586                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25127                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25284                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25531                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24857                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24549                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25592                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25866                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7812                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7680                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8067                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7745                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7320                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6957                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6792                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6401                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7236                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6892                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7391                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6866                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7045                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8010                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7989                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7955                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24563                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25102                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25273                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25528                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24851                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24526                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25574                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25842                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25743                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10288                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10037                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10678                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10053                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9806                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9437                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9137                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8750                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9885                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8937                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9881                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9301                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9770                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10691                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10395                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10507                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1883215617500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1884232486500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  405197                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404936                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118176                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402689                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2242                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        68                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 159699                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402545                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        71                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -147,337 +144,188 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63140                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      530.294837                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     322.585016                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.640457                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14650     23.20%     23.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10589     16.77%     39.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5075      8.04%     48.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3003      4.76%     52.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2370      3.75%     56.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2105      3.33%     59.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1364      2.16%     62.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1607      2.55%     64.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22377     35.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63140                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5316                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.186983                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2896.748549                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5313     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3925                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     9181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9850                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11766                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9987                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8498                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      397                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      547.429771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     335.789885                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     418.130322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14719     22.39%     22.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10714     16.30%     38.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4807      7.31%     45.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3176      4.83%     50.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2550      3.88%     54.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1953      2.97%     57.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1437      2.19%     59.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1697      2.58%     62.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24696     37.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65749                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5738                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.553154                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2788.767091                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5735     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5316                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5316                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.226862                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.933757                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.590348                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4662     87.70%     87.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              15      0.28%     87.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              21      0.40%     88.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             225      4.23%     92.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              46      0.87%     93.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              10      0.19%     93.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               7      0.13%     93.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.13%     93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              19      0.36%     94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.06%     94.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.04%     94.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.04%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              12      0.23%     94.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.11%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              29      0.55%     95.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              14      0.26%     95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.04%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              12      0.23%     95.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             164      3.09%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.09%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.04%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             3      0.06%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.08%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             3      0.06%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             8      0.15%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             6      0.11%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            12      0.23%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.06%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.06%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             3      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5316                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2156220500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9750176750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2025055000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5323.86                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5738                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5738                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.457825                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.746842                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       34.017596                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4693     81.79%     81.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             187      3.26%     85.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             275      4.79%     89.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              67      1.17%     91.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              92      1.60%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              47      0.82%     93.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              24      0.42%     93.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              11      0.19%     94.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              19      0.33%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               7      0.12%     94.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             14      0.24%     94.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             6      0.10%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             7      0.12%     94.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             4      0.07%     95.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            17      0.30%     95.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            47      0.82%     96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            17      0.30%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            17      0.30%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            79      1.38%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            32      0.56%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            20      0.35%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            19      0.33%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            15      0.26%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             7      0.12%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             4      0.07%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5738                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2167079250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9757773000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2024185000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5352.97                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24073.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.76                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24102.97                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.75                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.75                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.42                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.67                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364400                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95629                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.97                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3598228.45                       # Average gap between requests
-system.physmem.pageHitRate                      87.93                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1774012993500                       # Time in different power states
-system.physmem.memoryStateTime::REF       62884900000                       # Time in different power states
+system.physmem.avgWrQLen                        24.74                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364185                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    132456                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.96                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3337080.57                       # Average gap between requests
+system.physmem.pageHitRate                      88.31                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1774592996500                       # Time in different power states
+system.physmem.memoryStateTime::REF       62918700000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       46323736500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       46722146000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 232613640                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 244724760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 126922125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 133530375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1579227000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1579858800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               380855520                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               384808320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          123002864400                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          123002864400                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           59595719580                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           60657122565                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1077656022750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1076724967500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1262574225015                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1262727876720                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.433163                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.514753                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              295760                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295744                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9618                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9618                       # Transaction distribution
-system.membus.trans_dist::Writeback             76624                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              154                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             154                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116541                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116541                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33096                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887296                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920424                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1003716                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30835584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30879892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33540180                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              158                       # Total snoops (count)
-system.membus.snoop_fanout::samples            523708                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  523708    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              523708                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30927500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1547261750                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               20000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3825161596                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43114249                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.288180                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1728025257000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.288180                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.080511                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.080511                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2512658057                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2512658057                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                14964931                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12983118                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            374694                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9691016                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5184483                       # Number of BTB hits
+system.physmem.actEnergy::0                 242668440                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 254394000                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 132408375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 138806250                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1578704400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1579024200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               506645280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               514298160                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          123068977200                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          123068977200                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           59931006120                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           60719870160                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1077969239250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1077277253250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1263429649065                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1263552623220                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             670.526996                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.592261                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                15011318                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13019220                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            376037                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9980368                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5204970                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             53.497827                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  807557                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              32108                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             52.152085                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  808971                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32603                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9237824                       # DTB read hits
-system.cpu.dtb.read_misses                      17804                       # DTB read misses
+system.cpu.dtb.read_hits                      9241438                       # DTB read hits
+system.cpu.dtb.read_misses                      17791                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   766148                       # DTB read accesses
-system.cpu.dtb.write_hits                     6384867                       # DTB write hits
-system.cpu.dtb.write_misses                      2306                       # DTB write misses
+system.cpu.dtb.read_accesses                   766265                       # DTB read accesses
+system.cpu.dtb.write_hits                     6385998                       # DTB write hits
+system.cpu.dtb.write_misses                      2317                       # DTB write misses
 system.cpu.dtb.write_acv                          159                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298467                       # DTB write accesses
-system.cpu.dtb.data_hits                     15622691                       # DTB hits
-system.cpu.dtb.data_misses                      20110                       # DTB misses
+system.cpu.dtb.write_accesses                  298404                       # DTB write accesses
+system.cpu.dtb.data_hits                     15627436                       # DTB hits
+system.cpu.dtb.data_misses                      20108                       # DTB misses
 system.cpu.dtb.data_acv                           370                       # DTB access violations
-system.cpu.dtb.data_accesses                  1064615                       # DTB accesses
-system.cpu.itb.fetch_hits                     3999749                       # ITB hits
-system.cpu.itb.fetch_misses                      6851                       # ITB misses
-system.cpu.itb.fetch_acv                          647                       # ITB acv
-system.cpu.itb.fetch_accesses                 4006600                       # ITB accesses
+system.cpu.dtb.data_accesses                  1064669                       # DTB accesses
+system.cpu.itb.fetch_hits                     4019003                       # ITB hits
+system.cpu.itb.fetch_misses                      6884                       # ITB misses
+system.cpu.itb.fetch_acv                          661                       # ITB acv
+system.cpu.itb.fetch_accesses                 4025887                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -490,39 +338,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        174888375                       # number of cpu cycles simulated
+system.cpu.numCycles                        175285694                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56120453                       # Number of instructions committed
-system.cpu.committedOps                      56120453                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2530516                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5527                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3591560318                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.116304                       # CPI: cycles per instruction
-system.cpu.ipc                               0.320893                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56124126                       # Number of instructions committed
+system.cpu.committedOps                      56124126                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2495853                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5575                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3593196852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.123179                       # CPI: cycles per instruction
+system.cpu.ipc                               0.320187                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6374                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211459                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74787     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211480                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74791     40.94%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1900      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105855     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182673                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73420     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105868     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182691                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73424     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1900      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73420     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148871                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1832868777500     97.33%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                80360500      0.00%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               672864500      0.04%     97.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             49601349000      2.63%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1883223351500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981721                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73424     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148880                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1833816082000     97.32%     97.32% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                80474500      0.00%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               673053000      0.04%     97.36% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             49670669500      2.64%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1884240279000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981722                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693590                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814959                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693543                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814928                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -558,71 +406,475 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175516     91.23%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6803      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175532     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5125      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192398                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5867                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192418                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5870                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1743                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1910                      
-system.cpu.kern.mode_good::user                  1741                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.325550                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::kernel                1913                      
+system.cpu.kern.mode_good::user                  1743                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.325894                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080553                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393571                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36222818500      1.92%      1.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4061127000      0.22%      2.14% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1842939396000     97.86%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
-system.cpu.tickCycles                        83840328                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        91048047                       # Total number of cycles that the object has spent stopped
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.393986                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36270859500      1.92%      1.92% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4083023000      0.22%      2.14% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1843886386500     97.86%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
+system.cpu.tickCycles                        84485847                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        90799847                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1395229                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.982334                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13773041                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395741                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.867906                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          86820250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982334                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999965                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63657366                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63657366                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst      7814636                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7814636                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      5576637                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576637                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182736                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182736                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       198999                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       198999                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      13391273                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13391273                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     13391273                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13391273                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1201532                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201532                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       573582                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573582                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17284                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17284                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1775114                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775114                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1775114                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775114                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31036730750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31036730750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20700048539                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20700048539                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231020000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    231020000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  51736779289                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51736779289                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  51736779289                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51736779289                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst      9016168                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9016168                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      6150219                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6150219                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200020                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200020                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198999                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       198999                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     15166387                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15166387                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     15166387                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15166387                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133264                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133264                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093262                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093262                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086411                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086411                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.117043                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.117043                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29145.609403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29145.609403                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       838115                       # number of writebacks
+system.cpu.dcache.writebacks::total            838115                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127210                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127210                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269406                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269406                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       396616                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       396616                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       396616                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       396616                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074322                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074322                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304176                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304176                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17281                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17281                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1378498                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378498                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1378498                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378498                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26919627250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26919627250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10259801597                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10259801597                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196291500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196291500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37179428847                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37179428847                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37179428847                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37179428847                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423887000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423887000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2002910000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002910000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426797000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426797000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119155                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119155                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049458                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049458                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086396                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086396                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090892                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090892                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090892                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090892                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26970.970467                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26970.970467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26970.970467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26970.970467                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements           1458001                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.626489                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18970775                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1458512                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             13.006938                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31607473250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.626489                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995364                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995364                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          21888154                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21888154                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18970778                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18970778                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18970778                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18970778                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18970778                       # number of overall hits
+system.cpu.icache.overall_hits::total        18970778                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1458688                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1458688                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1458688                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1458688                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1458688                       # number of overall misses
+system.cpu.icache.overall_misses::total       1458688                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20029373869                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20029373869                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20029373869                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20029373869                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20029373869                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20029373869                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20429466                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20429466                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20429466                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20429466                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20429466                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20429466                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071401                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071401                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071401                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071401                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071401                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071401                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13731.088395                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13731.088395                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13731.088395                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13731.088395                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13731.088395                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13731.088395                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458688                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1458688                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1458688                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1458688                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1458688                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1458688                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17104729131                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17104729131                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17104729131                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17104729131                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17104729131                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17104729131                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071401                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071401                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071401                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11726.105330                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11726.105330                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements           339435                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65326.200893                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2981535                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404597                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.369148                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5873248750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.831524                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165275                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996799                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1458                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2791                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55536                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         30249203                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        30249203                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      2261508                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2261508                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       838115                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       838115                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.inst            4                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       187530                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187530                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      2449038                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2449038                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      2449038                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2449038                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       288693                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288693                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.inst           17                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       116655                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116655                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       405348                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        405348                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       405348                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       405348                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18932535000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  18932535000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       214497                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       214497                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8075894612                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8075894612                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  27008429612                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27008429612                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  27008429612                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27008429612                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      2550201                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2550201                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       838115                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       838115                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304185                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304185                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      2854386                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2854386                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2854386                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2854386                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113204                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.113204                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.809524                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383500                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383500                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142009                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.142009                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142009                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.142009                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65580.166474                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        76635                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76635                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288693                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288693                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           17                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116655                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116655                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       405348                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       405348                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       405348                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       405348                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15323296500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15323296500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       271014                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       271014                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6608324888                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6608324888                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21931621388                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21931621388                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21931621388                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21931621388                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333779000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333779000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1887481500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887481500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3221260500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3221260500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113204                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113204                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.809524                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383500                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383500                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.142009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.142009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst        15942                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15942                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        2557364                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557331                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       838115                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917316                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3662927                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6580243                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93352192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143021148                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          236373340                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       41941                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3734307                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.011173                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.105112                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3692582     98.88%     98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              41725      1.12%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3734307                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2697490998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2191666369                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2194528153                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51170                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51170                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5092                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51171                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               9619                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5094                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -634,11 +886,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33096                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33098                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116546                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20368                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20376                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -650,11 +902,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44308                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44316                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705916                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4703000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705924                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              4705000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -676,435 +928,188 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           374407689                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406196790                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23478000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23479000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42013751                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42010500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1457910                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.626980                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18940924                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1458421                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.987281                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31560714250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.626980                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995365                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995365                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21858119                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21858119                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18940927                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18940927                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18940927                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18940927                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18940927                       # number of overall hits
-system.cpu.icache.overall_hits::total        18940927                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1458596                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1458596                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1458596                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1458596                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1458596                       # number of overall misses
-system.cpu.icache.overall_misses::total       1458596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20022164568                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20022164568                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20022164568                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20022164568                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20022164568                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20022164568                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20399523                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20399523                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20399523                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20399523                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20399523                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20399523                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071501                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071501                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071501                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071501                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071501                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071501                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13727.011844                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13727.011844                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458596                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1458596                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1458596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1458596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1458596                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1458596                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17097663432                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17097663432                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17097663432                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17097663432                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17097663432                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17097663432                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071501                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071501                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071501                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071501                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071501                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071501                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2557139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557106                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       838111                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917133                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3662791                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6579924                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93346368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143016724                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          236363092                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       41947                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3734153                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.011176                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.105123                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3692421     98.88%     98.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41732      1.12%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3734153                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2697404999                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2191548568                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2194491404                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           339424                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65327.181695                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2981337                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404586                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.368859                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5872511750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.831497                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165317                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996814                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1457                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5166                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2781                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         30247978                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        30247978                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      2261320                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2261320                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       838111                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       838111                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       187575                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187575                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      2448895                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2448895                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      2448895                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2448895                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst       288657                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288657                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst           17                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       116678                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116678                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       405335                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        405335                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       405335                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405335                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18918279000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  18918279000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       115495                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       115495                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8105432113                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8105432113                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27023711113                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27023711113                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27023711113                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27023711113                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      2549977                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2549977                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       838111                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       838111                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304253                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304253                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      2854230                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2854230                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2854230                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2854230                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113200                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.113200                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383490                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383490                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142012                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.142012                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142012                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.142012                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst  6793.823529                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6793.823529                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76624                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76624                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288657                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288657                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116678                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116678                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       405335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       405335                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405335                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15309425000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15309425000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       170516                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       170516                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6604759387                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6604759387                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21914184387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21914184387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21914184387                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21914184387                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333304000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333304000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1888377500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1888377500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3221681500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3221681500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113200                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113200                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383490                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383490                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.142012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142012                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.142012                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1395163                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.982303                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13764370                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395675                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.862160                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          86814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982303                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63622669                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63622669                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst      7806418                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7806418                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst      5576177                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5576177                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182756                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182756                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       198986                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       198986                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      13382595                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13382595                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     13382595                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13382595                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      1201460                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201460                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       573699                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573699                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17252                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17252                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1775159                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1775159                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1775159                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1775159                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31026314750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31026314750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20775588791                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20775588791                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    230892000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    230892000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  51801903541                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51801903541                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  51801903541                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51801903541                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst      9007878                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9007878                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst      6149876                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6149876                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200008                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200008                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198986                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       198986                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     15157754                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15157754                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     15157754                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15157754                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133379                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133379                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093286                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093286                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086257                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086257                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.117112                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117112                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.117112                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117112                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29181.556999                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29181.556999                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838111                       # number of writebacks
-system.cpu.dcache.writebacks::total            838111                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127232                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127232                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269462                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269462                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       396694                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       396694                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       396694                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       396694                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074228                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074228                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304237                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304237                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17249                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17249                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1378465                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378465                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1378465                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378465                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26911701750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26911701750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10289625346                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10289625346                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196226500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196226500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37201327096                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37201327096                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37201327096                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37201327096                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423395500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423395500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2003794000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2003794000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3427189500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3427189500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119254                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119254                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049470                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049470                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086242                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086242                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090941                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090941                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090941                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090941                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.tags.replacements                41685                       # number of replacements
+system.iocache.tags.tagsinuse                1.296059                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1728026020000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.296059                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081004                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081004                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13635314907                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13635314907                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        206297                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23564                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.754753                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11474610907                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11474610907                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              295796                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295780                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
+system.membus.trans_dist::Writeback            118147                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              155                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             155                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116517                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116517                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920188                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1044992                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30819584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30863900                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36180956                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              433                       # Total snoops (count)
+system.membus.snoop_fanout::samples            565237                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  565237    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              565237                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30298500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy          1878232500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy               20000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3792450097                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy           43109500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 4efdefebb..092a1319f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,125 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.905068                       # Number of seconds simulated
-sim_ticks                                1905067807000                       # Number of ticks simulated
-final_tick                               1905067807000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.901187                       # Number of seconds simulated
+sim_ticks                                1901187238000                       # Number of ticks simulated
+final_tick                               1901187238000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 154638                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154638                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5148903745                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378896                       # Number of bytes of host memory used
-host_seconds                                   369.99                       # Real time elapsed on the host
-sim_insts                                    57215334                       # Number of instructions simulated
-sim_ops                                      57215334                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 164685                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164685                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5473626023                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 324480                       # Number of bytes of host memory used
+host_seconds                                   347.34                       # Real time elapsed on the host
+sim_insts                                    57201060                       # Number of instructions simulated
+sim_ops                                      57201060                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           865344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24709248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           118912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           545600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           886592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24764800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            96384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           525056                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26240064                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       865344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       118912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          984256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5157696                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7817024                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13521                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            386082                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1858                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8525                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26273792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       886592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        96384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          982976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7873024                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7873024                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13853                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            386950                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1506                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8204                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                410001                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           80589                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122141                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              454233                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12970272                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               62419                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              286394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13773822                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         454233                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          62419                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             516651                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2707356                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1395923                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4103279                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2707356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             454233                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12970272                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              62419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             286394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1396427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17877100                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        410001                       # Number of read requests accepted
-system.physmem.writeReqs                       122141                       # Number of write requests accepted
-system.physmem.readBursts                      410001                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     122141                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26227648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     12416                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7815104                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26240064                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7817024                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      194                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           6364                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25988                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25697                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25753                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25768                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25192                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25524                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25779                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25095                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25528                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25751                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25719                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25446                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25795                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25643                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25930                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25199                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8301                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7506                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7807                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7337                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6902                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7063                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7447                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7245                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7339                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7570                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7510                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8378                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8362                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8512                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7850                       # Per bank write bursts
+system.physmem.num_reads::total                410528                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123016                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123016                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              466336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            13025966                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               50697                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              276173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13819676                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         466336                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          50697                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517033                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4141109                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4141109                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4141109                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             466336                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13025966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              50697                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             276173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17960785                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410528                       # Number of read requests accepted
+system.physmem.writeReqs                       164568                       # Number of write requests accepted
+system.physmem.readBursts                      410528                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     164568                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26267072                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10385920                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26273792                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10532352                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2261                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           6311                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25881                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25672                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26260                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25757                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25283                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25202                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25755                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25257                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25550                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25721                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25770                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25804                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25810                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25881                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25644                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25176                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10943                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9789                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10222                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9625                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9290                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9560                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10277                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9346                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9649                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9784                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9978                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10113                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              11182                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11629                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10712                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10181                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1905063366000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1901182789000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  410001                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410528                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 122141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     40469                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     42857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9026                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 164568                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317417                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     40637                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     43118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9157                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        73                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -161,192 +158,187 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64430                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      528.357101                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.789036                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.784578                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14909     23.14%     23.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11361     17.63%     40.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5102      7.92%     48.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2869      4.45%     53.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2286      3.55%     56.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1687      2.62%     59.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1558      2.42%     61.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1655      2.57%     64.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23003     35.70%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64430                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5515                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        74.305712                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2843.118152                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5512     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9457                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    12067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    11257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67066                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      546.521218                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     334.319778                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.846112                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14858     22.15%     22.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11363     16.94%     39.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5157      7.69%     46.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2935      4.38%     51.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2350      3.50%     54.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1701      2.54%     57.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1587      2.37%     59.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1704      2.54%     62.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25411     37.89%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67066                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6000                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.402667                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2725.840527                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5997     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5515                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5515                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.141614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.970992                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.024334                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4751     86.15%     86.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             123      2.23%     88.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              15      0.27%     88.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             231      4.19%     92.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              39      0.71%     93.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              12      0.22%     93.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               8      0.15%     93.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               4      0.07%     93.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              23      0.42%     94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.05%     94.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.09%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.04%     94.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               7      0.13%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.05%     94.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.09%     94.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              28      0.51%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              10      0.18%     95.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.04%     95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              17      0.31%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             177      3.21%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.05%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.04%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.04%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.07%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.04%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.07%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             5      0.09%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.05%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.09%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             8      0.15%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.04%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.07%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             2      0.04%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5515                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3875472500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11559353750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2049035000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9456.82                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6000                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.046667                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.651184                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       33.190276                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4953     82.55%     82.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             193      3.22%     85.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             289      4.82%     90.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              50      0.83%     91.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              96      1.60%     93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              44      0.73%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              19      0.32%     94.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               8      0.13%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              23      0.38%     94.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              10      0.17%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             13      0.22%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             6      0.10%     95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             7      0.12%     95.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             5      0.08%     95.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            20      0.33%     95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            38      0.63%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            17      0.28%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            12      0.20%     96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            91      1.52%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            43      0.72%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            17      0.28%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            19      0.32%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             8      0.13%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.03%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             9      0.15%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6000                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3893190750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11588622000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2052115000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9485.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28206.82                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28235.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.82                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.54                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.97                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.10                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     369467                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98020                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.25                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3579990.62                       # Average gap between requests
-system.physmem.pageHitRate                      87.88                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1804432107750                       # Time in different power states
-system.physmem.memoryStateTime::REF       63614200000                       # Time in different power states
+system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     370176                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    135461                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  83.46                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3305852.92                       # Average gap between requests
+system.physmem.pageHitRate                      88.29                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1800384684500                       # Time in different power states
+system.physmem.memoryStateTime::REF       63484720000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37016700250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       37315104250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 243908280                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 243137160                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 133084875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 132664125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1597408800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1598750400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               384555600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               406470960                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          124429375200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          124429375200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           57078983475                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           56985810705                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1092967983000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1093049713500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1276835299230                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1276845922050                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.232898                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.238474                       # Core power per rank (mW)
-system.cpu0.branchPred.lookups               14962614                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13045209                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           300344                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             9143692                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5116520                       # Number of BTB hits
+system.physmem.actEnergy::0                 252216720                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 254802240                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 137618250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 139029000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1599522600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1601776800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               512256960                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               539317440                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          124176112320                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          124176112320                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           57055460715                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           57001965930                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1090662047250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1090708972500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1274395234815                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1274421976230                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             670.316446                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.330512                       # Core power per rank (mW)
+system.cpu0.branchPred.lookups               15024669                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13090822                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           302150                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             9266199                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5129053                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            55.956828                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 756655                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             14726                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            55.352286                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 762066                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             14857                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8668714                       # DTB read hits
-system.cpu0.dtb.read_misses                     31568                       # DTB read misses
-system.cpu0.dtb.read_acv                          533                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  683834                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5507711                       # DTB write hits
-system.cpu0.dtb.write_misses                     6832                       # DTB write misses
-system.cpu0.dtb.write_acv                         377                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 235007                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14176425                       # DTB hits
-system.cpu0.dtb.data_misses                     38400                       # DTB misses
-system.cpu0.dtb.data_acv                          910                       # DTB access violations
-system.cpu0.dtb.data_accesses                  918841                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1355401                       # ITB hits
-system.cpu0.itb.fetch_misses                    29256                       # ITB misses
-system.cpu0.itb.fetch_acv                         621                       # ITB acv
-system.cpu0.itb.fetch_accesses                1384657                       # ITB accesses
+system.cpu0.dtb.read_hits                     8699665                       # DTB read hits
+system.cpu0.dtb.read_misses                     31652                       # DTB read misses
+system.cpu0.dtb.read_acv                          518                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  684964                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5527628                       # DTB write hits
+system.cpu0.dtb.write_misses                     7312                       # DTB write misses
+system.cpu0.dtb.write_acv                         384                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 236678                       # DTB write accesses
+system.cpu0.dtb.data_hits                    14227293                       # DTB hits
+system.cpu0.dtb.data_misses                     38964                       # DTB misses
+system.cpu0.dtb.data_acv                          902                       # DTB access violations
+system.cpu0.dtb.data_accesses                  921642                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1360805                       # ITB hits
+system.cpu0.itb.fetch_misses                    29325                       # ITB misses
+system.cpu0.itb.fetch_acv                         623                       # ITB acv
+system.cpu0.itb.fetch_accesses                1390130                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -359,467 +351,467 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       108456707                       # number of cpu cycles simulated
+system.cpu0.numCycles                       108792579                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          24325754                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      66694894                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   14962614                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5873175                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     76828249                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1001726                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       825                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               30281                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      1454626                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       459540                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          204                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7777949                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               213350                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.icacheStallCycles          24480610                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      66921510                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   15024669                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5891119                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     76960209                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1006918                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       587                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               30320                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      1459024                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       459440                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          228                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7808182                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               214478                       # Number of outstanding Icache misses that were squashed
 system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         103600342                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.643771                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.943909                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples         103893877                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.644133                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.944480                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                91056774     87.89%     87.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  810107      0.78%     88.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1760430      1.70%     90.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  739408      0.71%     91.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2516394      2.43%     93.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  557837      0.54%     94.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  633248      0.61%     94.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  717698      0.69%     95.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4808446      4.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                91308838     87.89%     87.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  814381      0.78%     88.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1763801      1.70%     90.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  741690      0.71%     91.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2523255      2.43%     93.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  561128      0.54%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  635570      0.61%     94.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  719335      0.69%     95.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4825879      4.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           103600342                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.137959                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.614945                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                19762809                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             73625982                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8017389                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1725855                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                468306                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              492047                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                33030                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              58728782                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               102789                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                468306                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                20585060                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               48251734                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17899835                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  8819055                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7576350                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              56729728                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               201548                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2018005                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                142949                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               3756211                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           38050244                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             69305662                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        69181835                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           114815                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33467059                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4583177                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1358842                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        197413                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12487165                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8791454                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5770533                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1295730                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          947864                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  50680779                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1726956                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 49798033                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            52306                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5972660                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2859786                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1187974                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    103600342                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.480674                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.214257                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           103893877                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.138104                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.615129                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                19900832                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             73745257                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8046257                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1730950                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                470580                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              495026                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                33344                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              58913691                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               103815                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                470580                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                20722206                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               48316669                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17970373                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  8856068                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7557979                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              56901533                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               202703                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2015999                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                141191                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               3736855                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           38160864                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             69501237                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        69376844                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           115358                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33567232                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4593624                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1365129                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        198221                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12480015                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             8824182                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5791367                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1299957                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          953544                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  50831435                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1735186                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 49951846                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            52661                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5989483                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2856975                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1193961                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    103893877                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.480797                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.214404                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           83011266     80.13%     80.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            8965198      8.65%     88.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3720190      3.59%     92.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2652497      2.56%     94.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2683429      2.59%     97.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1272361      1.23%     98.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             837773      0.81%     99.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             348219      0.34%     99.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             109409      0.11%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           83240383     80.12%     80.12% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            8994841      8.66%     88.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3729897      3.59%     92.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2662216      2.56%     94.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2692674      2.59%     97.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1272103      1.22%     98.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             842802      0.81%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             349148      0.34%     99.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             109813      0.11%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      103600342                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      103893877                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 174041     19.05%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     19.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                435557     47.67%     66.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               304020     33.28%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 174329     19.02%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     19.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                437335     47.71%     66.72% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               305033     33.28%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             34383436     69.05%     69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               54432      0.11%     69.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              27661      0.06%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             8987932     18.05%     87.27% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5577936     11.20%     98.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            760973      1.53%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             34481483     69.03%     69.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               54630      0.11%     69.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              27712      0.06%     69.20% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.20% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.20% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.20% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9019851     18.06%     87.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5598402     11.21%     98.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            764115      1.53%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              49798033                       # Type of FU issued
-system.cpu0.iq.rate                          0.459151                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     913618                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.018346                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         203658933                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         58161397                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     48529720                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             503398                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            236532                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       231367                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              50437037                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 270834                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          558638                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              49951846                       # Type of FU issued
+system.cpu0.iq.rate                          0.459148                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     916697                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018352                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         204260867                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         58336070                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     48679612                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             506059                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            237571                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       232415                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              50592327                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 272446                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          560089                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1034329                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4271                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        17854                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       485625                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1038811                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4304                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        17864                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       487331                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18828                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       348593                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18869                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       349661                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                468306                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               44263410                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1515089                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           55600538                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           120472                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8791454                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5770533                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1526368                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 47186                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1245112                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         17854                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        151677                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       326896                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              478573                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             49327282                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8721913                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           470750                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                470580                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               44276704                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1577501                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           55768983                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           120052                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              8824182                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5791367                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1533608                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 47079                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1307470                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         17864                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        152204                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       328517                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              480721                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             49479281                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8753036                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           472564                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3192803                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14249477                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7854369                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5527564                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.454811                       # Inst execution rate
-system.cpu0.iew.wb_sent                      48871282                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     48761087                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 25232648                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 34850080                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3202362                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14301032                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7879408                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5547996                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.454804                       # Inst execution rate
+system.cpu0.iew.wb_sent                      49022541                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     48912027                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 25297454                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 34938196                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu0.iew.wb_rate                      0.449590                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.724034                       # average fanout of values written-back
+system.cpu0.iew.wb_fanout                    0.724063                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6529157                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         538982                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           437949                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    102449449                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.477940                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.411753                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6548409                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         541225                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           440159                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    102738863                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.478033                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.411836                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     85074848     83.04%     83.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      6905483      6.74%     89.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3794087      3.70%     93.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1998795      1.95%     95.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1509892      1.47%     96.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       553563      0.54%     97.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       413229      0.40%     97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       408476      0.40%     98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1791076      1.75%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     85310078     83.04%     83.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6928869      6.74%     89.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3804927      3.70%     93.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2004533      1.95%     95.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1514323      1.47%     96.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       555844      0.54%     97.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       414883      0.40%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       408778      0.40%     98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1796628      1.75%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    102449449                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            48964739                       # Number of instructions committed
-system.cpu0.commit.committedOps              48964739                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    102738863                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            49112602                       # Number of instructions committed
+system.cpu0.commit.committedOps              49112602                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13042033                       # Number of memory references committed
-system.cpu0.commit.loads                      7757125                       # Number of loads committed
-system.cpu0.commit.membars                     182252                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7421354                       # Number of branches committed
-system.cpu0.commit.fp_insts                    228314                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 45387875                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              614232                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2794177      5.71%      5.71% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        32097051     65.55%     71.26% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          53183      0.11%     71.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         27190      0.06%     71.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        7939377     16.21%     87.64% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5290905     10.81%     98.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       760973      1.55%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      13089407                       # Number of memory references committed
+system.cpu0.commit.loads                      7785371                       # Number of loads committed
+system.cpu0.commit.membars                     183023                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7443994                       # Number of branches committed
+system.cpu0.commit.fp_insts                    229281                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 45524861                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              617737                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2801788      5.70%      5.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        32185758     65.53%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          53394      0.11%     71.35% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.35% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         27239      0.06%     71.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        7968394     16.22%     87.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5310031     10.81%     98.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       764115      1.56%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         48964739                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1791076                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         49112602                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1796628                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   155949601                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  112132496                       # The number of ROB writes
-system.cpu0.timesIdled                         444606                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        4856365                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3701678908                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   46174329                       # Number of Instructions Simulated
-system.cpu0.committedOps                     46174329                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.348853                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.348853                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.425740                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.425740                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                65048250                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               35377381                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   113752                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  114375                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1675774                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                759002                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          1223787                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.953471                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9930066                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1224299                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.110818                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                   156399894                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  112470885                       # The number of ROB writes
+system.cpu0.timesIdled                         448982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        4898702                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3693581898                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   46314581                       # Number of Instructions Simulated
+system.cpu0.committedOps                     46314581                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.348992                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.348992                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.425715                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.425715                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                65241971                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               35484902                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   114300                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  114851                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1680980                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                762179                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          1226061                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.967877                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs            9972327                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1226573                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.130235                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         25151000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.953471                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988190                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988190                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.967877                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988219                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988219                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          236                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         53654077                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        53654077                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6167393                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6167393                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3426848                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3426848                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       149101                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       149101                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171294                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       171294                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9594241                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9594241                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9594241                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9594241                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1498647                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1498647                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1667216                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1667216                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        19081                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19081                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4721                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         4721                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3165863                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3165863                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3165863                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3165863                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39188841077                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  39188841077                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  77581958562                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  77581958562                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    288599741                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    288599741                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     35650235                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     35650235                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 116770799639                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 116770799639                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7666040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7666040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5094064                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5094064                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       168182                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       168182                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176015                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       176015                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12760104                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12760104                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12760104                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12760104                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.195492                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.195492                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.327286                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.327286                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113454                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113454                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026822                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026822                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248106                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.248106                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248106                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.248106                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26149.480883                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26149.480883                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46533.837584                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 46533.837584                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15124.979875                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7551.416014                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7551.416014                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      3791444                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2983                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           159835                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             87                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.720987                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    34.287356                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         53849509                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        53849509                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6192446                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6192446                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3442531                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3442531                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150135                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       150135                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       172107                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       172107                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9634977                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9634977                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9634977                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9634977                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1501821                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1501821                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1669841                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1669841                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        19141                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19141                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4636                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         4636                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3171662                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3171662                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3171662                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3171662                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39101656628                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  39101656628                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  78115764371                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  78115764371                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    290102987                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    290102987                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     35172730                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     35172730                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 117217420999                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 117217420999                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7694267                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7694267                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5112372                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5112372                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       169276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176743                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       176743                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12806639                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12806639                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12806639                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12806639                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.195187                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.195187                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.326627                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.326627                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113076                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113076                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026230                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026230                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.247658                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.247658                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.247658                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.247658                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7586.870147                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7586.870147                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      3837622                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         3343                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           160954                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             89                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.842974                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    37.561798                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       710527                       # number of writebacks
-system.cpu0.dcache.writebacks::total           710527                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       518299                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       518299                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1417662                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1417662                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4443                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4443                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1935961                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1935961                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1935961                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1935961                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       980348                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       980348                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249554                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249554                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14638                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14638                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4721                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         4721                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1229902                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1229902                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1229902                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1229902                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27067717433                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27067717433                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11277928082                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11277928082                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    147839258                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147839258                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     26206765                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     26206765                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38345645515                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  38345645515                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38345645515                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  38345645515                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1453124500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1453124500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2199080998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2199080998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3652205498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3652205498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127882                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127882                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048989                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048989                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087037                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087037                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026822                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026822                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096387                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096387                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096387                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096387                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5551.104639                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5551.104639                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       711843                       # number of writebacks
+system.cpu0.dcache.writebacks::total           711843                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       520027                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       520027                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1419840                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1419840                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4544                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4544                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1939867                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1939867                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1939867                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1939867                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       981794                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       981794                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       250001                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       250001                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14597                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14597                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4636                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         4636                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1231795                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1231795                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1231795                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1231795                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27071690424                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27071690424                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11368022018                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11368022018                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    148174261                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    148174261                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25899270                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25899270                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38439712442                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  38439712442                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38439712442                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  38439712442                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1458085000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1458085000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2211101998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2211101998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3669186998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3669186998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127601                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127601                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048901                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048901                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086232                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086232                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026230                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026230                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096184                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.096184                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096184                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.096184                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5586.555220                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5586.555220                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -827,126 +819,126 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           815495                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.595712                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            6922237                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           816007                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.483061                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           821620                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.585426                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            6946118                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           822130                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.448929                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      26485869250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.595712                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995304                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995304                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          411                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          8594091                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         8594091                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6922237                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6922237                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6922237                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6922237                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6922237                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6922237                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       855710                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       855710                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       855710                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        855710                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       855710                       # number of overall misses
-system.cpu0.icache.overall_misses::total       855710                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12231378721                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12231378721                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12231378721                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12231378721                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12231378721                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12231378721                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7777947                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7777947                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7777947                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7777947                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7777947                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7777947                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110017                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.110017                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110017                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.110017                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110017                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.110017                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14293.836371                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14293.836371                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4554                       # number of cycles access was blocked
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.585426                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995284                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.995284                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          431                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          8630516                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         8630516                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6946118                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6946118                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6946118                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6946118                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6946118                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6946118                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       862061                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       862061                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       862061                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        862061                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       862061                       # number of overall misses
+system.cpu0.icache.overall_misses::total       862061                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12338398473                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  12338398473                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  12338398473                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  12338398473                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  12338398473                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  12338398473                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7808179                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7808179                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7808179                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7808179                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7808179                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7808179                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110405                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.110405                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110405                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.110405                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110405                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.110405                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14312.674478                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14312.674478                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4878                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              181                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              185                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.160221                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.367568                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        39566                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        39566                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        39566                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        39566                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        39566                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        39566                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       816144                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       816144                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       816144                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       816144                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       816144                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       816144                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10088624022                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10088624022                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10088624022                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10088624022                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10088624022                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10088624022                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.104931                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.104931                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.104931                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.104931                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.104931                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.104931                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        39724                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        39724                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        39724                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        39724                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        39724                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        39724                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       822337                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       822337                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       822337                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       822337                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       822337                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       822337                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10177943027                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10177943027                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10177943027                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10177943027                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10177943027                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10177943027                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105317                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.105317                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.105317                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                4639832                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          4063901                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            82203                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2874870                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1132301                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4575539                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          4011453                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            80159                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2846769                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1118608                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            39.386164                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 224009                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              7064                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            39.293950                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 219011                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              6943                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2413283                       # DTB read hits
-system.cpu1.dtb.read_misses                     10075                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  292262                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1597058                       # DTB write hits
-system.cpu1.dtb.write_misses                     2093                       # DTB write misses
-system.cpu1.dtb.write_acv                          37                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 110264                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4010341                       # DTB hits
-system.cpu1.dtb.data_misses                     12168                       # DTB misses
+system.cpu1.dtb.read_hits                     2376918                       # DTB read hits
+system.cpu1.dtb.read_misses                      9978                       # DTB read misses
+system.cpu1.dtb.read_acv                            5                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  290947                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1576285                       # DTB write hits
+system.cpu1.dtb.write_misses                     2026                       # DTB write misses
+system.cpu1.dtb.write_acv                          38                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 109535                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3953203                       # DTB hits
+system.cpu1.dtb.data_misses                     12004                       # DTB misses
 system.cpu1.dtb.data_acv                           43                       # DTB access violations
-system.cpu1.dtb.data_accesses                  402526                       # DTB accesses
-system.cpu1.itb.fetch_hits                     608432                       # ITB hits
-system.cpu1.itb.fetch_misses                     5602                       # ITB misses
-system.cpu1.itb.fetch_acv                          65                       # ITB acv
-system.cpu1.itb.fetch_accesses                 614034                       # ITB accesses
+system.cpu1.dtb.data_accesses                  400482                       # DTB accesses
+system.cpu1.itb.fetch_hits                     602928                       # ITB hits
+system.cpu1.itb.fetch_misses                     5576                       # ITB misses
+system.cpu1.itb.fetch_acv                          51                       # ITB acv
+system.cpu1.itb.fetch_accesses                 608504                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -959,257 +951,257 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        19085086                       # number of cpu cycles simulated
+system.cpu1.numCycles                        18735029                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8490084                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      17874574                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4639832                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1356310                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9216388                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 327612                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles               26792                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       219924                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        67319                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1967111                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                67009                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          18184335                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.982966                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.394246                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           8327481                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      17619609                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4575539                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1337619                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      9079051                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 321428                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               26636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       222369                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        65129                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1934705                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                65647                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          17881393                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.985360                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.396691                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                15065350     82.85%     82.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  205923      1.13%     83.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  307986      1.69%     85.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  226074      1.24%     86.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  391185      2.15%     89.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  151633      0.83%     89.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  170482      0.94%     90.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  296956      1.63%     92.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1368746      7.53%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                14806869     82.81%     82.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  203122      1.14%     83.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  303524      1.70%     85.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  223355      1.25%     86.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  384843      2.15%     89.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  149669      0.84%     89.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  166893      0.93%     90.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  294645      1.65%     92.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1348473      7.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            18184335                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.243113                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.936573                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 6979571                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8518725                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2274233                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               256003                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                155802                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              137194                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 8084                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              14619784                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                26597                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                155802                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 7159934                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 614392                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6924569                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2350603                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               979033                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              13886683                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 9133                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 71770                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 16856                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                365854                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            9047331                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             16422939                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        16337871                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            78141                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              7835755                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1211576                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            562751                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         58900                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2353285                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2494844                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1679253                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           277357                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          156260                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  12201401                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             661557                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 11978627                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            22551                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1735034                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       788886                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        473891                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     18184335                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.658733                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.375592                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            17881393                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.244224                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.940463                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6834927                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              8400269                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2240291                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               252863                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                153042                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              134285                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 7749                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              14408505                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                25621                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                153042                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 7012697                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 586426                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       6840794                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2316099                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               972333                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              13683407                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 9781                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 69005                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 16467                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                367791                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            8910587                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             16181694                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        16097130                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            77675                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              7724005                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1186582                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            556647                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         57942                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2323703                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2456737                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1657029                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           275399                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          155321                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  12021391                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             653222                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 11806375                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            22216                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1705669                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       770229                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        468205                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     17881393                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.660260                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.377042                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           13164849     72.40%     72.40% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2231541     12.27%     84.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             929377      5.11%     89.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             639609      3.52%     93.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             582340      3.20%     96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             317160      1.74%     98.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             211313      1.16%     99.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              78701      0.43%     99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              29445      0.16%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           12935770     72.34%     72.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2198264     12.29%     84.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             914656      5.12%     89.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             630896      3.53%     93.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             572849      3.20%     96.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             314457      1.76%     98.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             208202      1.16%     99.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              77174      0.43%     99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              29125      0.16%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       18184335                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       17881393                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  24291      8.14%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                162499     54.43%     62.57% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               111756     37.43%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  23808      8.12%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                159009     54.21%     62.33% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               110483     37.67%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass             3518      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7464610     62.32%     62.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               20078      0.17%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              12377      0.10%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2524426     21.07%     83.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1623488     13.55%     97.26% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            328371      2.74%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              7355530     62.30%     62.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               19854      0.17%     62.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.50% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              12327      0.10%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2486397     21.06%     83.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1602376     13.57%     97.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            324614      2.75%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              11978627                       # Type of FU issued
-system.cpu1.iq.rate                          0.627643                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     298546                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.024923                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          42145115                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         14453685                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     11556214                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             317571                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            148430                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       146304                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              12102736                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 170919                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          117615                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              11806375                       # Type of FU issued
+system.cpu1.iq.rate                          0.630176                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     293300                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.024843                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          41494201                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         14236824                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     11389686                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             315458                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            147457                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       145351                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              11926347                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 169810                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          115792                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       314973                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         1097                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4259                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       145447                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       308768                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1081                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         4102                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       143102                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          424                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        56672                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          395                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        55406                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                155802                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 328818                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               249531                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           13597003                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            38106                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2494844                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1679253                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            593871                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4649                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               243688                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4259                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         37580                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       120039                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              157619                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             11824953                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2433073                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           153674                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                153042                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 303896                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               248843                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           13398271                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            36703                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2456737                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1657029                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            586577                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  4501                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               243181                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          4102                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         36741                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       118067                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              154808                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             11654930                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2396476                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           151445                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       734045                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     4040076                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1766091                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1607003                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.619591                       # Inst execution rate
-system.cpu1.iew.wb_sent                      11733612                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     11702518                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5498346                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7839453                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       723658                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3982565                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1739472                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1586089                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.622093                       # Inst execution rate
+system.cpu1.iew.wb_sent                      11565622                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     11535037                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5422471                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  7736628                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.613176                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.701369                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.615694                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.700883                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1874564                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         187666                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           145503                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     17835799                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.653281                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.639800                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1839025                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         185017                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           142916                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     17538839                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.655077                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.643008                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     13664737     76.61%     76.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1906046     10.69%     87.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       699754      3.92%     91.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       424730      2.38%     93.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       316948      1.78%     95.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       133544      0.75%     96.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       114109      0.64%     96.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       155571      0.87%     97.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       420360      2.36%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     13431880     76.58%     76.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1875136     10.69%     87.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       688221      3.92%     91.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       418119      2.38%     93.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       312509      1.78%     95.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       131127      0.75%     96.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       110360      0.63%     96.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       156367      0.89%     97.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       415120      2.37%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     17835799                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            11651787                       # Number of instructions committed
-system.cpu1.commit.committedOps              11651787                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     17538839                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            11489295                       # Number of instructions committed
+system.cpu1.commit.committedOps              11489295                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3713677                       # Number of memory references committed
-system.cpu1.commit.loads                      2179871                       # Number of loads committed
-system.cpu1.commit.membars                      62781                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1664922                       # Number of branches committed
-system.cpu1.commit.fp_insts                    144632                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 10748857                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              187454                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       614300      5.27%      5.27% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         6897823     59.20%     64.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          19873      0.17%     64.64% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.64% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         12372      0.11%     64.75% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.75% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.75% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.75% # Class of committed instruction
+system.cpu1.commit.refs                       3661896                       # Number of memory references committed
+system.cpu1.commit.loads                      2147969                       # Number of loads committed
+system.cpu1.commit.membars                      61867                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1640602                       # Number of branches committed
+system.cpu1.commit.fp_insts                    143665                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 10598150                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              183822                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       606334      5.28%      5.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         6800030     59.19%     64.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          19654      0.17%     64.63% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.63% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         12323      0.11%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.74% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.74% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.76% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.76% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.76% # Class of committed instruction
@@ -1232,190 +1224,190 @@ system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.76%
 system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.76% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.76% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        2242652     19.25%     84.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1534637     13.17%     97.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       328371      2.82%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        2209836     19.23%     83.99% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1514745     13.18%     97.17% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       324614      2.83%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         11651787                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               420360                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         11489295                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               415120                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    30855147                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   27397116                       # The number of ROB writes
-system.cpu1.timesIdled                         166983                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         900751                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3790431319                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   11041005                       # Number of Instructions Simulated
-system.cpu1.committedOps                     11041005                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.728564                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.728564                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.578515                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.578515                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                15169687                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                8276758                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    77475                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   77542                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                1124650                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                280447                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           140166                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          492.227589                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3241153                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           140473                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.073139                       # Average number of references to valid blocks.
+system.cpu1.rob.rob_reads                    30366198                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   26995045                       # The number of ROB writes
+system.cpu1.timesIdled                         163095                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         853636                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3782985916                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   10886479                       # Number of Instructions Simulated
+system.cpu1.committedOps                     10886479                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.720945                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.720945                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.581076                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.581076                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                14951888                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                8155185                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    77020                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   77068                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                1117526                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                276759                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           138501                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          492.617684                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3193598                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           138812                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.006642                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle      39570817000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.227589                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.961382                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.961382                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          307                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.599609                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         15302146                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        15302146                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1936775                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1936775                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1212075                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1212075                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        45668                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        45668                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        44613                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        44613                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3148850                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3148850                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3148850                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3148850                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       269383                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       269383                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       265424                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       265424                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8139                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8139                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         4996                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         4996                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       534807                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        534807                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       534807                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       534807                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4084517434                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   4084517434                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8552113041                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8552113041                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     77678496                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     77678496                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     36778735                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     36778735                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  12636630475                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12636630475                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  12636630475                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12636630475                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2206158                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2206158                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1477499                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1477499                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        53807                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        53807                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        49609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        49609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3683657                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3683657                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3683657                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3683657                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.122105                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.122105                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.179644                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.179644                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.151263                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.151263                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100708                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100708                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.145184                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.145184                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.145184                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.145184                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15162.491449                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15162.491449                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32220.571768                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32220.571768                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9543.985256                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9543.985256                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7361.636309                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7361.636309                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23628.393935                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23628.393935                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23628.393935                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23628.393935                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       376916                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          344                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            18544                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets             11                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.325496                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    31.272727                       # average number of cycles each access was blocked
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.617684                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.962144                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.962144                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         15087685                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        15087685                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1906947                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1906947                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1195571                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1195571                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        44901                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        44901                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        43886                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        43886                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3102518                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3102518                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3102518                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3102518                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       266692                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       266692                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       262982                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       262982                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8052                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8052                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         4916                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         4916                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       529674                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        529674                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       529674                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       529674                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4020623652                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   4020623652                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8531401983                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   8531401983                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     76759992                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     76759992                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     36344731                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     36344731                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  12552025635                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  12552025635                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  12552025635                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  12552025635                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2173639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2173639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1458553                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1458553                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        52953                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        52953                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        48802                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        48802                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3632192                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3632192                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3632192                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3632192                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.122694                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.122694                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.180303                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.180303                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152059                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152059                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100734                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100734                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.145828                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.145828                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.145828                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.145828                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9533.034277                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9533.034277                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7393.151139                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7393.151139                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       379144                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          215                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            18342                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              9                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.670810                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    23.888889                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        94206                       # number of writebacks
-system.cpu1.dcache.writebacks::total            94206                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       165989                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       165989                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       215339                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       215339                       # number of WriteReq MSHR hits
+system.cpu1.dcache.writebacks::writebacks        93139                       # number of writebacks
+system.cpu1.dcache.writebacks::total            93139                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       164682                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       164682                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       213530                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       213530                       # number of WriteReq MSHR hits
 system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          655                       # number of LoadLockedReq MSHR hits
 system.cpu1.dcache.LoadLockedReq_mshr_hits::total          655                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       381328                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       381328                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       381328                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       381328                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       103394                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       103394                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        50085                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        50085                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7484                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7484                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         4996                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         4996                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       153479                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       153479                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       153479                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       153479                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1212902508                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1212902508                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1317911046                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1317911046                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     54853004                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     54853004                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     26784265                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     26784265                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2530813554                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2530813554                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2530813554                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2530813554                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     29140000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     29140000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    708818500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    708818500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    737958500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    737958500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.046866                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.046866                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033899                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033899                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.139090                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.139090                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100708                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100708                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041665                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.041665                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041665                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.041665                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11730.879045                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11730.879045                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7329.369856                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7329.369856                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5361.141914                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5361.141914                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16489.640628                       # average overall mshr miss latency
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       378212                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       378212                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       378212                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       378212                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       102010                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       102010                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        49452                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        49452                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7397                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7397                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         4916                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         4916                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       151462                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       151462                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       151462                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       151462                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1194457513                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1194457513                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1312928589                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1312928589                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     54001007                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     54001007                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     26510269                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     26510269                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2507386102                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2507386102                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2507386102                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2507386102                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     24847500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     24847500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    692513000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    692513000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    717360500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    717360500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.046931                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.046931                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033905                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033905                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.139690                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.139690                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100734                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100734                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041700                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.041700                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041700                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.041700                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7300.392997                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7300.392997                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5392.650325                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5392.650325                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1423,94 +1415,95 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           312757                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          471.042243                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1644085                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           313269                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             5.248157                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1879134143250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   471.042243                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.920004                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.920004                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          2280436                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         2280436                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1644085                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1644085                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1644085                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1644085                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1644085                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1644085                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       323026                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       323026                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       323026                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        323026                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       323026                       # number of overall misses
-system.cpu1.icache.overall_misses::total       323026                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4370273976                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4370273976                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4370273976                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4370273976                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4370273976                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4370273976                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1967111                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1967111                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1967111                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1967111                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1967111                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1967111                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.164213                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.164213                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.164213                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.164213                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.164213                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.164213                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.170952                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.170952                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.170952                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13529.170952                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.170952                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13529.170952                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          341                       # number of cycles access was blocked
+system.cpu1.icache.tags.replacements           306147                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          470.962529                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1618659                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           306656                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             5.278419                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1878409820250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.962529                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919849                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.919849                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          2241410                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2241410                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1618659                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1618659                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1618659                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1618659                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1618659                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1618659                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       316046                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       316046                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       316046                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        316046                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       316046                       # number of overall misses
+system.cpu1.icache.overall_misses::total       316046                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4251188208                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4251188208                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4251188208                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4251188208                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4251188208                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4251188208                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1934705                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1934705                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1934705                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1934705                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1934705                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1934705                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.163356                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.163356                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.163356                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.163356                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.163356                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.163356                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13451.169159                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13451.169159                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          528                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               24                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               26                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.208333                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.307692                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9701                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         9701                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         9701                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         9701                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         9701                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         9701                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       313325                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       313325                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       313325                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       313325                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       313325                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       313325                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3639863451                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3639863451                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3639863451                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3639863451                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3639863451                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3639863451                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.159282                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.159282                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.159282                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.159282                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.159282                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.159282                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9341                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         9341                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         9341                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         9341                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         9341                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         9341                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       306705                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       306705                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       306705                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       306705                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       306705                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       306705                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3543296218                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3543296218                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3543296218                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3543296218                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3543296218                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3543296218                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.158528                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.158528                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.158528                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1524,13 +1517,13 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7369                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7369                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55215                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55217                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            2                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          464                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7368                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7368                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               55198                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              13646                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13082                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -1541,12 +1534,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        41714                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83458                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83458                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125172                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        52504                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        41682                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  125132                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        52328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -1557,13 +1550,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        78682                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2740322                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             12481000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        78554                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2740162                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             12437000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               347000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               356000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1583,277 +1576,285 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           374418188                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406224779                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28049000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28036000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42021755                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42010550                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41697                       # number of replacements
-system.iocache.tags.tagsinuse                0.496947                       # Cycle average of tags in use
+system.iocache.tags.replacements                41693                       # number of replacements
+system.iocache.tags.tagsinuse                0.465320                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41713                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41709                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1710336805000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.496947                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.031059                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.031059                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1710336865000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.465320                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.029083                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.029083                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375577                       # Number of tag accesses
-system.iocache.tags.data_accesses              375577                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          177                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide            2                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total            2                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::tsunami.ide          177                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               177                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          177                       # number of overall misses
-system.iocache.overall_misses::total              177                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21586383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21586383                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21586383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21586383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21586383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21586383                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          177                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41554                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41554                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          177                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             177                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          177                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            177                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13658910846                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13658910846                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21134383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21134383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21134383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21134383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide     0.000048                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000048                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 121956.966102                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121956.966102                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121956.966102                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122164.063584                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122164.063584                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        207096                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23572                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.785678                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide          177                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          177                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          177                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          177                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          177                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          177                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12381383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12381383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2512854560                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2512854560                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12381383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12381383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12381383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12381383                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11498106946                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11498106946                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12137383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12137383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12137383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12137383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 69951.316384                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 69951.316384                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70158.283237                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70158.283237                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   344236                       # number of replacements
-system.l2c.tags.tagsinuse                65255.823465                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2587778                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   409374                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.321305                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   345011                       # number of replacements
+system.l2c.tags.tagsinuse                65255.839207                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2587062                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   410177                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.307184                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               7093665750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53392.763161                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5322.213179                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6227.888257                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      220.740542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       92.218326                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.814709                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081211                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.095030                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003368                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001407                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   53401.606938                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5320.695867                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6228.167915                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      214.693065                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       90.675422                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.814844                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.081187                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.095034                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003276                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.001384                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.995725                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65138                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         3694                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         4797                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4255                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52162                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.993927                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27098951                       # Number of tag accesses
-system.l2c.tags.data_accesses                27098951                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             802459                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             696077                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             311437                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              94339                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1904312                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          804733                       # number of Writeback hits
-system.l2c.Writeback_hits::total               804733                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             166                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             431                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 597                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            52                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            26                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                78                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           138280                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            34809                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               173089                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              802459                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              834357                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              311437                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              129148                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2077401                       # number of demand (read+write) hits
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1862,8 +1863,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadReq_mshr_hits::cpu0.inst            13                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
@@ -1876,111 +1877,111 @@ system.l2c.overall_mshr_hits::cpu0.inst            13                       # nu
 system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    652738500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2737842500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3451304000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    675896000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4127200000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016852                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.281490                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004911                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008877                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.131938                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.943328                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.779487                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.879238                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.934699                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.972477                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.953368                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.453705                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.177344                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.414250                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016852                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.317021                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004911                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.060898                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.165338                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016852                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.317021                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004911                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.060898                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.165338                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64153.933598                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53203.687233                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67803.784861                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77327.544910                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53873.489594                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10070.330073                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.284868                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.749030                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.557534                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.812668                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.108696                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70651.476086                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94651.507515                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72118.346984                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64153.933598                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58355.538817                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67803.784861                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92905.941113                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59281.513821                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64153.933598                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58355.538817                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67803.784861                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92905.941113                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59281.513821                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1991,101 +1992,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              296853                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296773                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13665                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13665                       # Transaction distribution
-system.membus.trans_dist::Writeback             80589                       # Transaction distribution
+system.membus.trans_dist::ReadReq              296777                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296698                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13646                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13646                       # Transaction distribution
+system.membus.trans_dist::Writeback            123016                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            14563                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           9639                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            6364                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            121274                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           120582                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           80                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        41714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       931819                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       973693                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83296                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83296                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1056989                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        78682                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31396800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31475482                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34135770                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            18692                       # Total snoops (count)
-system.membus.snoop_fanout::samples            557285                       # Request fanout histogram
+system.membus.trans_dist::UpgradeReq            14268                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           9480                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            6314                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122151                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121466                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           79                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        41682                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       933549                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          158                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       975389                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1100201                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        78554                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31488576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31567130                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36884698                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            18563                       # Total snoops (count)
+system.membus.snoop_fanout::samples            600049                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  557285    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  600049    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              557285                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40450499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              600049                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40411498                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1545398747                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1927899500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              102000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               99500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3825672402                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3832783452                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43153245                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43159450                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2231724                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2231628                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13665                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13665                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           804733                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        41559                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           14709                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          9717                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          24426                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295921                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295921                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           80                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1632137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3219560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       626624                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       407513                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5885834                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     52223552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    123671600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20051136                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     14868394                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              210814682                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           92075                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3391171                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.012307                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.110253                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2231232                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2231137                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13646                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13646                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           804982                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           14411                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          9552                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          23963                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296031                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296031                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           79                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1644513                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3224840                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       613391                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       402307                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5885051                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     52619264                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    123882452                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19627904                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     14694726                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              210824346                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           91368                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3390565                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.012306                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.110249                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3349435     98.77%     98.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41736      1.23%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                3348840     98.77%     98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  41725      1.23%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3391171                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4911486557                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3390565                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4912159072                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           706500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3677796473                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3705712969                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5655554210                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        5664612723                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1411093549                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy        1381251781                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         701201756                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         692182943                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2119,161 +2120,161 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6701                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    170162                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   59106     40.33%     40.33% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.42% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1925      1.31%     41.73% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    339      0.23%     41.96% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  85060     58.04%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              146561                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    58406     49.14%     49.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce                    6735                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    170888                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   59399     40.36%     40.36% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.45% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1921      1.31%     41.76% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    339      0.23%     41.99% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  85372     58.01%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              147162                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    58699     49.14%     49.14% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.11%     49.25% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1925      1.62%     50.86% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     339      0.29%     51.15% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   58067     48.85%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               118868                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1864755925000     97.88%     97.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               61031500      0.00%     97.89% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              543238000      0.03%     97.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              152147500      0.01%     97.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            39554606000      2.08%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1905066948000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.988157                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1921      1.61%     50.86% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     339      0.28%     51.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   58360     48.86%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               119450                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1860822176500     97.88%     97.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               61176000      0.00%     97.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              541931500      0.03%     97.91% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              152116500      0.01%     97.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            39608995500      2.08%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1901186396000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.988215                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682659                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811048                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.67%     28.44% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.44%     28.89% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.00%     32.89% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.44%     37.33% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.67%     40.00% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.44%     40.44% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.33%     41.78% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.11%     44.89% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.89%     45.78% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     16.00%     61.78% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.33%     63.11% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.44%     67.56% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.44%     72.00% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.44%     72.44% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.67%     75.11% # number of syscalls executed
-system.cpu0.kern.syscall::71                       25     11.11%     86.22% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.33%     87.56% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.67%     90.22% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.44%     90.67% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.33%     92.00% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.00%     96.00% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.89%     96.89% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.89%     97.78% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.44%     98.22% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.89%     99.11% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.683596                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811691                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
+system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
+system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
+system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
+system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
+system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  439      0.28%      0.28% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  432      0.28%      0.28% # number of callpals executed
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.28% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3223      2.08%      2.37% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.28% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.28% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3241      2.09%      2.37% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      50      0.03%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.41% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               139738     90.30%     92.70% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6333      4.09%     96.79% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.40% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               140334     90.29%     92.69% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6381      4.11%     96.80% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.80% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.80% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.01%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4427      2.86%     99.66% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 382      0.25%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.81% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4436      2.85%     99.66% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 391      0.25%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                154756                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6973                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1341                       # number of protection mode switches
+system.cpu0.kern.callpal::total                155429                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7000                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1355                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1340                      
-system.cpu0.kern.mode_good::user                 1341                      
+system.cpu0.kern.mode_good::kernel               1354                      
+system.cpu0.kern.mode_good::user                 1355                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.192170                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.193429                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.322468                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1903068198000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1998742000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.324237                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1899184407000     99.89%     99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2001981000      0.11%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3224                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3242                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2621                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     71304                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   23839     38.11%     38.11% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1924      3.08%     41.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    439      0.70%     41.89% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  36346     58.11%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               62548                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    23162     48.01%     48.01% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1924      3.99%     51.99% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     439      0.91%     52.90% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   22723     47.10%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                48248                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1872982420000     98.33%     98.33% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              531501500      0.03%     98.36% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              197949500      0.01%     98.37% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            31046317000      1.63%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1904758188000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.971601                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2589                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     70429                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   23508     38.03%     38.03% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1920      3.11%     41.14% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    432      0.70%     41.84% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  35949     58.16%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               61809                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    22831     47.98%     47.98% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1920      4.04%     52.02% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     432      0.91%     52.93% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   22399     47.07%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                47582                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1869145937500     98.33%     98.33% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              530408500      0.03%     98.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              194479500      0.01%     98.37% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            30989632500      1.63%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900860458000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.971201                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.625186                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.771376                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.94%     26.73% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.97%     29.70% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.97%     32.67% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.96%     36.63% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     17.82%     54.46% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.97%     57.43% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.99%     58.42% # number of syscalls executed
-system.cpu1.kern.syscall::71                       29     28.71%     87.13% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      9.90%     97.03% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.623077                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.769823                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
+system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
+system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
+system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
+system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  339      0.52%      0.52% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  339      0.53%      0.53% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.53% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.53% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1674      2.58%      3.11% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.11% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.13% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                56749     87.55%     90.68% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2425      3.74%     94.42% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.42% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.42% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.43% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3435      5.30%     99.73% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 133      0.21%     99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1656      2.59%      3.12% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      3.13% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.14% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                56045     87.56%     90.70% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2366      3.70%     94.40% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.40% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     94.41% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.41% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3411      5.33%     99.74% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 124      0.19%     99.93% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.07%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 64819                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1725                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                395                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2719                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                758                      
-system.cpu1.kern.mode_good::user                  395                      
-system.cpu1.kern.mode_good::idle                  363                      
-system.cpu1.kern.mode_switch_good::kernel     0.439420                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 64005                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1702                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                384                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2700                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                740                      
+system.cpu1.kern.mode_good::user                  384                      
+system.cpu1.kern.mode_good::idle                  356                      
+system.cpu1.kern.mode_switch_good::kernel     0.434783                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.133505                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.313288                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        6292990000      0.33%      0.33% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           709362000      0.04%      0.37% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1897439269000     99.63%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1675                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.131852                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.309235                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        6130779500      0.32%      0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           692688500      0.04%      0.36% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893719133000     99.64%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1657                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 987719302..44e9b2e2b 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,114 +1,111 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.859039                       # Number of seconds simulated
-sim_ticks                                1859038679000                       # Number of ticks simulated
-final_tick                               1859038679000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.859049                       # Number of seconds simulated
+sim_ticks                                1859049148500                       # Number of ticks simulated
+final_tick                               1859049148500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164458                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164458                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5776457310                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314484                       # Number of bytes of host memory used
-host_seconds                                   321.83                       # Real time elapsed on the host
-sim_insts                                    52927600                       # Number of instructions simulated
-sim_ops                                      52927600                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 168870                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168870                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5931192571                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320216                       # Number of bytes of host memory used
+host_seconds                                   313.44                       # Real time elapsed on the host
+sim_insts                                    52930035                       # Number of instructions simulated
+sim_ops                                      52930035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            968256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24892608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            967168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24875776                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25861824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       968256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          968256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4860032                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7519360                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15129                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388947                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25843904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       967168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          967168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7516224                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7516224                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15112                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388684                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404091                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           75938                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117490                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               520837                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13390043                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403811                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117441                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117441                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               520249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13380914                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13911396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          520837                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             520837                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2614272                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1430486                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4044757                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2614272                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              520837                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13390043                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1431002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17956154                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404091                       # Number of read requests accepted
-system.physmem.writeReqs                       117490                       # Number of write requests accepted
-system.physmem.readBursts                      404091                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117490                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25850368                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11456                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7517888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25861824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7519360                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      179                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            193                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25747                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25572                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25523                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25355                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25392                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24811                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25029                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25134                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24968                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25052                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25439                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24779                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24568                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25250                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25688                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25605                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8041                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7603                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7894                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7385                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7327                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6730                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6858                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6765                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7133                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6722                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7301                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6871                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7190                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7853                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7964                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7830                       # Per bank write bursts
+system.physmem.bw_read::total                13901679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          520249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             520249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4043047                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4043047                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4043047                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              520249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13380914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17944726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403811                       # Number of read requests accepted
+system.physmem.writeReqs                       158993                       # Number of write requests accepted
+system.physmem.readBursts                      403811                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     158993                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25836928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10037376                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25843904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10175552                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2130                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            189                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25744                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25560                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25512                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25342                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25388                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24802                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25022                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25128                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24929                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25033                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25435                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24778                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24542                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25239                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25649                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25599                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10531                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10049                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10576                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9740                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9614                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9115                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9087                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8933                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9694                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8895                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9699                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9449                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10004                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10709                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10413                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10326                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1859033424000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1859043836000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404091                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403811                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117490                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315071                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     37620                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     42963                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 158993                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    314947                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     37560                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     42912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        57                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -151,344 +148,189 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3979                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5517                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6788                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      496                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      430                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      156                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61280                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      544.521149                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     334.160448                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     418.029082                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13483     22.00%     22.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10372     16.93%     38.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4758      7.76%     46.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2785      4.54%     51.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2293      3.74%     54.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1673      2.73%     57.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1477      2.41%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1592      2.60%     62.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22847     37.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61280                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5232                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.198394                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2919.153555                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5229     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::48                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63789                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      562.390130                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     348.747922                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.715872                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13502     21.17%     21.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10319     16.18%     37.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4795      7.52%     44.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2857      4.48%     49.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2332      3.66%     53.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1655      2.59%     55.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1501      2.35%     57.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1587      2.49%     60.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25241     39.57%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63789                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5661                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.309309                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2806.420357                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5658     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5232                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5232                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.451644                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.067800                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.155033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4469     85.42%     85.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             138      2.64%     88.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              12      0.23%     88.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             232      4.43%     92.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              44      0.84%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               2      0.04%     93.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               5      0.10%     93.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              10      0.19%     93.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              17      0.32%     94.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.04%     94.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.02%     94.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.04%     94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               7      0.13%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.06%     94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.08%     94.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.02%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              28      0.54%     95.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              15      0.29%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              15      0.29%     95.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             171      3.27%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.11%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.04%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.04%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.10%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             6      0.11%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.08%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            11      0.21%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             7      0.13%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5232                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3681492750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11254842750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2019560000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9114.59                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5661                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5661                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.704293                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.909682                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       34.456612                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4621     81.63%     81.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             191      3.37%     85.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             281      4.96%     89.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              54      0.95%     90.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              96      1.70%     92.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              48      0.85%     93.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              17      0.30%     93.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              14      0.25%     94.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              19      0.34%     94.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.09%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             15      0.26%     94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.07%     94.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             5      0.09%     94.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.04%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            19      0.34%     95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            42      0.74%     95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            21      0.37%     96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            11      0.19%     96.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            96      1.70%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            35      0.62%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            14      0.25%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            13      0.23%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            10      0.18%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.09%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             5      0.09%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.04%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             5      0.09%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             6      0.11%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             2      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5661                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3666880250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11236292750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018510000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9083.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27864.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.91                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.91                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27833.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.40                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.47                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.92                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364830                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95269                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.32                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3564227.65                       # Average gap between requests
-system.physmem.pageHitRate                      88.24                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1761056207000                       # Time in different power states
-system.physmem.memoryStateTime::REF       62077340000                       # Time in different power states
+system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364667                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    132080                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.20                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3303181.63                       # Average gap between requests
+system.physmem.pageHitRate                      88.62                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1760890123500                       # Time in different power states
+system.physmem.memoryStateTime::REF       62077600000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       35903990500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       36077600250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 230322960                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 232953840                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 125672250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 127107750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1579991400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1570522200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               379747440                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               381438720                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          121423277040                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          121423277040                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           55561357620                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           55436078745                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1066684481250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1066794375000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1245984849960                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1245965753295                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.231146                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.220874                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              296046                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295957                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback             75938                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              188                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              5                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             193                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115222                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115222                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           89                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884476                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          178                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917708                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1001000                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30720896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30765036                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33425324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              158                       # Total snoops (count)
-system.membus.snoop_fanout::samples            522030                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  522030    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              522030                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            31457000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1484421249                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              110500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3754388311                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43151211                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.260487                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1709355301000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.260487                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078780                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078780                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               376213                       # Number of tag accesses
-system.iocache.tags.data_accesses              376213                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide           86                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           86                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41638                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41638                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide     0.002065                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.002065                       # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2529714027                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2529714027                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                17804968                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15499600                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            379466                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11923628                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5932721                       # Number of BTB hits
+system.physmem.actEnergy::0                 239795640                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 242449200                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 130840875                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 132288750                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1579484400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1569391200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               503139600                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               513144720                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          121423785600                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          121423785600                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           55719498420                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           55486362150                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1066550433000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1066754938500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1246146977535                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1246122360120                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             670.315549                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.302307                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                17761302                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15456576                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            379954                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12009119                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5937139                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             49.756005                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  914118                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21281                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             49.438589                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  914399                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21305                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10302215                       # DTB read hits
-system.cpu.dtb.read_misses                      41309                       # DTB read misses
-system.cpu.dtb.read_acv                           513                       # DTB read access violations
-system.cpu.dtb.read_accesses                   965594                       # DTB read accesses
-system.cpu.dtb.write_hits                     6646492                       # DTB write hits
-system.cpu.dtb.write_misses                      9371                       # DTB write misses
-system.cpu.dtb.write_acv                          419                       # DTB write access violations
-system.cpu.dtb.write_accesses                  342338                       # DTB write accesses
-system.cpu.dtb.data_hits                     16948707                       # DTB hits
-system.cpu.dtb.data_misses                      50680                       # DTB misses
-system.cpu.dtb.data_acv                           932                       # DTB access violations
-system.cpu.dtb.data_accesses                  1307932                       # DTB accesses
-system.cpu.itb.fetch_hits                     1774610                       # ITB hits
-system.cpu.itb.fetch_misses                     34401                       # ITB misses
-system.cpu.itb.fetch_acv                          653                       # ITB acv
-system.cpu.itb.fetch_accesses                 1809011                       # ITB accesses
+system.cpu.dtb.read_hits                     10308188                       # DTB read hits
+system.cpu.dtb.read_misses                      41379                       # DTB read misses
+system.cpu.dtb.read_acv                           521                       # DTB read access violations
+system.cpu.dtb.read_accesses                   967155                       # DTB read accesses
+system.cpu.dtb.write_hits                     6646702                       # DTB write hits
+system.cpu.dtb.write_misses                      9325                       # DTB write misses
+system.cpu.dtb.write_acv                          410                       # DTB write access violations
+system.cpu.dtb.write_accesses                  342603                       # DTB write accesses
+system.cpu.dtb.data_hits                     16954890                       # DTB hits
+system.cpu.dtb.data_misses                      50704                       # DTB misses
+system.cpu.dtb.data_acv                           931                       # DTB access violations
+system.cpu.dtb.data_accesses                  1309758                       # DTB accesses
+system.cpu.itb.fetch_hits                     1770443                       # ITB hits
+system.cpu.itb.fetch_misses                     36092                       # ITB misses
+system.cpu.itb.fetch_acv                          664                       # ITB acv
+system.cpu.itb.fetch_accesses                 1806535                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -501,254 +343,254 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        118301061                       # number of cpu cycles simulated
+system.cpu.numCycles                        118298016                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29562966                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       78094807                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17804968                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6846839                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      80553195                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1252096                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1416                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27926                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1649882                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       450417                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          232                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9025532                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                274121                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          112872082                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.691888                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.011514                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29541198                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78055768                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17761302                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6851538                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80476428                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1253224                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1384                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28562                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1737629                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       451562                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          217                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9019799                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                273133                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          112863592                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.691594                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.010851                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 98296528     87.09%     87.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   933530      0.83%     87.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1975700      1.75%     89.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   908755      0.81%     90.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2800334      2.48%     92.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   638924      0.57%     93.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   725896      0.64%     94.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1007040      0.89%     95.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5585375      4.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 98289284     87.09%     87.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   935566      0.83%     87.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1976201      1.75%     89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   911928      0.81%     90.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2795335      2.48%     92.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   642698      0.57%     93.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   727750      0.64%     94.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1007954      0.89%     95.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5576876      4.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            112872082                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.150506                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.660136                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24068860                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              76820836                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9500551                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1898196                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 583638                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               588301                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42850                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68299285                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                133126                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 583638                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24994916                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                47249741                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20742683                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10385328                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8915774                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65865702                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                202022                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2036806                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 141544                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4770005                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43944287                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79812474                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79631676                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168345                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38137411                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5806868                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1690855                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         241233                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13548292                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10425085                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6927485                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1490397                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1054253                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58626057                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2139161                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57592696                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             51229                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7502337                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3486338                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1478017                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     112872082                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.510247                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.252928                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            112863592                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.150140                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.659823                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24058379                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              76821722                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9496623                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1902660                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 584207                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               588094                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42817                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68303161                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                133250                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 584207                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24982800                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                47259981                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20734687                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10387203                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8914712                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65869472                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                202922                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2041149                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 141248                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4766165                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43946104                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79818079                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79637315                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168311                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38139253                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5806843                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1691151                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         241440                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13536828                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10424364                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6928356                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1483959                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1059889                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58630025                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2138995                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57603342                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             50950                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7503583                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3485287                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1477804                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     112863592                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.510380                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.252962                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            89394835     79.20%     79.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10016384      8.87%     88.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4304507      3.81%     91.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             2950730      2.61%     94.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3082787      2.73%     97.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1592384      1.41%     98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1013037      0.90%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              395526      0.35%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              121892      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            89383207     79.20%     79.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10013548      8.87%     88.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4301377      3.81%     91.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             2962557      2.62%     94.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3086274      2.73%     97.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1586017      1.41%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1012124      0.90%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              396460      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              122028      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       112872082                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       112863592                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  212963     18.82%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 545078     48.16%     66.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                373836     33.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  213045     18.77%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 547519     48.24%     67.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                374446     32.99%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39097776     67.89%     67.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61804      0.11%     68.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38376      0.07%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39102059     67.88%     67.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61815      0.11%     68.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38377      0.07%     68.07% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.07% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.07% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10712581     18.60%     86.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6722276     11.67%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             948961      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10718615     18.61%     86.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6722522     11.67%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949032      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57592696                       # Type of FU issued
-system.cpu.iq.rate                           0.486832                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1131877                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019653                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          228528169                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67952558                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55916727                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              712410                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             334609                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       328997                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58334880                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  382407                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           639606                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57603342                       # Type of FU issued
+system.cpu.iq.rate                           0.486934                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1135010                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019704                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          228544022                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          67957775                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55921178                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              712213                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             334464                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       328973                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58348779                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  382287                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           639736                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1340629                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4088                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1339690                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4038                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        20047                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       553798                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores       554552                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18287                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        539247                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18285                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        544771                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 583638                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                44307486                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                616008                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64468948                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            145079                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10425085                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6927485                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1890835                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  42893                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                369751                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                 584207                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                44318330                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                613096                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64473181                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            145267                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10424364                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6928356                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1890724                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  42751                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                366947                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          20047                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         190429                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       410127                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               600556                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              57009373                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10371242                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            583322                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         190952                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       410451                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               601403                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              57018878                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10377294                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            584463                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3703730                       # number of nop insts executed
-system.cpu.iew.exec_refs                     17042240                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8981920                       # Number of branches executed
-system.cpu.iew.exec_stores                    6670998                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.481901                       # Inst execution rate
-system.cpu.iew.wb_sent                       56380366                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56245724                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28936691                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  40310167                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3704161                       # number of nop insts executed
+system.cpu.iew.exec_refs                     17048455                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8982580                       # Number of branches executed
+system.cpu.iew.exec_stores                    6671161                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.481994                       # Inst execution rate
+system.cpu.iew.wb_sent                       56384919                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56250151                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28947314                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  40326252                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.475446                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.717851                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.475495                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717828                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8239182                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661144                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            548042                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    111437316                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.503568                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.455315                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         8239076                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661191                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            548552                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    111427799                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.503633                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.455266                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     91810154     82.39%     82.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7802563      7.00%     89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4132031      3.71%     93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2155493      1.93%     95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1853584      1.66%     96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       616181      0.55%     97.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       467348      0.42%     97.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       515869      0.46%     98.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2084093      1.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     91796177     82.38%     82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7808087      7.01%     89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4129534      3.71%     93.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2155296      1.93%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1855711      1.67%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       615462      0.55%     97.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       470761      0.42%     97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       513166      0.46%     98.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2083605      1.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    111437316                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56116260                       # Number of instructions committed
-system.cpu.commit.committedOps               56116260                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    111427799                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56118765                       # Number of instructions committed
+system.cpu.commit.committedOps               56118765                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15458143                       # Number of memory references committed
-system.cpu.commit.loads                       9084456                       # Number of loads committed
-system.cpu.commit.membars                      226334                       # Number of memory barriers committed
-system.cpu.commit.branches                    8434463                       # Number of branches committed
+system.cpu.commit.refs                       15458478                       # Number of memory references committed
+system.cpu.commit.loads                       9084674                       # Number of loads committed
+system.cpu.commit.membars                      226351                       # Number of memory barriers committed
+system.cpu.commit.branches                    8434924                       # Number of branches committed
 system.cpu.commit.fp_insts                     324518                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  51967854                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               739911                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3195933      5.70%      5.70% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36178550     64.47%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60663      0.11%     70.27% # Class of committed instruction
+system.cpu.commit.int_insts                  51970227                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               739937                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3196003      5.70%      5.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36180557     64.47%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60666      0.11%     70.27% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.27% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38089      0.07%     70.34% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.34% # Class of committed instruction
@@ -776,66 +618,550 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9310790     16.59%     86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6379639     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        948960      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9311025     16.59%     86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6379757     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949032      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56116260                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2084093                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          56118765                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2083605                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    173459156                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130141826                       # The number of ROB writes
-system.cpu.timesIdled                          576115                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5428979                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3599776298                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52927600                       # Number of Instructions Simulated
-system.cpu.committedOps                      52927600                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.235149                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.235149                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.447398                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.447398                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74648651                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40584029                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166982                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167600                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2029015                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939371                       # number of misc regfile writes
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu.rob.rob_reads                    173452486                       # The number of ROB reads
+system.cpu.rob.rob_writes                   130147702                       # The number of ROB writes
+system.cpu.timesIdled                          575947                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5434424                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3599800282                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52930035                       # Number of Instructions Simulated
+system.cpu.committedOps                      52930035                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.234988                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.234988                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.447430                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.447430                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74659793                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40587610                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166949                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167607                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2029497                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939434                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1404580                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994645                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11874772                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1405092                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.451242                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          25219000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994645                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          413                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63937777                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63937777                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7284414                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7284414                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4188003                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4188003                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186359                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186359                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215726                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215726                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11472417                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11472417                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11472417                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11472417                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1780024                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1780024                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1955346                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1955346                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23271                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23271                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           28                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           28                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3735370                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3735370                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3735370                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3735370                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  39520730746                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  39520730746                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  78084026192                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  78084026192                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    364876749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    364876749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       441006                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       441006                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 117604756938                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 117604756938                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 117604756938                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 117604756938                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9064438                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9064438                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6143349                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6143349                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209630                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209630                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215754                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215754                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15207787                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15207787                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15207787                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15207787                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.196374                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.196374                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318287                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318287                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111010                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111010                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.245622                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.245622                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.245622                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.245622                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31484.098480                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31484.098480                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      3992388                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1705                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            180260                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              24                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.147942                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    71.041667                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       842675                       # number of writebacks
+system.cpu.dcache.writebacks::total            842675                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       683874                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       683874                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664228                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1664228                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5276                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5276                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2348102                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2348102                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2348102                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2348102                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1096150                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1096150                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291118                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       291118                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17995                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17995                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1387268                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1387268                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1387268                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1387268                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27519652282                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27519652282                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11779193020                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11779193020                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    204738251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    204738251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       384994                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       384994                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39298845302                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  39298845302                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39298845302                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  39298845302                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423580000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423580000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1999637498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1999637498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3423217498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3423217498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120929                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120929                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047388                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047388                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085842                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085842                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091221                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091221                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements           1035530                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.402349                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7932375                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1036038                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.656452                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26422155250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.402349                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994926                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994926                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          10056088                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10056088                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7932376                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7932376                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7932376                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7932376                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7932376                       # number of overall hits
+system.cpu.icache.overall_hits::total         7932376                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1087421                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1087421                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1087421                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1087421                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1087421                       # number of overall misses
+system.cpu.icache.overall_misses::total       1087421                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15131971529                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15131971529                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15131971529                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15131971529                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15131971529                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15131971529                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9019797                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9019797                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9019797                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9019797                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9019797                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9019797                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120559                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.120559                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.120559                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.120559                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.120559                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.120559                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13915.467449                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13915.467449                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5307                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    26.142857                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        51130                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        51130                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        51130                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        51130                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        51130                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        51130                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1036291                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1036291                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1036291                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1036291                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1036291                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1036291                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12436978135                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12436978135                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12436978135                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12436978135                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12436978135                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12436978135                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114891                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.114891                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.114891                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements           338304                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65336.722890                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2576408                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403470                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.385625                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5538371750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5341.050861                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6255.313222                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.820013                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081498                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095449                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996959                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3329                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55432                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994354                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26978409                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26978409                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1021005                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       829436                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1850441                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       842675                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       842675                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           32                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           32                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           22                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           22                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       186561                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       186561                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1021005                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1015997                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2037002                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1021005                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1015997                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2037002                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        15114                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       273817                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288931                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           47                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           47                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            6                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            6                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       115372                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       115372                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15114                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       389189                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        404303                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15114                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       389189                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404303                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1159992750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17995310250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  19155303000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       355494                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       355494                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        92496                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total        92496                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9679121611                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9679121611                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1159992750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  27674431861                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  28834424611                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1159992750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  27674431861                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  28834424611                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1036119                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1103253                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2139372                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       842675                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       842675                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           79                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           28                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           28                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       301933                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       301933                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1036119                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1405186                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2441305                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1036119                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1405186                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2441305                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014587                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248191                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.135054                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.594937                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.594937                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.214286                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.214286                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382111                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.382111                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014587                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.276966                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.165609                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014587                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.276966                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.165609                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76749.553394                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65720.208205                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 66297.153992                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7563.702128                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7563.702128                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        15416                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        15416                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83894.893137                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83894.893137                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76749.553394                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71107.949765                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71318.849009                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76749.553394                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71107.949765                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71318.849009                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        75929                       # number of writebacks
+system.cpu.l2cache.writebacks::total            75929                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15113                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273817                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288930                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           47                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           47                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            6                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            6                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115372                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       115372                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15113                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389189                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404302                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15113                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389189                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404302                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    969372000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14584664250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15554036250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       622542                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       622542                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        60006                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        60006                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8273073889                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8273073889                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    969372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22857738139                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23827110139                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    969372000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22857738139                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23827110139                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333490000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333490000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1884459000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1884459000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3217949000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3217949000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014586                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248191                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.135054                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.594937                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.594937                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382111                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382111                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014586                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276966                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.165609                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014586                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276966                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165609                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64141.599947                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53264.275958                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53833.233828                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13245.574468                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13245.574468                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        2146647                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2146537                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       842675                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           28                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       301933                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       301933                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           93                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2072410                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3686471                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5758881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66311616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143911276                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          210222892                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       42053                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3325984                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.012545                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.111300                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3284259     98.75%     98.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              41725      1.25%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3325984                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2497867498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1558461609                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2189866891                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51063                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           86                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               9597                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -890,540 +1216,213 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           374547621                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406221775                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42014789                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42010536                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.trans_dist::ReadReq        2147499                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2147393                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       842679                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41561                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           81                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           26                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           89                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2074254                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3686339                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5760593                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66370688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143907436                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          210278124                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       42060                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3326850                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.012545                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.111298                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3285116     98.75%     98.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41734      1.25%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3326850                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2498300996                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1559854344                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2189806641                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1036451                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.402237                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7937240                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1036959                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.654343                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26422155250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.402237                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994926                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994926                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10062742                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10062742                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7937241                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7937241                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7937241                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7937241                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7937241                       # number of overall hits
-system.cpu.icache.overall_hits::total         7937241                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1088289                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1088289                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1088289                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1088289                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1088289                       # number of overall misses
-system.cpu.icache.overall_misses::total       1088289                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15130440508                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15130440508                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15130440508                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15130440508                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15130440508                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15130440508                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9025530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9025530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9025530                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9025530                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9025530                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9025530                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120579                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.120579                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.120579                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.120579                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.120579                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.120579                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13902.961904                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13902.961904                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4627                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.793103                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        51077                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        51077                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        51077                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        51077                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        51077                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        51077                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1037212                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1037212                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1037212                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1037212                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1037212                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1037212                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12445124401                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12445124401                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12445124401                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12445124401                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12445124401                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12445124401                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114920                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114920                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114920                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114920                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114920                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114920                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338311                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65336.723406                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2577279                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403479                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.387641                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5538371750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5341.296148                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6255.276773                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.820010                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081502                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095448                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996959                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          497                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3500                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3328                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55422                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26985288                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26985288                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1021912                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       829370                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1851282                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       842679                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       842679                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           21                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           21                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       186572                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       186572                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1021912                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1015942                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2037854                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1021912                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1015942                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2037854                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        15130                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       273814                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288944                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           48                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           48                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            5                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115362                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115362                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15130                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389176                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404306                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15130                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389176                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404306                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1158124750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17992143250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  19150268000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       194993                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       194993                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        69497                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        69497                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9692879611                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9692879611                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1158124750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27685022861                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28843147611                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1158124750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27685022861                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28843147611                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1037042                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1103184                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2140226                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       842679                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       842679                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           81                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           81                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           26                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           26                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       301934                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       301934                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1037042                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1405118                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2442160                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1037042                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1405118                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2442160                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014590                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248203                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.135006                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.592593                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.592593                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.192308                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.192308                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382077                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.382077                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014590                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.276970                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.165553                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014590                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.276970                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.165553                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4062.354167                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4062.354167                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75938                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75938                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15129                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273814                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288943                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           48                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           48                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       115362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15129                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389176                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404305                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15129                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389176                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404305                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    967311000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14580972250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15548283250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       493045                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       493045                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        50005                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        50005                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8286916389                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8286916389                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    967311000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22867888639                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  23835199639                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    967311000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22867888639                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  23835199639                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333507000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333507000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1884436000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1884436000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3217943000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3217943000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014589                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248203                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.135006                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.592593                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.592593                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.192308                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.192308                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382077                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382077                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014589                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276970                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165552                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014589                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276970                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165552                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1404516                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994651                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11877087                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1405028                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.453274                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          25219000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994651                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63934725                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63934725                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7287009                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7287009                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4187789                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4187789                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186297                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186297                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215715                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215715                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11474798                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11474798                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11474798                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11474798                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1776849                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1776849                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1955456                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1955456                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23283                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23283                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           26                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           26                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3732305                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3732305                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3732305                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3732305                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  39503001495                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  39503001495                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  78159072008                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  78159072008                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    364867750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    364867750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       402005                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       402005                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 117662073503                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 117662073503                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 117662073503                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 117662073503                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9063858                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9063858                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6143245                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6143245                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209580                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209580                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215741                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215741                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15207103                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15207103                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15207103                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15207103                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.196037                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.196037                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318310                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318310                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111094                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111094                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000121                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000121                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.245432                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.245432                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.245432                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.245432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31525.310365                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31525.310365                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      3999248                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1376                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            180044                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              22                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.212615                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    62.545455                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842679                       # number of writebacks
-system.cpu.dcache.writebacks::total            842679                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       680758                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       680758                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664340                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1664340                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5292                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5292                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2345098                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2345098                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2345098                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2345098                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1096091                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1096091                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291116                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       291116                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17991                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17991                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           26                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           26                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1387207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1387207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1387207                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1387207                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27515724784                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27515724784                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11792803134                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11792803134                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    204517750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    204517750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       349995                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       349995                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39308527918                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  39308527918                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39308527918                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  39308527918                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423597000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423597000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1999614498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1999614498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3423211498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3423211498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120930                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120930                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047388                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047388                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085843                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085843                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000121                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000121                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091221                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091221                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.tags.replacements                41685                       # number of replacements
+system.iocache.tags.tagsinuse                1.260575                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1709355371000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.260575                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078786                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078786                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13648838856                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13648838856                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        206574                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23538                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.776192                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11488062928                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11488062928                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              296033                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295940                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
+system.membus.trans_dist::Writeback            117441                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              186                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             192                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115233                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115233                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           93                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884176                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          186                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917416                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1042220                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30702400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30746540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36063596                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              435                       # Total snoops (count)
+system.membus.snoop_fanout::samples            563522                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  563522    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              563522                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            31470000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy          1857946999                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy              115000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3754266813                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy           43145464                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     210986                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74656     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6441                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211003                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74662     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105550     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182216                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73289     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105561     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182233                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73295     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73289     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148588                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817327743500     97.76%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                61881000      0.00%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               521765000      0.03%     97.79% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41126450000      2.21%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1859037839500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981689                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73295     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148600                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1817339213500     97.76%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                61863500      0.00%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               521835500      0.03%     97.79% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             41125418500      2.21%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1859048331000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694353                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815450                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694338                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815440                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1462,7 +1461,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4178      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175101     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175118     91.22%     93.44% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6783      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
@@ -1471,20 +1470,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.98% # nu
 system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191946                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1910                      
-system.cpu.kern.mode_good::user                  1740                      
+system.cpu.kern.callpal::total                 191963                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5853                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1911                      
+system.cpu.kern.mode_good::user                  1741                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326499                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394302                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29097785000      1.57%      1.57% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2655967500      0.14%      1.71% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827284079000     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394468                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29096339500      1.57%      1.57% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2660038000      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1827291945500     98.29%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index def1f96ac..3aeb0bbf5 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,134 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.841612                       # Number of seconds simulated
-sim_ticks                                1841612450000                       # Number of ticks simulated
-final_tick                               1841612450000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.842592                       # Number of seconds simulated
+sim_ticks                                1842592129000                       # Number of ticks simulated
+final_tick                               1842592129000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 223623                       # Simulator instruction rate (inst/s)
-host_op_rate                                   223623                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6307109470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313464                       # Number of bytes of host memory used
-host_seconds                                   291.99                       # Real time elapsed on the host
-sim_insts                                    65295558                       # Number of instructions simulated
-sim_ops                                      65295558                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 226605                       # Simulator instruction rate (inst/s)
+host_op_rate                                   226605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6393875150                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320256                       # Number of bytes of host memory used
+host_seconds                                   288.18                       # Real time elapsed on the host
+sim_insts                                    65303087                       # Number of instructions simulated
+sim_ops                                      65303087                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           476096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20002240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           480640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20073664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           146816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2246336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           292800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2554880                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2248832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           298304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2641344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25814784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       476096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       298304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          921408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4825792                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7485120                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7439                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            312535                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25796096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       480640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       146816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       292800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          920256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7481536                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7481536                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7510                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            313651                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2294                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             35099                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4575                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39920                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             35138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             41271                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403356                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           75403                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116955                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              258521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10861265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116899                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116899                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              260850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10894253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1219117                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              158907                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1386568                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               79826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1221121                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              161980                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1434256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14017490                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         258521                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          79826                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         161980                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             500327                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2620417                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1444022                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4064438                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2620417                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             258521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10861265                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1444543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              79826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1221121                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             161980                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1434256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18081928                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         83382                       # Number of read requests accepted
-system.physmem.writeReqs                        46694                       # Number of write requests accepted
-system.physmem.readBursts                       83382                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      46694                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5333696                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      2752                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2986816                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5336448                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2988416                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       43                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             55                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5371                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5100                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5085                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5221                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5159                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5196                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5274                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5273                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5416                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5013                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5453                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5267                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4696                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5103                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5623                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5089                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2944                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2803                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2831                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3111                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3010                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2812                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                3230                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2824                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3325                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2680                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3123                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2945                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2356                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2727                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3249                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2699                       # Per bank write bursts
+system.physmem.bw_read::total                13999895                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         260850                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         158907                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             499436                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4060332                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4060332                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4060332                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             260850                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10894253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1219117                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             158907                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1386568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18060227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         81903                       # Number of read requests accepted
+system.physmem.writeReqs                        62699                       # Number of write requests accepted
+system.physmem.readBursts                       81903                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      62699                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5240384                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   3952512                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5241792                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4012736                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                     916                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs             49                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5341                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4966                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4940                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5071                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5028                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5062                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5140                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5148                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5331                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5012                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5278                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5132                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4684                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5065                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5602                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5081                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                3943                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                3578                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                3780                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4114                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3703                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                3530                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4127                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                3704                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4410                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                3736                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4083                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3942                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3446                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               3846                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4153                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3663                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1840600173500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1841579852500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   83382                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   81903                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  46694                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     66361                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      7479                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1778                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        21                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  62699                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     65847                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      7163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -162,640 +159,187 @@ system.physmem.wrQLenPdf::2                        46                       # Wh
 system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        44                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     3527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        43                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30                     2412                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::46                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        6                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      384.870346                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     218.868855                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     380.663334                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7130     32.98%     32.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4830     22.34%     55.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1852      8.57%     63.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1050      4.86%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          916      4.24%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          498      2.30%     75.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          396      1.83%     77.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          403      1.86%     78.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4544     21.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21619                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2039                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        40.867092                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1027.907354                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2037     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::47                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       45                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52                       33                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54                       21                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        22200                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      414.094414                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     234.871610                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     395.166984                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           6979     31.44%     31.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4758     21.43%     52.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1802      8.12%     60.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1018      4.59%     65.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          909      4.09%     69.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          488      2.20%     71.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          377      1.70%     73.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          379      1.71%     75.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5490     24.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          22200                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2135                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        38.346604                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1004.576162                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2133     99.91%     99.91% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2039                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2039                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.888180                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.579378                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.470267                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                42      2.06%      2.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15                4      0.20%      2.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            1722     84.45%     86.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             114      5.59%     92.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              19      0.93%     93.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               3      0.15%     93.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               5      0.25%     93.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               2      0.10%     93.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               2      0.10%     93.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               3      0.15%     93.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              15      0.74%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.25%     94.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103             79      3.87%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             5      0.25%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.05%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             5      0.25%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             5      0.25%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             3      0.15%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             1      0.05%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.10%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2039                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      882163500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2444769750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    416695000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10585.24                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2135                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2135                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        28.926464                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.717874                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       36.556650                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                42      1.97%      1.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15                3      0.14%      2.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            1647     77.14%     79.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              96      4.50%     83.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             109      5.11%     88.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              21      0.98%     89.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              47      2.20%     92.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              14      0.66%     92.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               5      0.23%     92.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               4      0.19%     93.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               8      0.37%     93.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              8      0.37%     93.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             2      0.09%     93.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             2      0.09%     94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.05%     94.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            13      0.61%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            15      0.70%     95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            12      0.56%     95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             7      0.33%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            36      1.69%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            13      0.61%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             7      0.33%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             7      0.33%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             5      0.23%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             3      0.14%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.14%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.05%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::296-303             1      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2135                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      816878250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2352147000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    409405000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9976.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29335.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28726.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.18                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.38                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      71513                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36876                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.97                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14150190.45                       # Average gap between requests
-system.physmem.pageHitRate                      83.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1766563042250                       # Time in different power states
-system.physmem.memoryStateTime::REF       61495460000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         8.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      70255                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51184                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.80                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  82.84                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12735507.48                       # Average gap between requests
+system.physmem.pageHitRate                      84.53                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1767479155500                       # Time in different power states
+system.physmem.memoryStateTime::REF       61527960000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       13553394000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       13578075750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                  81912600                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                  81527040                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  44694375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  44484000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                325096200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                324948000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               152701200                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               149713920                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          120285119760                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          120285119760                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           46099249605                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           45830401695                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1064529191250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1064765022750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1231517964990                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1231481217165                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.717430                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.697476                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              294949                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294942                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9810                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9810                       # Transaction distribution
-system.membus.trans_dist::Writeback             75403                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              148                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             150                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115716                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115716                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            7                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       882385                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       916307                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83395                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83395                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 999702                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30639616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30685184                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2666880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2666880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33352064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                               55                       # Total snoops (count)
-system.membus.snoop_fanout::samples            520629                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  520629    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              520629                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11839500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           516853000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy                9000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          782820695                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           17912499                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.physmem.actEnergy::0                  83696760                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                  84135240                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                  45667875                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                  45907125                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                317428800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                321243000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               197503920                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               202687920                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          120348689760                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          120348689760                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           46124478945                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           45810126225                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1065091037250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1065366785250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1232208503310                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1232179574520                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.738964                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.723264                       # Core power per rank (mW)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   337573                       # number of replacements
-system.l2c.tags.tagsinuse                65418.651212                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2486411                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402735                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.173814                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54701.898581                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2338.827583                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2722.708612                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      571.952854                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      605.884854                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2274.772027                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2202.606700                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.834685                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.035688                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.041545                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008727                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009245                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034710                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.033609                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998209                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1013                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5951                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2693                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55337                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26257052                       # Number of tag accesses
-system.l2c.tags.data_accesses                26257052                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             505398                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             481784                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             121841                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              80801                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             322748                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             255127                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1767699                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835833                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835833                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  14                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 6                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            90729                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            25227                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            70911                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               186867                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              505398                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              572513                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              121841                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              106028                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              322748                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              326038                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1954566                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             505398                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             572513                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             121841                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             106028                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             322748                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             326038                       # number of overall hits
-system.l2c.overall_hits::total                1954566                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst             7439                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           238433                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2297                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data            16797                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             4661                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            18005                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               287632                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                24                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu2.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          74189                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          18351                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          23300                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115840                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst              7439                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            312622                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2297                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             35148                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              4661                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             41305                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                403472                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst             7439                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           312622                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2297                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            35148                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             4661                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            41305                       # number of overall misses
-system.l2c.overall_misses::total               403472                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    172213000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data   1123783250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    353640000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1207129000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2856765250                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       175993                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       175993                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu2.data        46498                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        46498                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1259346740                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1952437723                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3211784463                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    172213000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2383129990                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    353640000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3159566723                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6068549713                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    172213000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2383129990                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    353640000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3159566723                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6068549713                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         512837                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         720217                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         124138                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          97598                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         327409                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         273132                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2055331                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       835833                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835833                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           26                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              38                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data            8                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             8                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       164918                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        43578                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        94211                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302707                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          512837                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          885135                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          124138                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          141176                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          327409                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          367343                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2358038                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         512837                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         885135                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         124138                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         141176                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         327409                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         367343                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2358038                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014506                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.331057                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.018504                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.172104                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.014236                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.065921                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.139944                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.615385                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.631579                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.449854                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.421107                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.247317                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382680                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014506                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.353191                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.018504                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.248966                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.014236                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.112443                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.171105                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014506                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.353191                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.018504                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.248966                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.014236                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.112443                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.171105                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74973.008272                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 66903.807227                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75872.130444                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 67044.098861                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total  9932.014692                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10999.562500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  7333.041667                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        23249                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        23249                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68625.510326                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83795.610429                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 27726.039908                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74973.008272                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 67802.719643                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 75872.130444                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 76493.565501                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 15040.819965                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74973.008272                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 67802.719643                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 75872.130444                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 76493.565501                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 15040.819965                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75403                       # number of writebacks
-system.l2c.writebacks::total                    75403                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2297                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data        16797                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         4661                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        18005                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           41760                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        18351                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        23300                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         41651                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2297                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        35148                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4661                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        41305                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            83411                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2297                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        35148                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4661                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        41305                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           83411                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    142970000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    913492250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    294969000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    982528500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2333959750                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       173016                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       173016                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1028775260                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1667747777                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   2696523037                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    142970000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1942267510                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    294969000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2650276277                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5030482787                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    142970000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1942267510                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    294969000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2650276277                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5030482787                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    233807000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    320899000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    554706000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    302174000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    396022500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total    698196500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    535981000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716921500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1252902500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018504                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.172104                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014236                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.065921                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020318                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.615385                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.421053                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.421107                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.247317                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.137595                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018504                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.248966                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014236                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.112443                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035373                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018504                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.248966                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014236                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.112443                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035373                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62242.054854                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54384.250164                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63284.488307                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54569.758400                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 55889.840757                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10813.500000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10813.500000                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56060.991772                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71577.157811                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 64740.895465                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62242.054854                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55259.687891                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63284.488307                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64163.570439                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60309.584911                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62242.054854                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55259.687891                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63284.488307                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64163.570439                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60309.584911                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254811                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693889963000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254811                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078426                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078426                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9417462                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9417462                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide      9417462                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total      9417462                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide      9417462                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total      9417462                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 54436.196532                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 54436.196532                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 54436.196532                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5776462                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      5776462                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   1039517841                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1039517841                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide      5776462                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      5776462                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide      5776462                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      5776462                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4820532                       # DTB read hits
-system.cpu0.dtb.read_misses                      5970                       # DTB read misses
-system.cpu0.dtb.read_acv                          109                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  427970                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3430087                       # DTB write hits
-system.cpu0.dtb.write_misses                      674                       # DTB write misses
-system.cpu0.dtb.write_acv                          81                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 164325                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8250619                       # DTB hits
-system.cpu0.dtb.data_misses                      6644                       # DTB misses
-system.cpu0.dtb.data_acv                          190                       # DTB access violations
-system.cpu0.dtb.data_accesses                  592295                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2728150                       # ITB hits
-system.cpu0.itb.fetch_misses                     3015                       # ITB misses
-system.cpu0.itb.fetch_acv                          97                       # ITB acv
-system.cpu0.itb.fetch_accesses                2731165                       # ITB accesses
+system.cpu0.dtb.read_hits                     4840766                       # DTB read hits
+system.cpu0.dtb.read_misses                      6162                       # DTB read misses
+system.cpu0.dtb.read_acv                          126                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  429577                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3449248                       # DTB write hits
+system.cpu0.dtb.write_misses                      688                       # DTB write misses
+system.cpu0.dtb.write_acv                          85                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 165228                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8290014                       # DTB hits
+system.cpu0.dtb.data_misses                      6850                       # DTB misses
+system.cpu0.dtb.data_acv                          211                       # DTB access violations
+system.cpu0.dtb.data_accesses                  594805                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2745005                       # ITB hits
+system.cpu0.itb.fetch_misses                     3071                       # ITB misses
+system.cpu0.itb.fetch_acv                         104                       # ITB acv
+system.cpu0.itb.fetch_accesses                2748076                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -808,87 +352,87 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       929887646                       # number of cpu cycles simulated
+system.cpu0.numCycles                       930170502                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   30964546                       # Number of instructions committed
-system.cpu0.committedOps                     30964546                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             28877269                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                164895                       # Number of float alu accesses
-system.cpu0.num_func_calls                     798898                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3870413                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    28877269                       # number of integer instructions
-system.cpu0.num_fp_insts                       164895                       # number of float instructions
-system.cpu0.num_int_register_reads           39993375                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21214284                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               85263                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86719                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8280000                       # number of memory refs
-system.cpu0.num_load_insts                    4841351                       # Number of load instructions
-system.cpu0.num_store_insts                   3438649                       # Number of store instructions
-system.cpu0.num_idle_cycles              908004121.642144                       # Number of idle cycles
-system.cpu0.num_busy_cycles              21883524.357856                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023534                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976466                       # Percentage of idle cycles
-system.cpu0.Branches                          4926659                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1578204      5.10%      5.10% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 20416117     65.92%     71.01% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31858      0.10%     71.12% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.12% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12902      0.04%     71.16% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1598      0.01%     71.16% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.16% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4972343     16.05%     87.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3441751     11.11%     98.33% # Class of executed instruction
-system.cpu0.op_class::IprAccess                516607      1.67%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   31084978                       # Number of instructions committed
+system.cpu0.committedOps                     31084978                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             28990115                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                165280                       # Number of float alu accesses
+system.cpu0.num_func_calls                     801354                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3884267                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    28990115                       # number of integer instructions
+system.cpu0.num_fp_insts                       165280                       # number of float instructions
+system.cpu0.num_int_register_reads           40144651                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          21293303                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               85481                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              86924                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8319976                       # number of memory refs
+system.cpu0.num_load_insts                    4862063                       # Number of load instructions
+system.cpu0.num_store_insts                   3457913                       # Number of store instructions
+system.cpu0.num_idle_cycles              907838728.357051                       # Number of idle cycles
+system.cpu0.num_busy_cycles              22331773.642949                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024008                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975992                       # Percentage of idle cycles
+system.cpu0.Branches                          4943919                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1583961      5.09%      5.09% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 20486094     65.89%     70.98% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31888      0.10%     71.09% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.09% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12950      0.04%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1606      0.01%     71.13% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.13% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4993462     16.06%     87.19% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3461022     11.13%     98.32% # Class of executed instruction
+system.cpu0.op_class::IprAccess                521056      1.68%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  30971380                       # Class of executed instruction
+system.cpu0.op_class::total                  31092039                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6422                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211354                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.hwrei                    211371                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74797     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105681     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182556                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105691     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182570                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73430     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1818780188000     98.76%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               39182000      0.00%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              357649000      0.02%     98.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22434661500      1.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1841611680500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73430     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148942                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1819773509500     98.76%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38545500      0.00%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              357643000      0.02%     98.78% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22421661500      1.22%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1842591359500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981724                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694798                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815832                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694761                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815808                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -924,537 +468,278 @@ system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175299     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175311     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192210                       # number of callpals executed
+system.cpu0.kern.callpal::total                192226                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2093                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1907                      
+system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1908                      
 system.cpu0.kern.mode_good::user                 1738                      
-system.cpu0.kern.mode_good::idle                  169                      
-system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_good::idle                  170                      
+system.cpu0.kern.mode_switch_good::kernel     0.322188                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.080745                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.391059                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29705567000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2577814500      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1809328294500     98.25%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2062606                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2062584                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              9810                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             9810                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           835833                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        17283                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              38                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             8                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             46                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302707                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302707                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            7                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1928849                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3657196                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5586045                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61721856                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142735808                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              204457664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           41925                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3235706                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012896                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.112826                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3193978     98.71%     98.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  41728      1.29%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3235706                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2218971499                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2034366165                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2306919756                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51362                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              27090                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        24272                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5192                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          756                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18256                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33908                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117358                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20768                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2208000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               105000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5523000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             2079000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           155677802                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9370000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17534501                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           963743                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.196442                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           40274426                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           964254                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            41.767445                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10190503250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.296847                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    67.404531                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   180.495065                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.514252                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131649                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.352529                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998431                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42219519                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42219519                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30458523                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7341413                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2474490                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       40274426                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     30458523                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7341413                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2474490                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        40274426                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     30458523                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7341413                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2474490                       # number of overall hits
-system.cpu0.icache.overall_hits::total       40274426                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       512857                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       124138                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       343653                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       980648                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       512857                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       124138                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       343653                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        980648                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       512857                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       124138                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       343653                       # number of overall misses
-system.cpu0.icache.overall_misses::total       980648                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1770888500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4833799298                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6604687798                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1770888500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4833799298                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6604687798                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1770888500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4833799298                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6604687798                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30971380                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7465551                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2818143                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41255074                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30971380                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7465551                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2818143                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41255074                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30971380                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7465551                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2818143                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41255074                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016559                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016628                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.121943                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023770                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016559                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016628                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.121943                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023770                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016559                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016628                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.121943                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023770                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.482769                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14065.930744                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6735.023982                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.482769                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14065.930744                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6735.023982                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.482769                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14065.930744                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6735.023982                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3646                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              161                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.645963                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16203                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16203                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16203                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16203                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16203                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16203                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       124138                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       327450                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       451588                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       124138                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       327450                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       451588                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       124138                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       327450                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       451588                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1521699500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3997566325                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5519265825                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1521699500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3997566325                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5519265825                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1521699500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3997566325                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5519265825                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016628                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116194                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010946                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016628                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116194                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010946                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016628                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116194                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010946                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.128051                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.173233                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.905420                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.128051                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.173233                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.905420                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.128051                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12208.173233                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.905420                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1393134                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13262946                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393646                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.516725                       # Average number of references to valid blocks.
+system.cpu0.kern.mode_switch_good::idle      0.081107                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29639680500      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2561811500      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1810389863000     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
+system.cpu0.dcache.tags.replacements          1393201                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997818                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13277254                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393713                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.526534                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   261.690760                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    74.796063                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   175.510993                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.511115                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.146086                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.342795                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   261.608452                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    74.750107                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   175.639259                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.510954                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.145996                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.343045                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63351559                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63351559                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      3996259                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1054031                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2516397                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7566687                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3140432                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       808252                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1363715                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5312399                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114574                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18764                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51112                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184450                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123404                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20737                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55180                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199321                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7136691                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1862283                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3880112                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12879086                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7136691                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1862283                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3880112                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12879086                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       710837                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        95497                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       564447                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1370781                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       164929                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        43579                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       628162                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       836670                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9380                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2101                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7681                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19162                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         63354718                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63354718                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4014926                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1052133                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2504051                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7571110                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3157714                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       807247                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1357321                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5322282                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114982                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18680                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        50783                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184445                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123850                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20650                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        54829                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199329                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7172640                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1859380                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3861372                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12893392                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7172640                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1859380                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3861372                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12893392                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       712217                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        95395                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       559235                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1366847                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       166399                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        43585                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       617129                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       827113                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9420                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2097                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7598                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19115                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu2.data            8                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       875766                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       139076                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1192609                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2207451                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       875766                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       139076                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1192609                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2207451                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2207514000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9811838599                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  12019352599                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1651311760                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  20363561979                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  22014873739                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27705250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    128352996                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    156058246                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       130502                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       130502                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3858825760                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  30175400578                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  34034226338                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3858825760                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  30175400578                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  34034226338                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4707096                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1149528                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3080844                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8937468                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3305361                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       851831                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      1991877                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6149069                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123954                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20865                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58793                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203612                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123404                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20737                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55188                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199329                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8012457                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2001359                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5072721                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15086537                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8012457                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2001359                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5072721                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15086537                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151014                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083075                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.183212                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.153375                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049897                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051159                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315362                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.136065                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075673                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100695                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130645                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094110                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000145                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000040                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109301                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069491                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.235102                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146319                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109301                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069491                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.235102                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146319                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23116.056002                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17383.099917                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8768.251529                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37892.373850                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32417.691581                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 26312.493264                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13186.696811                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16710.453847                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8144.152281                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16312.750000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16312.750000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27746.165837                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.006423                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15417.885307                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27746.165837                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25302.006423                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15417.885307                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       891586                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          724                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            62691                       # number of cycles access was blocked
+system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       878616                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       138980                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1176364                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2193960                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       878616                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       138980                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1176364                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2193960                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2203388500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9682985565                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11886374065                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1649926260                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19421964168                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  21071890428                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27653250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    126867246                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    154520496                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       104000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       104000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3853314760                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  29104949733                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  32958264493                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3853314760                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  29104949733                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  32958264493                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4727143                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1147528                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3063286                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8937957                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3324113                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       850832                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1974450                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6149395                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124402                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20777                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58381                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203560                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123852                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20650                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        54837                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199339                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8051256                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      1998360                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5037736                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15087352                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8051256                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      1998360                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5037736                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15087352                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150665                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083131                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182560                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152926                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050058                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051226                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.312557                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.134503                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075722                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100929                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130145                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093904                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000016                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000146                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000050                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109128                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069547                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.233510                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.145417                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109128                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069547                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.233510                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.145417                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23097.526076                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17314.698767                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8696.199403                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37855.369049                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31471.481924                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25476.434814                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13187.052933                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16697.452751                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8083.729846                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        10400                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27725.678227                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24741.448848                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15022.272281                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27725.678227                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24741.448848                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15022.272281                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       825872                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          866                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            61038                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.221914                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    80.444444                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.530456                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    96.222222                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835833                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835833                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       297087                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       297087                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       534212                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       534212                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1624                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1624                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       831299                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       831299                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       831299                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       831299                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95497                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       267360                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       362857                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43579                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        93950                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       137529                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2101                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6057                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8158                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       835902                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835902                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       293112                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       293112                       # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1568                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1568                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       817754                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       817754                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       817754                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       817754                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95395                       # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43585                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        92487                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       136072                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6030                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8127                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            8                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       139076                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       361310                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       500386                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       139076                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       361310                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       500386                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2008989000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4477810640                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6486799640                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1555821240                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2924918842                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4480740082                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23501750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     73479753                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96981503                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       114498                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       114498                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3564810240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7402729482                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10967539722                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3564810240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7402729482                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10967539722                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    249745500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342957000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    592702500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    320247000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    420262500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    740509500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    569992500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    763219500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1333212000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083075                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086781                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040600                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051159                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047167                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022366                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100695                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.103022                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040066                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000145                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       138980                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       358610                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       497590                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       138980                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       358610                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       497590                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2005063500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4453995148                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6459058648                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1554433740                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2785719201                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4340152941                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23457750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72881252                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96339002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        88000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        88000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3559497240                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7239714349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10799211589                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3559497240                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7239714349                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10799211589                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    248461000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342715000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    591176000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    319650500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    420043000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    739693500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    568111500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    762758000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1330869500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083131                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086875                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040447                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051226                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.046842                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022128                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100929                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.103287                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.039924                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000146                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069491                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071226                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.033168                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069491                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071226                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.033168                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069547                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071185                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032981                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069547                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071185                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032981                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21703.031791                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1465,26 +750,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements           964194                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.195402                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           40365438                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           964705                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            41.842261                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10190503250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.118461                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    67.369800                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   180.707141                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.513903                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131582                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.352944                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998429                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         42311419                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42311419                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     30577752                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7329263                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2458423                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       40365438                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     30577752                       # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu0.inst     30577752                       # number of overall hits
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+system.cpu0.icache.overall_hits::total       40365438                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       514287                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       123865                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       342932                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       981084                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       514287                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       123865                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::total        981084                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       514287                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       123865                       # number of overall misses
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+system.cpu0.icache.overall_misses::total       981084                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1766313750                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_latency::total   6579620845                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1766313750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4813307095                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6579620845                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1766313750                       # number of overall miss cycles
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+system.cpu0.icache.overall_miss_latency::total   6579620845                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     31092039                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7453128                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2801355                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41346522                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.overall_accesses::cpu0.inst     31092039                       # number of overall (read+write) accesses
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+system.cpu0.icache.overall_accesses::total     41346522                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016541                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016619                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122416                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023728                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016541                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016619                       # miss rate for demand accesses
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+system.cpu0.icache.demand_miss_rate::total     0.023728                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016541                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016619                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122416                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023728                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14259.990716                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14035.747889                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6706.480633                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14259.990716                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14035.747889                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6706.480633                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14259.990716                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14035.747889                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6706.480633                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3823                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.892216                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16187                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16187                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16187                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16187                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16187                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16187                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       123865                       # number of ReadReq MSHR misses
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+system.cpu0.icache.ReadReq_mshr_misses::total       450610                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       123865                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       326745                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       450610                       # number of demand (read+write) MSHR misses
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+system.cpu0.icache.overall_mshr_misses::total       450610                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1517675250                       # number of ReadReq MSHR miss cycles
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+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5500634276                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1517675250                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.icache.demand_mshr_miss_latency::total   5500634276                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1517675250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3982959026                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5500634276                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010898                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010898                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010898                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12207.084343                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12207.084343                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12207.084343                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1168269                       # DTB read hits
-system.cpu1.dtb.read_misses                      1330                       # DTB read misses
-system.cpu1.dtb.read_acv                           35                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  141659                       # DTB read accesses
-system.cpu1.dtb.write_hits                     872893                       # DTB write hits
-system.cpu1.dtb.write_misses                      171                       # DTB write misses
+system.cpu1.dtb.read_hits                     1166206                       # DTB read hits
+system.cpu1.dtb.read_misses                      1314                       # DTB read misses
+system.cpu1.dtb.read_acv                           34                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  141633                       # DTB read accesses
+system.cpu1.dtb.write_hits                     871808                       # DTB write hits
+system.cpu1.dtb.write_misses                      168                       # DTB write misses
 system.cpu1.dtb.write_acv                          22                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  57101                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2041162                       # DTB hits
-system.cpu1.dtb.data_misses                      1501                       # DTB misses
-system.cpu1.dtb.data_acv                           57                       # DTB access violations
-system.cpu1.dtb.data_accesses                  198760                       # DTB accesses
-system.cpu1.itb.fetch_hits                     849127                       # ITB hits
-system.cpu1.itb.fetch_misses                      665                       # ITB misses
-system.cpu1.itb.fetch_acv                          34                       # ITB acv
-system.cpu1.itb.fetch_accesses                 849792                       # ITB accesses
+system.cpu1.dtb.write_accesses                  57088                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2038014                       # DTB hits
+system.cpu1.dtb.data_misses                      1482                       # DTB misses
+system.cpu1.dtb.data_acv                           56                       # DTB access violations
+system.cpu1.dtb.data_accesses                  198721                       # DTB accesses
+system.cpu1.itb.fetch_hits                     847614                       # ITB hits
+system.cpu1.itb.fetch_misses                      662                       # ITB misses
+system.cpu1.itb.fetch_acv                          32                       # ITB acv
+system.cpu1.itb.fetch_accesses                 848276                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1497,34 +919,34 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953403050                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953409628                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7463992                       # Number of instructions committed
-system.cpu1.committedOps                      7463992                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              6937939                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 43895                       # Number of float alu accesses
-system.cpu1.num_func_calls                     203449                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       905325                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     6937939                       # number of integer instructions
-system.cpu1.num_fp_insts                        43895                       # number of float instructions
-system.cpu1.num_int_register_reads            9652072                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5060714                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               23736                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24066                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2048141                       # number of memory refs
-system.cpu1.num_load_insts                    1172984                       # Number of load instructions
-system.cpu1.num_store_insts                    875157                       # Number of store instructions
-system.cpu1.num_idle_cycles              923975246.943285                       # Number of idle cycles
-system.cpu1.num_busy_cycles              29427803.056715                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030866                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969134                       # Percentage of idle cycles
-system.cpu1.Branches                          1173357                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               399705      5.35%      5.35% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4844088     64.89%     70.24% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8214      0.11%     70.35% # Class of executed instruction
+system.cpu1.committedInsts                    7451589                       # Number of instructions committed
+system.cpu1.committedOps                      7451589                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              6926409                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 43920                       # Number of float alu accesses
+system.cpu1.num_func_calls                     202937                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       904115                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     6926409                       # number of integer instructions
+system.cpu1.num_fp_insts                        43920                       # number of float instructions
+system.cpu1.num_int_register_reads            9636713                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5051586                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               23745                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24097                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2044932                       # number of memory refs
+system.cpu1.num_load_insts                    1170872                       # Number of load instructions
+system.cpu1.num_store_insts                    874060                       # Number of store instructions
+system.cpu1.num_idle_cycles              925046236.205368                       # Number of idle cycles
+system.cpu1.num_busy_cycles              28363391.794632                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029749                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970251                       # Percentage of idle cycles
+system.cpu1.Branches                          1171500                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               399169      5.36%      5.36% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4836084     64.89%     70.24% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8208      0.11%     70.35% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5110      0.07%     70.42% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5096      0.07%     70.42% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     70.42% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                      0      0.00%     70.42% # Class of executed instruction
 system.cpu1.op_class::FloatMult                     0      0.00%     70.42% # Class of executed instruction
@@ -1550,11 +972,11 @@ system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.43% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.43% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.43% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1201071     16.09%     86.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 876369     11.74%     98.26% # Class of executed instruction
-system.cpu1.op_class::IprAccess                130183      1.74%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1198833     16.08%     86.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 875271     11.74%     98.26% # Class of executed instruction
+system.cpu1.op_class::IprAccess                129656      1.74%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7465550                       # Class of executed instruction
+system.cpu1.op_class::total                   7453127                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1572,35 +994,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups                9020137                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          8282573                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           125563                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             6965204                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                4892106                       # Number of BTB hits
+system.cpu2.branchPred.lookups                8975833                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          8240091                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           125146                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             6986744                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                4884457                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            70.236364                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 299658                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7807                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            69.910347                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 298693                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7800                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3485260                       # DTB read hits
-system.cpu2.dtb.read_misses                     12402                       # DTB read misses
-system.cpu2.dtb.read_acv                          152                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  227268                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2138350                       # DTB write hits
-system.cpu2.dtb.write_misses                     2805                       # DTB write misses
-system.cpu2.dtb.write_acv                         140                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  85115                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5623610                       # DTB hits
-system.cpu2.dtb.data_misses                     15207                       # DTB misses
-system.cpu2.dtb.data_acv                          292                       # DTB access violations
-system.cpu2.dtb.data_accesses                  312383                       # DTB accesses
-system.cpu2.itb.fetch_hits                     538601                       # ITB hits
-system.cpu2.itb.fetch_misses                     5813                       # ITB misses
-system.cpu2.itb.fetch_acv                         166                       # ITB acv
-system.cpu2.itb.fetch_accesses                 544414                       # ITB accesses
+system.cpu2.dtb.read_hits                     3460113                       # DTB read hits
+system.cpu2.dtb.read_misses                     12059                       # DTB read misses
+system.cpu2.dtb.read_acv                          120                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  225843                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2120785                       # DTB write hits
+system.cpu2.dtb.write_misses                     2578                       # DTB write misses
+system.cpu2.dtb.write_acv                         111                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  84303                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5580898                       # DTB hits
+system.cpu2.dtb.data_misses                     14637                       # DTB misses
+system.cpu2.dtb.data_acv                          231                       # DTB access violations
+system.cpu2.dtb.data_accesses                  310146                       # DTB accesses
+system.cpu2.itb.fetch_hits                     534656                       # ITB hits
+system.cpu2.itb.fetch_misses                     5715                       # ITB misses
+system.cpu2.itb.fetch_acv                         156                       # ITB acv
+system.cpu2.itb.fetch_accesses                 540371                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1613,305 +1035,892 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        29513686                       # number of cpu cycles simulated
+system.cpu2.numCycles                        29309170                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9389582                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      35469274                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    9020137                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           5191764                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     18021119                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 410530                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                       647                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                9356                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1948                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       228650                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        98931                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          387                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2818143                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                92772                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          27955647                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.268770                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.388372                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9355872                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      35312418                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    8975833                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           5183150                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     17863271                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 408038                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                       247                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                9336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1926                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       226509                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        98836                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          360                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2801357                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                93254                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          27760138                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.272055                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.388957                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                20239272     72.40%     72.40% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  311789      1.12%     73.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  473018      1.69%     75.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 3278988     11.73%     86.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  836372      2.99%     89.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  194449      0.70%     90.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  239819      0.86%     91.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  437682      1.57%     93.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1944258      6.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20067804     72.29%     72.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  312324      1.13%     73.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  471431      1.70%     75.11% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 3277065     11.80%     86.92% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  832356      3.00%     89.92% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  194310      0.70%     90.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  239050      0.86%     91.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  435621      1.57%     93.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1930177      6.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            27955647                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.305626                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.201791                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7697914                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             13194592                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  6089531                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               535341                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                192357                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              175638                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13257                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              32098439                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                42458                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                192357                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7981444                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4806689                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6360452                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  6310892                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2057913                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              31276153                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                68586                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                406035                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 57262                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents                980638                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           20937225                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             38641604                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        38581458                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56230                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             19023888                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1913337                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            532654                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         63537                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3939185                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3509523                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2229292                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           463055                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          331167                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  28745476                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             680921                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 28394222                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            16375                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2445259                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1154216                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        487025                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     27955647                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.015688                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.594887                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            27760138                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.306247                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.204825                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7663207                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13056286                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6071971                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               531660                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                191161                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              175121                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13218                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              31964587                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                42189                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                191161                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7944282                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4747926                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6306317                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  6292094                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2032514                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              31148031                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                68690                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                405455                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 57635                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents                961672                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           20857546                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             38489272                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        38429323                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56078                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             18957389                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1900157                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            527032                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         63032                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3906781                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3488819                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2211142                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           463556                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          329659                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  28630875                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             676639                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 28279580                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            16369                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2426454                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1141058                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        483735                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     27760138                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.018712                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.595651                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17573743     62.86%     62.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2782129      9.95%     72.81% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1379697      4.94%     77.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4038946     14.45%     92.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1015784      3.63%     95.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             573145      2.05%     97.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             387606      1.39%     99.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             155412      0.56%     99.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              49185      0.18%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17419876     62.75%     62.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2765921      9.96%     72.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1372782      4.95%     77.66% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4034544     14.53%     92.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1009748      3.64%     95.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             570537      2.06%     97.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             383332      1.38%     99.27% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             154390      0.56%     99.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              49008      0.18%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       27955647                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       27760138                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  83781     21.60%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.60% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                179225     46.21%     67.82% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               124810     32.18%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  83197     21.73%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                176333     46.06%     67.80% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               123266     32.20%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             22268545     78.43%     78.43% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21109      0.07%     78.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     78.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20518      0.07%     78.58% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     78.58% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     78.58% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     78.58% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3613635     12.73%     91.31% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2162330      7.62%     98.93% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            304401      1.07%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             22202311     78.51%     78.52% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21087      0.07%     78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     78.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20489      0.07%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     78.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3587142     12.68%     91.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2144327      7.58%     98.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            300564      1.06%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              28394222                       # Type of FU issued
-system.cpu2.iq.rate                          0.962070                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     387816                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.013658                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          84894498                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         31757890                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     27813110                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             253784                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            119651                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       117192                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              28643478                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 136104                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          207211                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              28279580                       # Type of FU issued
+system.cpu2.iq.rate                          0.964871                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     382796                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.013536                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          84465202                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         31620396                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     27707676                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             253261                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            119445                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       116967                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              28524107                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 135829                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          206522                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       438819                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1413                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6020                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       178766                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       435956                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1412                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6012                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       178431                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         5023                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       176307                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         5029                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       168380                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                192357                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                4003600                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               328635                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           30811270                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            51966                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3509523                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2229292                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            606230                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 15640                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               265026                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6020                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         63511                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       134698                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              198209                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             28196871                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3506429                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           197351                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                191161                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3997544                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               279888                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           30686163                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            51755                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3488819                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2211142                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            602233                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 15645                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               216255                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6012                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         63410                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       133827                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              197237                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             28083451                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3480678                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           196129                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1384873                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5652310                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 5956275                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2145881                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.955383                       # Inst execution rate
-system.cpu2.iew.wb_sent                      27971955                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     27930302                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 15891558                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 19546280                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1378649                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5608668                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 5940571                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2127990                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.958180                       # Inst execution rate
+system.cpu2.iew.wb_sent                      27865492                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     27824643                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 15848860                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 19489990                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.946351                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.813022                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.949349                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.813179                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2680068                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         193896                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           181086                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     27486207                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.021790                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.858200                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2662629                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         192904                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           180156                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     27293607                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.025131                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.859726                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18368842     66.83%     66.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2248676      8.18%     75.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1182960      4.30%     79.31% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      3745017     13.63%     92.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       544035      1.98%     94.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       201250      0.73%     95.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       165260      0.60%     96.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       179807      0.65%     96.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       850360      3.09%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18211809     66.73%     66.73% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2232896      8.18%     74.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1177901      4.32%     79.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      3741262     13.71%     92.93% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       541174      1.98%     94.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       200137      0.73%     95.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       164418      0.60%     96.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       176928      0.65%     96.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       847082      3.10%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     27486207                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            28085126                       # Number of instructions committed
-system.cpu2.commit.committedOps              28085126                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     27293607                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            27979525                       # Number of instructions committed
+system.cpu2.commit.committedOps              27979525                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5121230                       # Number of memory references committed
-system.cpu2.commit.loads                      3070704                       # Number of loads committed
-system.cpu2.commit.membars                      68250                       # Number of memory barriers committed
-system.cpu2.commit.branches                   5783973                       # Number of branches committed
-system.cpu2.commit.fp_insts                    115466                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 26570607                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              240322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1220562      4.35%      4.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        21327099     75.94%     80.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20651      0.07%     80.36% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     80.36% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20069      0.07%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3138954     11.18%     91.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2052162      7.31%     98.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       304401      1.08%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5085574                       # Number of memory references committed
+system.cpu2.commit.loads                      3052863                       # Number of loads committed
+system.cpu2.commit.membars                      67982                       # Number of memory barriers committed
+system.cpu2.commit.branches                   5768887                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115191                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 26471742                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              239400                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1215445      4.34%      4.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        21266434     76.01%     80.35% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20635      0.07%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     80.42% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20039      0.07%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.50% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3120845     11.15%     91.65% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2034343      7.27%     98.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       300564      1.07%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         28085126                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               850360                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         27979525                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               847082                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    57323983                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   61998256                       # The number of ROB writes
-system.cpu2.timesIdled                         175445                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1558039                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1746293269                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   26867020                       # Number of Instructions Simulated
-system.cpu2.committedOps                     26867020                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.098510                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.098510                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.910324                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.910324                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                36957336                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               19827241                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    70923                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   71075                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                3638892                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                273174                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    57015033                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   61749251                       # The number of ROB writes
+system.cpu2.timesIdled                         174924                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1549032                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1748451761                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   26766520                       # Number of Instructions Simulated
+system.cpu2.committedOps                     26766520                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.094994                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.094994                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.913247                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.913247                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                36812900                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               19756149                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    70792                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   70904                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                3635366                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                270473                       # number of misc regfile writes
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51363                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               9811                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5194                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          756                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18256                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33910                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  117360                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          952                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9128                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        45576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2707184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2201000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy             5523000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy             2073000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer29.occupancy           169052512                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy             9350000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy            17532500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements                41685                       # number of replacements
+system.iocache.tags.tagsinuse                1.262652                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1693890023000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.262652                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078916                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078916                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide      9417462                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9417462                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   5715176550                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   5715176550                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide      9417462                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total      9417462                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide      9417462                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total      9417462                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54436.196532                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 54436.196532                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 54436.196532                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         87544                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9998                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.756151                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5776462                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      5776462                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   4816616550                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4816616550                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide      5776462                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      5776462                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide      5776462                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      5776462                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278739.383681                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278739.383681                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                   337552                       # number of replacements
+system.l2c.tags.tagsinuse                65418.667862                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2487006                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402715                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.175598                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   54698.574366                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2340.440822                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2723.231256                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      572.328176                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      607.228358                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2274.234670                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2202.630214                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.834634                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.035712                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.041553                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.008733                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009266                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.034702                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.033609                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998210                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1015                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5951                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2685                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55344                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26261755                       # Number of tag accesses
+system.l2c.tags.data_accesses                26261755                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             506757                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             483132                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             121571                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              80695                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             322132                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             253945                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1768232                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835902                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835902                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data               8                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  12                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data             8                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            90966                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            25233                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            70678                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               186877                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              506757                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              574098                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              121571                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              105928                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              322132                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              324623                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1955109                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             506757                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             574098                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             121571                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             105928                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             322132                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             324623                       # number of overall hits
+system.l2c.overall_hits::total                1955109                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst             7510                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           238505                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2294                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            16797                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             4575                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            17928                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               287609                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                23                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          75422                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          18351                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          22068                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115841                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst              7510                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            313927                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2294                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             35148                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4575                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             39996                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                403450                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst             7510                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           313927                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2294                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            35148                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4575                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            39996                       # number of overall misses
+system.l2c.overall_misses::total               403450                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    171175250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data   1120981750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    346316750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data   1198339500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2836813250                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       317996                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       317996                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1257891740                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1818546723                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   3076438463                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    171175250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2378873490                       # number of demand (read+write) miss cycles
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+system.l2c.Writeback_accesses::writebacks       835902                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835902                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           23                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              35                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.652174                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.657143                       # miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::cpu1.data     0.421049                       # miss rate for ReadExReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::total 13825.913043                       # average UpgradeReq miss latency
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+system.l2c.overall_avg_miss_latency::total 14656.715115                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
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+system.l2c.writebacks::writebacks               75387                       # number of writebacks
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+system.l2c.UpgradeReq_mshr_misses::total           15                       # number of UpgradeReq MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    974576000                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::total       309012                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu2.data   2523552277                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.data   1938028510                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu2.data   2523552277                       # number of overall MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::total    553284500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    301613500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::total    697427500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716485000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1250712000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018520                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.172291                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014003                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.065943                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020232                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.652174                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.421049                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.237940                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.133520                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018520                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.249142                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014003                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.109693                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034773                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018520                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.249142                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014003                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.109693                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034773                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54217.672799                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54360.553324                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55680.452710                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20600.800000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20600.800000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55982.467440                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70191.058410                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63740.086024                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55139.083589                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63095.116437                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59652.534196                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55139.083589                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63095.116437                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59652.534196                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              294926                       # Transaction distribution
+system.membus.trans_dist::ReadResp             294920                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9811                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9811                       # Transaction distribution
+system.membus.trans_dist::Writeback            116899                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              147                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             149                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115717                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115717                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       882240                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       916162                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124907                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124907                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1041069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30632000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30677576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5323648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5323648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36001224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              140                       # Total snoops (count)
+system.membus.snoop_fanout::samples            562099                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  562099    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              562099                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11803000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy           659094000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy                8000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          769927201                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy           17910500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq            2063113                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2063092                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              9811                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             9811                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           835902                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        17280                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              35                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             45                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302718                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302718                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1929756                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3657397                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5587153                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61750976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142744520                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              204495496                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           41919                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3236289                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012893                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.112812                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3194564     98.71%     98.71% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  41725      1.29%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            3236289                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2206148499                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy        2029921963                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        2294082992                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 405fa6e98..9cf124dc2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,157 +1,154 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.843655                       # Number of seconds simulated
-sim_ticks                                2843654861000                       # Number of ticks simulated
-final_tick                               2843654861000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.844427                       # Number of seconds simulated
+sim_ticks                                2844427140500                       # Number of ticks simulated
+final_tick                               2844427140500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 157498                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190690                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3581426538                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 613612                       # Number of bytes of host memory used
-host_seconds                                   794.00                       # Real time elapsed on the host
-sim_insts                                   125053138                       # Number of instructions simulated
-sim_ops                                     151407658                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 150296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   181972                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3416553864                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 612172                       # Number of bytes of host memory used
+host_seconds                                   832.54                       # Real time elapsed on the host
+sim_insts                                   125127935                       # Number of instructions simulated
+sim_ops                                     151499394                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         9664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker        10304                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1363068                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     10771008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           534304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      1165248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1349820                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     10836800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           503456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      1120064                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13845276                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       418688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        26560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          445248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7176128                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             13821980                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       416640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        27264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          443904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9404288                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.inst         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.inst            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9512208                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          151                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           9422032                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          161                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             21823                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       168297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              8372                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        18207                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             21616                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       169325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7890                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        17501                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                216881                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          112127                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                216517                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          146942                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.inst             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.inst               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               152787                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3398                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               151378                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              479337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3787734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              187893                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       409771                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              474549                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3809836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           180                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              176997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       393775                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4868831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         147236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst           9340                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2523558                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst               6226                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4859319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         146476                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst           9585                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             156061                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3306215                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst               6224                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.inst                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          815266                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3345064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2523558                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3398                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3312453                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3306215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             485562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3787734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             187907                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       409771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          815604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8213896                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        216881                       # Number of read requests accepted
-system.physmem.writeReqs                       152787                       # Number of write requests accepted
-system.physmem.readBursts                      216881                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     152787                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 13864960                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     15424                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9526912                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  13845276                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9512208                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      241                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3914                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          13516                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               13445                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13090                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14400                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               13760                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15799                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12812                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13576                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13750                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13572                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13600                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              13300                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11904                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              13370                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              13720                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              13497                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              13045                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9322                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9428                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10143                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9576                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8974                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8900                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9376                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9386                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9384                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9431                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9355                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8834                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9379                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9206                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9289                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8875                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             480773                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3809836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          180                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             177011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       393775                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                8171773                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        216517                       # Number of read requests accepted
+system.physmem.writeReqs                       187602                       # Number of write requests accepted
+system.physmem.readBursts                      216517                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     187602                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 13846784                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10304                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  11642944                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  13821980                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11740368                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      161                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5664                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          13644                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               13513                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               13311                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               14548                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               14027                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15548                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               13123                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               13508                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               14039                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               13183                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               13181                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              13142                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11743                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              13238                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              14181                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              13272                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12799                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               11429                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               11725                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               12190                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               11854                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10909                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               11199                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11528                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               11643                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               11026                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               11436                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              11468                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              11022                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              11525                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11398                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10974                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10595                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2843652584000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2844424796500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  216294                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  215930                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 148351                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     79253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     62833                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     17902                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     10637                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      9321                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      7490                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      6044                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      425                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      210                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 183166                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     79055                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     63481                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     16932                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12216                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     10702                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      9369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      7427                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      6415                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      442                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      303                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      155                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       92                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -179,156 +176,173 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8963                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    10430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    10909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5952                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19                     8745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    12267                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                    11920                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30                     9631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8901                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      577                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       48                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        92618                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      252.562223                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     143.207145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     307.469960                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46921     50.66%     50.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18876     20.38%     71.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6855      7.40%     78.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3600      3.89%     82.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3008      3.25%     85.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2120      2.29%     87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1341      1.45%     89.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1115      1.20%     90.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8782      9.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          92618                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7463                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.028407                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      529.473600                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7462     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::55                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        93322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      273.137395                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     151.655882                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.256113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45588     48.85%     48.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18736     20.08%     68.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6915      7.41%     76.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3558      3.81%     80.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3108      3.33%     83.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2062      2.21%     85.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1352      1.45%     87.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1057      1.13%     88.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10946     11.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          93322                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7762                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.873744                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      521.384620                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7761     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7463                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7463                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.946134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.603737                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.129560                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6171     82.69%     82.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             489      6.55%     89.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              84      1.13%     90.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             205      2.75%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             200      2.68%     95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              17      0.23%     96.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              17      0.23%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.16%     96.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              25      0.33%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               6      0.08%     96.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.08%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.04%     96.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             165      2.21%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.09%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.08%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              18      0.24%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.09%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.11%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7463                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7683149500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11745149500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1083200000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35465.05                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7762                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7762                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.437387                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.920909                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.626862                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6141     79.12%     79.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             490      6.31%     85.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              77      0.99%     86.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             208      2.68%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             144      1.86%     90.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              54      0.70%     91.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              53      0.68%     92.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              34      0.44%     92.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             115      1.48%     94.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              15      0.19%     94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              16      0.21%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.18%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              31      0.40%     95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              17      0.22%     95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.12%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              24      0.31%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              61      0.79%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               9      0.12%     96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.05%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               7      0.09%     96.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              74      0.95%     97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            12      0.15%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             8      0.10%     98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            21      0.27%     98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             7      0.09%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            12      0.15%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             7      0.09%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            28      0.36%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             9      0.12%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.04%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.12%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             8      0.10%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.04%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             7      0.09%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.04%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.06%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             3      0.04%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             3      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7762                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7644398000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11701073000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1081780000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       35332.50                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54215.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.35                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.35                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  54082.50                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.87                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.09                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.86                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.13                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     183194                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89685                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.56                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  60.24                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7692449.94                       # Average gap between requests
-system.physmem.pageHitRate                      74.66                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2709796310750                       # Time in different power states
-system.physmem.memoryStateTime::REF       94955640000                       # Time in different power states
+system.physmem.avgRdQLen                         1.94                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     183280                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    121675                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.71                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                      7038582.19                       # Average gap between requests
+system.physmem.pageHitRate                      76.57                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2710525028500                       # Time in different power states
+system.physmem.memoryStateTime::REF       94981640000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       38900516750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       38919724000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 358956360                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 341235720                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 195859125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 186190125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                862929600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                826854600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               486680400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               477919440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          185733231840                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          185733231840                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           81937929780                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           81435296655                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1634313275250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1634754181500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1903888862355                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1903754909880                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.523453                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.476347                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 365533560                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 339980760                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 199447875                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 185505375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                870612600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                816964200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               599250960                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               579597120                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          185784087840                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          185784087840                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           82151193285                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           81119552850                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1634593377000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1635498324750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1904563503120                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1904324012895                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.577359                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.493163                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
@@ -353,15 +367,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               34892527                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         17126488                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1674515                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            20008950                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               14462185                       # Number of BTB hits
+system.cpu0.branchPred.lookups               35736686                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         17706973                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1707657                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            20554340                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               14845557                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.278580                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               10813099                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            822816                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.225900                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               10924417                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            815226                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -386,25 +400,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    23969265                       # DTB read hits
-system.cpu0.dtb.read_misses                     62663                       # DTB read misses
-system.cpu0.dtb.write_hits                   17948332                       # DTB write hits
-system.cpu0.dtb.write_misses                     6711                       # DTB write misses
+system.cpu0.dtb.read_hits                    24607000                       # DTB read hits
+system.cpu0.dtb.read_misses                     66402                       # DTB read misses
+system.cpu0.dtb.write_hits                   18455953                       # DTB write hits
+system.cpu0.dtb.write_misses                     6655                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3475                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1396                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1982                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3808                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1234                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2108                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      568                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24031928                       # DTB read accesses
-system.cpu0.dtb.write_accesses               17955043                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      615                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24673402                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18462608                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         41917597                       # DTB hits
-system.cpu0.dtb.misses                          69374                       # DTB misses
-system.cpu0.dtb.accesses                     41986971                       # DTB accesses
+system.cpu0.dtb.hits                         43062953                       # DTB hits
+system.cpu0.dtb.misses                          73057                       # DTB misses
+system.cpu0.dtb.accesses                     43136010                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -426,8 +440,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    70358748                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3854                       # ITB inst misses
+system.cpu0.itb.inst_hits                    71661808                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4142                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -436,123 +450,123 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2220                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2456                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7388                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     8241                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                70362602                       # ITB inst accesses
-system.cpu0.itb.hits                         70358748                       # DTB hits
-system.cpu0.itb.misses                           3854                       # DTB misses
-system.cpu0.itb.accesses                     70362602                       # DTB accesses
-system.cpu0.numCycles                       229119066                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                71665950                       # ITB inst accesses
+system.cpu0.itb.hits                         71661808                       # DTB hits
+system.cpu0.itb.misses                           4142                       # DTB misses
+system.cpu0.itb.accesses                     71665950                       # DTB accesses
+system.cpu0.numCycles                       235973632                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  109189984                       # Number of instructions committed
-system.cpu0.committedOps                    132016369                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      8791665                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1828                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5458204948                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.098352                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.476564                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  111703770                       # Number of instructions committed
+system.cpu0.committedOps                    135097839                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8562554                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1855                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5452894525                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.112495                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.473374                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1830                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      193229301                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       35889765                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           714801                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          493.827802                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           40473769                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           715313                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            56.581901                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        306537500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   493.827802                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.964507                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.964507                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1855                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      199544848                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       36428784                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           751860                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.262864                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           41566353                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           752372                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.247076                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        306713000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   494.262864                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.965357                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.965357                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         83782876                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        83782876                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst     22802755                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       22802755                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst     16862558                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      16862558                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       381551                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       381551                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       362630                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       362630                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst     39665313                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        39665313                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst     39665313                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       39665313                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst       537301                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       537301                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst       532764                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       532764                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6412                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6412                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        20204                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20204                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst      1070065                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1070065                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst      1070065                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1070065                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6609674711                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6609674711                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8019150247                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   8019150247                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    105707749                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    105707749                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    437634051                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    437634051                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       129000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       129000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  14628824958                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  14628824958                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  14628824958                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  14628824958                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23340056                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23340056                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17395322                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17395322                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       387963                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       387963                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       382834                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       382834                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst     40735378                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     40735378                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst     40735378                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     40735378                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023021                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.023021                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030627                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.030627                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016527                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016527                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.052775                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052775                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026269                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026269                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026269                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.026269                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         86104149                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        86104149                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst     23403701                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23403701                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst     17336391                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      17336391                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       390425                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       390425                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       371566                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       371566                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst     40740092                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        40740092                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst     40740092                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       40740092                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst       564897                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       564897                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst       554409                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       554409                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6644                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6644                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        20340                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20340                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst      1119306                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1119306                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst      1119306                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1119306                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6887885459                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6887885459                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8219762503                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8219762503                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    108110000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    108110000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    440070983                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    440070983                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       121000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       121000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  15107647962                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  15107647962                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  15107647962                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  15107647962                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23968598                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23968598                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17890800                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17890800                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       397069                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       397069                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       391906                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391906                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst     41859398                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     41859398                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst     41859398                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     41859398                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023568                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.023568                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030988                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.030988                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016733                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016733                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.051900                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051900                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026740                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026740                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026740                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.026740                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -561,76 +575,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       517954                       # number of writebacks
-system.cpu0.dcache.writebacks::total           517954                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        42678                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        42678                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       230706                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       230706                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst            1                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst       273384                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       273384                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst       273384                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       273384                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       494623                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       494623                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       302058                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       302058                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6411                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6411                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        20204                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20204                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst       796681                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       796681                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst       796681                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       796681                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5117531439                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5117531439                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4270825900                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4270825900                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     92832750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     92832750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    396783949                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    396783949                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       121000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       121000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9388357339                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9388357339                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9388357339                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   9388357339                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6191310497                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6191310497                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4803760492                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4803760492                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  10995070989                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10995070989                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021192                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021192                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017364                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017364                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.052775                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052775                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019557                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.019557                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019557                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.019557                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       541643                       # number of writebacks
+system.cpu0.dcache.writebacks::total           541643                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        45094                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        45094                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       240822                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       240822                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst       285916                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       285916                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst       285916                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       285916                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       519803                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       519803                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       313587                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       313587                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6644                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6644                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        20340                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20340                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst       833390                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       833390                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst       833390                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       833390                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5323715430                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5323715430                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4366940170                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4366940170                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     94806000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94806000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    398879017                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    398879017                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       115000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       115000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9690655600                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9690655600                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9690655600                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9690655600                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6196262496                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6196262496                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4811489492                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4811489492                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  11007751988                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11007751988                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021687                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021687                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017528                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017528                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016733                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016733                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.051900                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051900                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019909                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.019909                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019909                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.019909                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -638,58 +650,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1983566                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.796833                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           68366923                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1984078                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.457780                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6227191000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.796833                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999603                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999603                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          2070442                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.797171                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           69582233                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          2070954                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            33.599121                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6297775000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.797171                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999604                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          106                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        142686127                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       142686127                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     68366923                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       68366923                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     68366923                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        68366923                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     68366923                       # number of overall hits
-system.cpu0.icache.overall_hits::total       68366923                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1984094                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1984094                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1984094                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1984094                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1984094                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1984094                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16546799645                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  16546799645                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  16546799645                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  16546799645                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  16546799645                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  16546799645                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     70351017                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     70351017                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     70351017                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     70351017                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     70351017                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     70351017                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028203                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028203                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028203                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028203                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028203                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028203                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8339.725661                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8339.725661                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8339.725661                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8339.725661                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8339.725661                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8339.725661                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        145377375                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       145377375                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     69582233                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       69582233                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     69582233                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        69582233                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     69582233                       # number of overall hits
+system.cpu0.icache.overall_hits::total       69582233                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      2070970                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2070970                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      2070970                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2070970                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      2070970                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2070970                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17258012980                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17258012980                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  17258012980                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17258012980                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  17258012980                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17258012980                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     71653203                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     71653203                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     71653203                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     71653203                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     71653203                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     71653203                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028903                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028903                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028903                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028903                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028903                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028903                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8333.299362                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8333.299362                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8333.299362                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8333.299362                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8333.299362                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8333.299362                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -698,326 +710,313 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1984094                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1984094                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1984094                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1984094                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1984094                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1984094                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13568682853                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  13568682853                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13568682853                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  13568682853                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13568682853                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  13568682853                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    276787500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    276787500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    276787500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    276787500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028203                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028203                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028203                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028203                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6838.729845                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  6838.729845                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6838.729845                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  6838.729845                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2070970                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      2070970                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      2070970                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      2070970                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      2070970                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      2070970                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  14149699520                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  14149699520                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  14149699520                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  14149699520                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  14149699520                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  14149699520                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    276493750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    276493750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    276493750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    276493750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028903                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028903                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028903                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6832.401976                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  6832.401976                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  6832.401976                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     17337039                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       425762                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     16383461                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9078                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     18115074                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       431506                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     17132776                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9283                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         6456                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       512279                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      1329409                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         6596                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       534910                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      1383846                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          409357                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16202.462840                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3013500                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          425611                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.080409                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4205.324174                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    51.364575                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.062072                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2198.474976                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9747.237044                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.256673                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003135                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.replacements          428439                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16212.256950                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3152645                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          444682                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            7.089662                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle    2824980212500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  4226.197620                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    50.775812                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065487                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2187.555983                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9747.662049                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.257947                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003099                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.134184                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.594924                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988920                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8963                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7281                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           54                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          134                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2805                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5150                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          820                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3125                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3482                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          341                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.547058                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.444397                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        55309059                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       55309059                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77781                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4268                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2390782                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       2472831                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       517951                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       517951                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4630                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total         4630                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         2244                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2244                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       223140                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       223140                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77781                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4268                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      2613922                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2695971                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77781                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4268                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      2613922                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2695971                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          986                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          173                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        94341                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        95500                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        27941                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27941                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        17958                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        17958                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        46352                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        46352                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          986                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          173                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       140693                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       141852                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          986                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          173                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       140693                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       141852                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     32261749                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3849999                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2894443882                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   2930555630                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    497270548                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    497270548                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    354837739                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    354837739                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       117000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       117000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   1925679719                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   1925679719                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     32261749                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3849999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4820123601                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   4856235349                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     32261749                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3849999                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4820123601                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   4856235349                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78767                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4441                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2485123                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      2568331                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       517951                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       517951                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        32571                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        32571                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        20202                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20202                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       269492                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269492                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78767                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4441                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      2754615                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2837823                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78767                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4441                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      2754615                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2837823                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.037962                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.037184                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.857849                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.857849                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.888922                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.888922                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.171998                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171998                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.051075                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.049986                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.012518                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.038955                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.051075                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.049986                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst        58500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total        58500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        25463                       # number of cycles access was blocked
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.133518                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.594950                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.989518                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8981                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7254                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           61                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          111                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2870                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5529                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          410                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3049                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3651                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          230                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.548157                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.442749                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        57799798                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       57799798                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        84149                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4243                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2500411                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total       2588803                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       541643                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       541643                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4674                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total         4674                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         2411                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         2411                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       234433                       # number of ReadExReq hits
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+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        84149                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::total       2823236                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          906                       # number of ReadReq misses
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+system.cpu0.l2cache.UpgradeReq_misses::total        27960                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        17929                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          906                       # number of demand (read+write) misses
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+system.cpu0.l2cache.demand_misses::total       144570                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          906                       # number of overall misses
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+system.cpu0.l2cache.overall_misses::cpu0.inst       143526                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       144570                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     31530500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3231999                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2954004148                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   2988766647                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    497244183                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    497244183                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    356127296                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    356127296                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       112000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       112000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   1936152477                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   1936152477                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     31530500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3231999                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4890156625                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   4924919124                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     31530500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3231999                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4890156625                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   4924919124                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        85055                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2597412                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      2686848                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       541643                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       541643                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        32634                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        32634                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        20340                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20340                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       280958                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       280958                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        85055                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.demand_accesses::cpu0.inst      2878370                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        85055                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.inst      2878370                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2967806                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.037345                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.036491                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.856775                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.856775                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.881465                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.881465                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.165594                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.165594                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.049864                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.048713                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.049864                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.048713                       # miss rate for overall accesses
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+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058                       # average ReadReq miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs        25119                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs             375                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs             346                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    67.901333                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    72.598266                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       214094                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          214094                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         7763                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         7763                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3115                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         3115                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        10878                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        10878                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        10878                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        10878                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          986                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          173                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        86578                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        87737                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       512278                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       512278                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        27941                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27941                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        17958                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17958                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        43237                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        43237                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          986                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          173                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       129815                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       130974                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          986                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          173                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       129815                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       512278                       # number of overall MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2121502252                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2149486002                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21334624793                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21334624793                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    476101816                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    476101816                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    237455029                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    237455029                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst        89000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        89000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1189409987                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1189409987                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2638999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3310912239                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   3338895989                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     25344751                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2638999                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3310912239                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21334624793                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  24673520782                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6176243748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6176243748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4587514507                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4587514507                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10763758255                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10763758255                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.034839                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.034161                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.writebacks::writebacks       220063                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          220063                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         8315                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total         8315                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3034                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         3034                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        11349                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        11349                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        11349                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        11349                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          906                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          138                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        88686                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        89730                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       534906                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       534906                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        27960                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27960                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        17929                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17929                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        43491                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        43491                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          906                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          138                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       132177                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       133221                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          906                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          138                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       132177                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       534906                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       668127                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2160848492                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2188282991                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21648732719                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21648732719                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    481473058                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    481473058                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    238593946                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    238593946                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst        91000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        91000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1198815233                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1198815233                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3359663725                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   3387098224                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3359663725                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21648732719                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  25035830943                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6180670251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6180670251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4594924508                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4594924508                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10775594759                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10775594759                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.034144                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.033396                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.857849                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.857849                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.888922                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.888922                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.160439                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.160439                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.047126                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.046153                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.012518                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.038955                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.047126                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.856775                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.856775                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.881465                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.881465                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.154795                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.154795                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.045921                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.044889                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.045921                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226671                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst        44500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total        44500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.225125                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1025,67 +1024,67 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       2765429                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2670282                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28813                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28813                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       517951                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       696439                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        70465                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42615                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        93717                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       291656                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       282057                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3974309                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2393187                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11845                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       168040                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6547381                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    127177856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86874167                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17764                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       315068                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         214384855                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1083965                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4385734                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.219720                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.414057                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq       2861093                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2792980                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28855                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28855                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       541643                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       731101                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        68486                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42622                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        93982                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       302729                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       293421                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      4148051                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2491359                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12339                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       183942                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6835691                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    132737600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     90757533                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17524                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       340220                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         223852877                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1093341                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4548807                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.213001                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.409428                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           3422100     78.03%     78.03% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            963634     21.97%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           3579907     78.70%     78.70% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            968900     21.30%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4385734                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2275890990                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4548807                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2378574445                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    119346000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    119537998                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2982392646                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   3112636730                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1235371968                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1291088389                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7407493                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7963988                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     89292476                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     98908477                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                4040174                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2339682                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           248924                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2652147                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1629183                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3448752                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          1941981                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           196391                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2221819                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1396869                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            61.428835                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 794888                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             55483                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            62.870513                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 715789                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             52420                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1109,25 +1108,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4061400                       # DTB read hits
-system.cpu1.dtb.read_misses                     20326                       # DTB read misses
-system.cpu1.dtb.write_hits                    3327397                       # DTB write hits
-system.cpu1.dtb.write_misses                     1493                       # DTB write misses
+system.cpu1.dtb.read_hits                     3432223                       # DTB read hits
+system.cpu1.dtb.read_misses                     19764                       # DTB read misses
+system.cpu1.dtb.write_hits                    2826731                       # DTB write hits
+system.cpu1.dtb.write_misses                     1392                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2042                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      130                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   315                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1674                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      101                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   224                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      275                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4081726                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3328890                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      209                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3451987                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2828123                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7388797                       # DTB hits
-system.cpu1.dtb.misses                          21819                       # DTB misses
-system.cpu1.dtb.accesses                      7410616                       # DTB accesses
+system.cpu1.dtb.hits                          6258954                       # DTB hits
+system.cpu1.dtb.misses                          21156                       # DTB misses
+system.cpu1.dtb.accesses                      6280110                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1149,8 +1148,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     7665717                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2240                       # ITB inst misses
+system.cpu1.itb.inst_hits                     6653879                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1856                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1159,122 +1158,122 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1155                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     882                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1927                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1128                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7667957                       # ITB inst accesses
-system.cpu1.itb.hits                          7665717                       # DTB hits
-system.cpu1.itb.misses                           2240                       # DTB misses
-system.cpu1.itb.accesses                      7667957                       # DTB accesses
-system.cpu1.numCycles                        40520229                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 6655735                       # ITB inst accesses
+system.cpu1.itb.hits                          6653879                       # DTB hits
+system.cpu1.itb.misses                           1856                       # DTB misses
+system.cpu1.itb.accesses                      6655735                       # DTB accesses
+system.cpu1.numCycles                        36145472                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   15863154                       # Number of instructions committed
-system.cpu1.committedOps                     19391289                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1555006                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2808                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5646190749                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.554361                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.391487                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   13424165                       # Number of instructions committed
+system.cpu1.committedOps                     16401555                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1287407                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5652095397                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.692568                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.371393                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2810                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       29462484                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       11057745                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           188500                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          474.724355                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6998456                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           188865                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            37.055336                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     107393225500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   474.724355                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.927196                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.927196                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         14854828                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        14854828                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst      3752021                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3752021                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst      3051608                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3051608                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        88860                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88860                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        69213                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        69213                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst      6803629                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         6803629                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst      6803629                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        6803629                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst       182037                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       182037                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst       139457                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       139457                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5164                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         5164                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        23160                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23160                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst       321494                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        321494                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst       321494                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       321494                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2747896424                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2747896424                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3339347493                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3339347493                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     93721501                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     93721501                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    540094758                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    540094758                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       317500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       317500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst   6087243917                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6087243917                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst   6087243917                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6087243917                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3934058                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3934058                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst      3191065                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3191065                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        94024                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        94024                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        92373                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92373                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst      7125123                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      7125123                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst      7125123                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      7125123                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.046272                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.046272                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043702                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.043702                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.054922                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054922                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.250723                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250723                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.045121                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.045121                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.045121                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.045121                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       26236459                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                        9909013                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           149765                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          476.829408                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5935391                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           150124                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.536590                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     107725830000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   476.829408                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.931307                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.931307                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12574886                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12574886                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst      3167382                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3167382                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst      2587127                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2587127                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        79870                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        79870                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        60510                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        60510                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst      5754509                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5754509                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst      5754509                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5754509                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst       151161                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       151161                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst       116953                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       116953                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5079                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5079                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        22818                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        22818                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst       268114                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        268114                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst       268114                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       268114                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2359046468                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2359046468                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3063915205                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   3063915205                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     93260000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     93260000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    534664798                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    534664798                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       106500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       106500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst   5422961673                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   5422961673                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst   5422961673                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   5422961673                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3318543                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3318543                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst      2704080                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2704080                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        84949                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        84949                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        83328                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        83328                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst      6022623                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6022623                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst      6022623                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6022623                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.045550                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.045550                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043251                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.043251                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.059789                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.059789                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.273834                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273834                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.044518                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.044518                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.044518                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044518                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1283,74 +1282,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       115754                       # number of writebacks
-system.cpu1.dcache.writebacks::total           115754                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        15456                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        15456                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        49471                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        49471                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst        64927                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        64927                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst        64927                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        64927                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       166581                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       166581                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        89986                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        89986                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5164                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5164                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        23160                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23160                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst       256567                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       256567                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst       256567                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       256567                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2204876516                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2204876516                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   1996537354                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1996537354                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     83385499                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83385499                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    492548242                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    492548242                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       303500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       303500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   4201413870                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4201413870                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   4201413870                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4201413870                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    329634997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    329634997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    202961999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    202961999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    532596996                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    532596996                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042343                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042343                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.028199                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028199                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.054922                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054922                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.250723                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250723                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.036009                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.036009                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.036009                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.036009                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks        93707                       # number of writebacks
+system.cpu1.dcache.writebacks::total            93707                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        11593                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        11593                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        39187                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        39187                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst        50780                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        50780                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst        50780                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        50780                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       139568                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       139568                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        77766                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        77766                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5079                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5079                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        22818                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        22818                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst       217334                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       217334                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst       217334                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       217334                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   1914681986                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1914681986                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   1867013423                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1867013423                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     83091000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83091000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    487833202                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    487833202                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       100500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       100500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   3781695409                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3781695409                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   3781695409                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3781695409                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    327471996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    327471996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    198424999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    198424999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    525896995                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    525896995                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042057                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042057                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.028759                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028759                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.059789                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.059789                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.273834                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273834                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.036086                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.036086                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.036086                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.036086                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1358,57 +1357,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           893030                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.459009                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6770083                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           893542                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             7.576681                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      71221486500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.459009                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975506                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975506                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           827152                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.447245                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            5824947                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           827664                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.037816                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      71343314500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.447245                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975483                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975483                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           48                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          469                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         16220792                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        16220792                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6770083                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6770083                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6770083                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6770083                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6770083                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6770083                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       893542                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       893542                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       893542                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        893542                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       893542                       # number of overall misses
-system.cpu1.icache.overall_misses::total       893542                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7266670468                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7266670468                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7266670468                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7266670468                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7266670468                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7266670468                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7663625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7663625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7663625                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7663625                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7663625                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7663625                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.116595                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.116595                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.116595                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.116595                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.116595                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.116595                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8132.433023                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8132.433023                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8132.433023                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8132.433023                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8132.433023                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8132.433023                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14132886                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14132886                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      5824947                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5824947                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      5824947                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         5824947                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      5824947                       # number of overall hits
+system.cpu1.icache.overall_hits::total        5824947                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       827664                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       827664                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       827664                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        827664                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       827664                       # number of overall misses
+system.cpu1.icache.overall_misses::total       827664                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6712177482                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6712177482                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6712177482                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6712177482                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6712177482                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6712177482                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      6652611                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      6652611                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      6652611                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      6652611                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      6652611                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      6652611                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124412                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.124412                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124412                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.124412                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124412                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.124412                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8109.785471                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8109.785471                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8109.785471                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8109.785471                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8109.785471                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8109.785471                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1417,310 +1417,310 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       893542                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       893542                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       893542                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       893542                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       893542                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       893542                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5923954530                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5923954530                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5923954530                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5923954530                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5923954530                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5923954530                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10589750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10589750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10589750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10589750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.116595                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.116595                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.116595                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.116595                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6629.743795                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6629.743795                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6629.743795                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6629.743795                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       827664                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       827664                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       827664                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       827664                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       827664                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       827664                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5467532518                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5467532518                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5467532518                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5467532518                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5467532518                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5467532518                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10038000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10038000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10038000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10038000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124412                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.124412                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.124412                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6605.980830                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  6605.980830                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  6605.980830                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      7064659                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        40510                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      6914419                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         1409                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      6453687                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        29592                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      6340817                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          898                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2627                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       105694                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       724613                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2376                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued        80004                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       668025                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           80002                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15534.005683                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1138706                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           95380                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           11.938624                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements           52740                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15520.178150                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1029232                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           68128                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           15.107327                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6881.050205                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    26.485106                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.098583                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2338.762949                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6287.608842                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.419986                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001617                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.142747                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.383765                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.948120                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022        10071                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           34                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5273                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          132                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         6676                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         3263                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          237                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3167                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1869                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.614685                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002075                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.321838                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        21370209                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       21370209                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        22701                       # number of ReadReq hits
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-system.cpu1.l2cache.Writeback_hits::writebacks       115754                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       115754                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1810                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1810                       # number of UpgradeReq hits
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total    531483393                       # number of UpgradeReq miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst       296000                       # number of SCUpgradeFailReq miss cycles
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-system.cpu1.l2cache.ReadExReq_miss_latency::total   1126750383                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     13239000                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     13239000                       # number of overall miss cycles
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-system.cpu1.l2cache.overall_miss_latency::total   2768595021                       # number of overall miss cycles
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-system.cpu1.l2cache.Writeback_accesses::writebacks       115754                       # number of Writeback accesses(hits+misses)
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-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        29950                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29950                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        23160                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23160                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.overall_accesses::cpu1.inst      1125323                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1151310                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.090604                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.067774                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.066936                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.939566                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.939566                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.968048                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.968048                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.537011                       # miss rate for ReadExReq accesses
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-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.092808                       # miss rate for demand accesses
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-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.090604                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.092808                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.091449                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491                       # average SCUpgradeReq miss latency
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.084140                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2337.993929                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6253.257565                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.421239                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001664                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.393188                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.Writeback_hits::writebacks        93707                       # number of Writeback hits
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+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst        97500                       # number of SCUpgradeFailReq miss cycles
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+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        23273                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2534                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      1020747                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1046554                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        23273                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2534                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      1020747                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1046554                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.068367                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.067550                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.947187                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.947187                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.976641                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.976641                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.622202                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.622202                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.094647                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.093220                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.094647                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.093220                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         4629                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         2801                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs             159                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              79                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    29.113208                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    35.455696                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        38442                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           38442                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1604                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total         1604                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          322                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          322                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1926                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1926                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1926                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1926                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          604                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          243                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        70595                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        71442                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       105694                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       105694                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        28140                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28140                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22420                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22420                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        31918                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31918                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          604                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          243                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       102513                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       103360                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          604                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          243                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       102513                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       105694                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       209054                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   1098179235                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1110385737                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2958247424                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   2958247424                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    404415795                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    404415795                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    308218727                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308218727                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst       247000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       247000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst    862164082                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    862164082                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1960343317                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   1972549819                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9008002                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3198500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1960343317                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2958247424                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4930797243                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    316625253                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    316625253                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    186937501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    186937501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    503562754                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    503562754                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.066269                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.065467                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks        30368                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           30368                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          950                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          950                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          295                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          295                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1245                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1245                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1245                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1245                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          704                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          245                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        65524                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        66473                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        80004                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        80004                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        27781                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27781                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22285                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22285                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        29842                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        29842                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          704                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          245                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        95366                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total        96315                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          704                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          245                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        95366                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        80004                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       176319                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    981688737                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    994327236                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2522312930                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   2522312930                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    396174942                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    396174942                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    306073762                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306073762                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst        76500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        76500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst    831450098                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    831450098                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1813138835                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   1825777334                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1813138835                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2522312930                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4348090264                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    313994504                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    313994504                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    182561501                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    182561501                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    496556005                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    496556005                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.067390                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.066598                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.939566                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.939566                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.968048                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.968048                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.531648                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.531648                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.091097                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.089776                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.025917                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.090604                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.091097                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.947187                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.947187                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.976641                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.976641                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.616112                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.616112                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.093428                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.092031                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.093428                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.181579                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.168476                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273                       # average SCUpgradeReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1728,64 +1728,64 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1582615                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1137834                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2120                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2120                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       115754                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       151048                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        84372                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41116                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85179                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        76804                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        64396                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1787314                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       769072                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6988                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        51360                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2614734                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     57194048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24925415                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        93220                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          82223411                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     838592                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      2085067                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.363773                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.481085                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq       1502965                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1041469                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2098                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2098                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback        93707                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       114724                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        83933                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40744                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        84523                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        65298                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        52790                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1655558                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       667978                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6105                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        48641                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2378282                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     52977856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     21039827                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        93092                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          74120911                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     816365                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1934720                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.382054                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.485890                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5           1326575     63.62%     63.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            758492     36.38%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1195552     61.79%     61.79% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            739168     38.21%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       2085067                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     782771935                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1934720                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     695166718                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     78513000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     78719500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1341710719                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1243267482                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    381436893                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    322631890                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4307996                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      3571998                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     28057498                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     25370995                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59407                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           33                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                31020                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31020                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59447                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              23223                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56686                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -1806,11 +1806,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       108000                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71630                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -1831,11 +1831,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162880                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484026                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40158000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1875,508 +1875,517 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326658321                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347075142                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84777000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36824131                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36822606                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36417                       # number of replacements
-system.iocache.tags.tagsinuse                0.992159                       # Cycle average of tags in use
+system.iocache.tags.replacements                36433                       # number of replacements
+system.iocache.tags.tagsinuse                0.995239                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36433                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         268855800000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.992159                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062010                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062010                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         269184120000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.995239                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062202                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062202                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328467                       # Number of tag accesses
-system.iocache.tags.data_accesses              328467                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
+system.iocache.tags.data_accesses              328203                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           33                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           33                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          243                       # number of overall misses
 system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31254127                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31254127                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31254127                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31254127                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31254127                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31254127                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     30315377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30315377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9644186159                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9644186159                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30315377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30315377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30315377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30315377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36257                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36257                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000910                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000910                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128617.806584                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128617.806584                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128617.806584                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128617.806584                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128617.806584                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124754.637860                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124754.637860                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124754.637860                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124754.637860                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124754.637860                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         57278                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7269                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.879763                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18617627                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18617627                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2261621825                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2261621825                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18617627                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18617627                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18617627                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18617627                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17678377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17678377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7760326371                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7760326371                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17678377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17678377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17678377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17678377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76615.748971                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76615.748971                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72750.522634                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72750.522634                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   151810                       # number of replacements
-system.l2c.tags.tagsinuse                64480.586594                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     529933                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   216565                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.446993                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   150396                       # number of replacements
+system.l2c.tags.tagsinuse                64479.883220                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     522727                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   215317                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.427709                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12374.174406                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    81.831156                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030524                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3874.361594                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.891665                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      757.615436                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4654.298093                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.188815                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001249                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.059118                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.651968                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000166                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.011560                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.071019                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983896                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        46322                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        18386                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6596                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        39440                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           47                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          273                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2604                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        15495                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.706818                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000717                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.280548                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6644341                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6644341                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker          563                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker          116                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst              36701                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       207577                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker          129                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           56                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              11433                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        45418                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 301993                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          252536                       # number of Writeback hits
-system.l2c.Writeback_hits::total               252536                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.inst           11942                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst             830                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               12772                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst           205                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst           179                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               384                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.inst             3525                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst             1107                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 4632                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           563                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           116                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               40226                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       207577                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           129                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            56                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               12540                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher        45418                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  306625                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          563                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker          116                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              40226                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       207577                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          129                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           56                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              12540                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher        45418                       # number of overall hits
-system.l2c.overall_hits::total                 306625                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker          151                       # number of ReadReq misses
+system.l2c.tags.occ_blocks::writebacks   12469.492368                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    93.733463                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.999899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3818.005633                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.718540                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      732.215158                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4549.115372                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.190269                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001430                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.058258                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.653238                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000087                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2          270                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2310                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        14797                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.724136                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.001038                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.265442                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6561930                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6561930                       # Number of data accesses
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 system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
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 system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
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-system.l2c.ReadReq_miss_rate::total          0.398184                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.430520                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.762518                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.477948                       # miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_miss_rate::total     0.817056                       # miss rate for SCUpgradeReq accesses
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-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.104167                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.397173                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.286172                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.410173                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.211485                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.008547                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.312646                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.447748                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.104167                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.397173                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.286172                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.410173                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1551498150                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  18265787207                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       597000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    590840495                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1914570464                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    22336192316                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker          737                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker          132                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst          50775                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       390859                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker          102                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker           19                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst           8241                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        43446                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             494311                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       250431                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           250431                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.inst        21362                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.inst         2722                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           24084                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.inst          711                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.inst         1406                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2117                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.inst        10615                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.inst         7337                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            17952                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          737                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker          132                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           61390                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       390859                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker          102                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           19                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           15578                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        43446                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              512263                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          737                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker          132                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          61390                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       390859                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          102                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           19                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          15578                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        43446                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             512263                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.218453                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.007576                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.221684                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.433960                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.078431                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.162723                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.402822                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.404371                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.448460                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.823292                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.490824                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.741210                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.863442                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.822390                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.inst     0.656524                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.inst     0.876244                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.746324                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.218453                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.007576                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.296872                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.433960                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.078431                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.498780                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.402822                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.416354                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.218453                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.007576                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.296872                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.433960                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.078431                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.498780                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.416354                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79652.173913                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76700                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 106484.162995                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1166.158064                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  1026.786116                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1134.393227                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  2454.344902                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   802.996810                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1246.886880                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 79609.130467                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74625                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 106384.709543                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1069.898121                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  1066.442660                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1069.243042                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  2496.111954                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   885.465404                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1373.007467                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 79973.477310                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        76700                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 104792.618090                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::total 104725.610180                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        76700                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 104792.618090                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               845                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74625                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 104725.610180                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       26                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     32.500000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              112127                       # number of writebacks
-system.l2c.writebacks::total                   112127                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks              110752                       # number of writebacks
+system.l2c.writebacks::total                   110752                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          151                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          161                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11286                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       168297                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1852                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        18207                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          199809                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst         9028                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2665                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11693                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          461                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1254                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1715                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst         7011                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.inst         6410                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         13421                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          151                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        11256                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       169616                       # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::cpu0.inst         9580                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2241                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11821                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          527                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1214                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        18297                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.inst         8262                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        18207                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           213230                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker          151                       # number of overall MSHR misses
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+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       169616                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         7770                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        17501                       # number of demand (read+write) MSHR misses
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 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     26828647                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    118025600                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
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 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5518590247                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    263108750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5781698997                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    150494000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4246495500                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    413602750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10028194497                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.235189                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::total     0.398182                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.762518                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.477948                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.692192                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.875087                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.817056                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.852734                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.743422                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.312646                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.104167                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.397173                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286157                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.410171                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.211485                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.008547                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.312646                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.104167                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.397173                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286157                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.410171                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average ReadReq mshr miss latency
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    260648000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5783076749                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    146450000                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  10032106248                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.221684                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.162723                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total     0.404369                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.448460                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.823292                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.490824                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.741210                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.863442                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.822390                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.876244                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.746324                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.007576                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.296872                       # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.078431                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.498780                       # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::total      0.416353                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.007576                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.296872                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.498780                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total     0.416353                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 92466.253407                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 92386.824795                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 92466.253407                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 92386.824795                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2387,57 +2396,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              238091                       # Transaction distribution
-system.membus.trans_dist::ReadResp             238091                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30933                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30933                       # Transaction distribution
-system.membus.trans_dist::Writeback            112127                       # Transaction distribution
+system.membus.trans_dist::ReadReq              238185                       # Transaction distribution
+system.membus.trans_dist::ReadResp             238185                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30953                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30953                       # Transaction distribution
+system.membus.trans_dist::Writeback            146942                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            79652                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          39985                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13516                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             30363                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            13313                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq            78292                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          39832                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13662                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             30241                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            13298                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       108000                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       704934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       826518                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72706                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72706                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 899224                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13634                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       701758                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       823430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108896                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108896                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 932326                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162880                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21038188                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     21229406                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23548702                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123399                       # Total snoops (count)
-system.membus.snoop_fanout::samples            498406                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27268                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     20926892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     21118256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                25753712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           122070                       # Total snoops (count)
+system.membus.snoop_fanout::samples            531658                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  498406    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  531658    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              498406                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87864494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              531658                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88755994                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11666999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11894500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1620379248                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1935574499                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2120601580                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2123782192                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38542869                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38517394                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2470,44 +2479,44 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             668340                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            668325                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30933                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30933                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           252536                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           92316                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40369                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         132685                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           11                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            38932                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           38932                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1370044                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       368770                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1738814                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     41959415                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7901735                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               49861150                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          291964                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1090717                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.033437                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.179774                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq             658320                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            658305                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30953                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30953                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           250431                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           90455                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40208                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         130663                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            38633                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           38633                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1411505                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       304961                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1716466                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     43486557                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5753747                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               49240304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          287552                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1076220                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.033884                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.180932                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1054247     96.66%     96.66% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36470      3.34%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1039753     96.61%     96.61% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36467      3.39%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1090717                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1589301055                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1076220                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1573537018                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy          1026000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2361799867                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2438104006                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         804005619                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         680349684                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 8921a3479..1c98029fc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,119 +1,116 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.852237                       # Number of seconds simulated
-sim_ticks                                2852237227000                       # Number of ticks simulated
-final_tick                               2852237227000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.852850                       # Number of seconds simulated
+sim_ticks                                2852849954000                       # Number of ticks simulated
+final_tick                               2852849954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 157725                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190692                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4039440180                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 566224                       # Number of bytes of host memory used
-host_seconds                                   706.10                       # Real time elapsed on the host
-sim_insts                                   111368950                       # Number of instructions simulated
-sim_ops                                     134647110                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 160685                       # Simulator instruction rate (inst/s)
+host_op_rate                                   194286                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4092855045                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 562916                       # Number of bytes of host memory used
+host_seconds                                   697.03                       # Real time elapsed on the host
+sim_insts                                   112002684                       # Number of instructions simulated
+sim_ops                                     135423332                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         6208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10897572                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10823844                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10904868                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1667392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1667392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5682816                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10832740                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1658560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1658560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7967296                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.inst          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8018676                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           97                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             170794                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7984820                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             169642                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170908                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           88794                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                169781                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124489                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.inst              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129399                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2177                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              3820710                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               128870                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2759                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3794046                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3823268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          584591                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             584591                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1992407                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst                6144                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          812813                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2811364                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1992407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2177                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3826854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          813150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6634632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170908                       # Number of read requests accepted
-system.physmem.writeReqs                       129399                       # Number of write requests accepted
-system.physmem.readBursts                      170908                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129399                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10927552                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10560                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8032256                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10904868                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8018676                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      165                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3869                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4597                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10514                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10246                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10769                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10552                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13499                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10126                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11178                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10889                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10887                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10100                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9610                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10315                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11222                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10292                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10316                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7730                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7667                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8410                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8128                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7856                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7340                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8209                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8042                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7786                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8073                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7525                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7421                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7760                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8405                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7549                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7603                       # Per bank write bursts
+system.physmem.bw_read::total                 3797164                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          581370                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             581370                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2792750                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst                6143                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2798892                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2792750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3800189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6596057                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        169781                       # Number of read requests accepted
+system.physmem.writeReqs                       165094                       # Number of write requests accepted
+system.physmem.readBursts                      169781                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     165094                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10858880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10194112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10832740                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10303156                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5787                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4592                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10675                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10570                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10940                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10884                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12996                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10666                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11098                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10877                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10287                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10457                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10268                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9318                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10425                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10908                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9678                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9623                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10097                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10006                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10747                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10511                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9282                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9914                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10247                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10166                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10178                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10302                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10037                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9553                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10068                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10279                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8984                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8912                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2852236741500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2852849531000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  170353                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169226                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125018                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164527                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 160713                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    162999                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -158,154 +155,173 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1957                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6500                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        60829                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.689227                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.313026                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.369125                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22276     36.62%     36.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14416     23.70%     60.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6737     11.08%     71.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3572      5.87%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2597      4.27%     81.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1607      2.64%     84.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1084      1.78%     85.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1076      1.77%     87.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7464     12.27%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          60829                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6321                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.008859                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      576.510415                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6319     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6321                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6321                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.855086                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.377929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.560499                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5522     87.36%     87.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              41      0.65%     88.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              34      0.54%     88.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             217      3.43%     91.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             214      3.39%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              10      0.16%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              16      0.25%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              20      0.32%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              24      0.38%     96.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.06%     96.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.03%     96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.03%     96.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             162      2.56%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.08%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.05%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              12      0.19%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.11%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             5      0.08%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.11%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6321                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1722371500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4923802750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    853715000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10087.51                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9997                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9441                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8955                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62892                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      334.747313                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.220308                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     348.895470                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22415     35.64%     35.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14531     23.10%     58.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6612     10.51%     69.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3482      5.54%     74.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2506      3.98%     78.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1581      2.51%     81.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1054      1.68%     82.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1133      1.80%     84.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9578     15.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62892                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6668                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.444061                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      561.318574                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6666     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6668                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6668                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.887672                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.937507                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.272912                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5557     83.34%     83.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              39      0.58%     83.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              24      0.36%     84.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             223      3.34%     87.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             119      1.78%     89.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              51      0.76%     90.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              29      0.43%     90.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              45      0.67%     91.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             120      1.80%     93.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.18%     93.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              15      0.22%     93.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.21%     93.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              30      0.45%     94.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              19      0.28%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.12%     94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              35      0.52%     95.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              60      0.90%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               9      0.13%     96.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.09%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              14      0.21%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             100      1.50%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            13      0.19%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             8      0.12%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            22      0.33%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            10      0.15%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            27      0.40%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             9      0.13%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.06%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             8      0.12%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.07%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.04%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6668                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1702635750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4883948250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    848350000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10034.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28837.51                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.83                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.82                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.81                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28784.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.61                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.39                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     140948                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94469                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.26                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9497736.45                       # Average gap between requests
-system.physmem.pageHitRate                      79.46                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2712717626000                       # Time in different power states
-system.physmem.memoryStateTime::REF       95242420000                       # Time in different power states
+system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139924                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    126136                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.47                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.18                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8519147.54                       # Average gap between requests
+system.physmem.pageHitRate                      80.87                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2713515031250                       # Time in different power states
+system.physmem.memoryStateTime::REF       95262700000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       44277091000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       44072132750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 234707760                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 225159480                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 128064750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 122854875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                684629400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                647158200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               410715360                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               402550560                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          186294173520                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          186294173520                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           83068916085                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           82611072135                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1638474130500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1638875748000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1909295337375                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1909178716770                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.403001                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.362113                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 246765960                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 228697560                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 134644125                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 124785375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                691906800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                631511400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               524685600                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               507468240                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          186333841200                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          186333841200                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           83199782385                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           82045768365                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1638723732000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1639736025000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1909855358070                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1909608097140                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.456797                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.370126                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
@@ -324,15 +340,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                30773662                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16735793                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2481146                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18414792                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13204104                       # Number of BTB hits
+system.cpu.branchPred.lookups                31051775                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16857996                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2519060                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18534749                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13337392                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.703791                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7765871                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1476448                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             71.958849                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7856975                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1512712                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -357,25 +373,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24574985                       # DTB read hits
-system.cpu.dtb.read_misses                      58557                       # DTB read misses
-system.cpu.dtb.write_hits                    19368965                       # DTB write hits
-system.cpu.dtb.write_misses                      5915                       # DTB write misses
+system.cpu.dtb.read_hits                     24746159                       # DTB read hits
+system.cpu.dtb.read_misses                      60199                       # DTB read misses
+system.cpu.dtb.write_hits                    19443156                       # DTB write hits
+system.cpu.dtb.write_misses                      6950                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4353                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1231                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1821                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4352                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1306                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1783                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       755                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24633542                       # DTB read accesses
-system.cpu.dtb.write_accesses                19374880                       # DTB write accesses
+system.cpu.dtb.perms_faults                       751                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24806358                       # DTB read accesses
+system.cpu.dtb.write_accesses                19450106                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          43943950                       # DTB hits
-system.cpu.dtb.misses                           64472                       # DTB misses
-system.cpu.dtb.accesses                      44008422                       # DTB accesses
+system.cpu.dtb.hits                          44189315                       # DTB hits
+system.cpu.dtb.misses                           67149                       # DTB misses
+system.cpu.dtb.accesses                      44256464                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -397,8 +413,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     57039019                       # ITB inst hits
-system.cpu.itb.inst_misses                       5418                       # ITB inst misses
+system.cpu.itb.inst_hits                     57672689                       # ITB inst hits
+system.cpu.itb.inst_misses                       5411                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -407,119 +423,119 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2981                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2970                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8633                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8383                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57044437                       # ITB inst accesses
-system.cpu.itb.hits                          57039019                       # DTB hits
-system.cpu.itb.misses                            5418                       # DTB misses
-system.cpu.itb.accesses                      57044437                       # DTB accesses
-system.cpu.numCycles                        313379229                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57678100                       # ITB inst accesses
+system.cpu.itb.hits                          57672689                       # DTB hits
+system.cpu.itb.misses                            5411                       # DTB misses
+system.cpu.itb.accesses                      57678100                       # DTB accesses
+system.cpu.numCycles                        314966932                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   111368950                       # Number of instructions committed
-system.cpu.committedOps                     134647110                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7900477                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5391141904                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.813883                       # CPI: cycles per instruction
-system.cpu.ipc                               0.355381                       # IPC: instructions per cycle
+system.cpu.committedInsts                   112002684                       # Number of instructions committed
+system.cpu.committedOps                     135423332                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7762811                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3036                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5390780993                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.812137                       # CPI: cycles per instruction
+system.cpu.ipc                               0.355601                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
-system.cpu.tickCycles                       224160135                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        89219094                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            841413                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.953450                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42452187                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            841925                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.422766                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         279721250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953450                       # Average occupied blocks per requestor
+system.cpu.kern.inst.quiesce                     3036                       # number of quiesce instructions executed
+system.cpu.tickCycles                       228185661                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        86781271                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            843230                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.953176                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42691062                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            843742                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.597294                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         281436250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953176                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          357                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         175172385                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        175172385                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     23318882                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23318882                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     18212211                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18212211                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457846                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457846                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       460333                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460333                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      41531093                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41531093                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     41531093                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41531093                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       583694                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        583694                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       541327                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       541327                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8314                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8314                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176134397                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176134397                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     23488260                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23488260                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     18281937                       # number of WriteReq hits
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+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457712                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457712                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       460238                       # number of StoreCondReq hits
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+system.cpu.dcache.demand_hits::cpu.inst      41770197                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41770197                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     41770197                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41770197                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       584617                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        584617                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       541532                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       541532                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8359                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8359                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1125021                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1125021                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1125021                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1125021                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8654598086                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8654598086                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21588798306                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21588798306                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    117927750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    117927750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst        52502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        52502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  30243396392                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30243396392                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  30243396392                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  30243396392                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     23902576                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23902576                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     18753538                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18753538                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466160                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466160                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       460335                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460335                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     42656114                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42656114                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     42656114                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42656114                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024420                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.024420                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028865                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.028865                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017835                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017835                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.inst      1126149                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1126149                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1126149                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1126149                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8658802092                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8658802092                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21460434801                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21460434801                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    117977250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    117977250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       152000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       152000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  30119236893                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30119236893                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  30119236893                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30119236893                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     24072877                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24072877                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     18823469                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18823469                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466071                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466071                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       460240                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::cpu.inst     42896346                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42896346                       # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total     42896346                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024285                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.024285                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028769                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.028769                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017935                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017935                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.026374                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026374                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.026374                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026374                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14827.286362                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14827.286362                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39881.251639                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39881.251639                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14184.237431                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.237431                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        26251                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26251                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26882.517208                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26882.517208                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26882.517208                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26882.517208                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.026253                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026253                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.026253                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026253                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14811.067916                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14811.067916                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39629.116656                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39629.116656                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14113.799498                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14113.799498                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        76000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        76000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26745.339110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26745.339110                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -528,70 +544,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       697938                       # number of writebacks
-system.cpu.dcache.writebacks::total            697938                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45858                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        45858                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242707                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       242707                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       288565                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       288565                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       288565                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       288565                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       537836                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       537836                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298620                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298620                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8314                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8314                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       699279                       # number of writebacks
+system.cpu.dcache.writebacks::total            699279                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45143                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        45143                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242778                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       242778                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       287921                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       287921                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       287921                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       287921                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       539474                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       539474                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298754                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298754                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8359                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8359                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       836456                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       836456                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       836456                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       836456                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6884995145                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6884995145                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11268709155                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11268709155                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    101270250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    101270250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst        48498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        48498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18153704300                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18153704300                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18153704300                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18153704300                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790985000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790985000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439182000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439182000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230167000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230167000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022501                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022501                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015923                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015923                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017835                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017835                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       838228                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       838228                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       838228                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       838228                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6896325139                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6896325139                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11211804160                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11211804160                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    101230750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    101230750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       148000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       148000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18108129299                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18108129299                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18108129299                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18108129299                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790997000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790997000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439577500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439577500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230574500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230574500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022410                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022410                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015871                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015871                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017935                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017935                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019609                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.019609                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019609                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019609                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.290998                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12801.290998                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37735.949216                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37735.949216                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12180.689199                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12180.689199                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        24249                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24249                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21703.119232                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21703.119232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21703.119232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21703.119232                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.019541                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019541                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        74000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        74000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -599,58 +615,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2897611                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.427780                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54131846                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2898123                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.678243                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       15213015250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.427780                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998882                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998882                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           2898546                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.424366                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54764882                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2899058                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.890578                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       15302672250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.424366                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998876                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998876                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          59928115                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         59928115                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54131846                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54131846                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54131846                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54131846                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54131846                       # number of overall hits
-system.cpu.icache.overall_hits::total        54131846                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2898135                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2898135                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2898135                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2898135                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2898135                       # number of overall misses
-system.cpu.icache.overall_misses::total       2898135                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  39145708027                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  39145708027                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  39145708027                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  39145708027                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  39145708027                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  39145708027                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57029981                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57029981                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57029981                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57029981                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57029981                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57029981                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050818                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050818                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050818                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050818                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050818                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050818                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.206540                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13507.206540                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.206540                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13507.206540                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.206540                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13507.206540                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60563021                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60563021                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54764882                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54764882                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54764882                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54764882                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54764882                       # number of overall hits
+system.cpu.icache.overall_hits::total        54764882                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2899070                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2899070                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2899070                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2899070                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2899070                       # number of overall misses
+system.cpu.icache.overall_misses::total       2899070                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39144211468                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39144211468                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39144211468                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39144211468                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39144211468                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39144211468                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57663952                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57663952                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57663952                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57663952                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57663952                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57663952                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050275                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050275                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050275                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050275                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050275                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050275                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13502.334013                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13502.334013                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13502.334013                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13502.334013                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -659,176 +675,176 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2898135                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2898135                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2898135                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2898135                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2898135                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2898135                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33339952973                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  33339952973                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33339952973                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  33339952973                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33339952973                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  33339952973                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    222062750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    222062750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    222062750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    222062750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050818                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050818                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050818                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050818                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050818                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050818                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.933727                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.933727                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.933727                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.933727                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.933727                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.933727                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2899070                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      2899070                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      2899070                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      2899070                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      2899070                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      2899070                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33336586532                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  33336586532                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33336586532                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  33336586532                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33336586532                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  33336586532                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    222066250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    222066250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    222066250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    222066250                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050275                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.050275                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.050275                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11499.062297                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            97521                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65074.207270                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4042767                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162784                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            24.835162                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      93462601500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47538.276045                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    53.278527                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000399                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 17482.652299                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.725377                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000813                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            96693                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65074.721793                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4049393                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           161936                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            25.006132                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 47626.273785                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.769943                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000365                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 17377.677699                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.726719                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.266764                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992954                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65223                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2327                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6958                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55810                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995224                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         36581031                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        36581031                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69052                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4779                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      3406716                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        3480547                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       697938                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       697938                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst           45                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       164104                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       164104                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        69052                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         4779                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      3570820                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         3644651                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        69052                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         4779                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      3570820                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        3644651                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           97                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        37533                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        37632                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2776                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2776                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.265162                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992961                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           43                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2281                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6890                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55911                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000656                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         36630547                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        36630547                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        71506                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4492                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        3485623                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       699279                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       699279                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.inst           49                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       164818                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       164818                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        71506                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::cpu.inst      3574443                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         3650441                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        71506                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.inst      3574443                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        3650441                       # number of overall hits
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+system.cpu.l2cache.UpgradeReq_misses::total         2769                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       131700                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       131700                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           97                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::cpu.inst       169233                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        169332                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           97                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       169233                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       169332                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      7518750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2779279750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2786947500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst      1021956                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      1021956                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst        46498                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        46498                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9264906431                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      7518750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  12044186181                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12051853931                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      7518750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  12044186181                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12051853931                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        69149                       # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::cpu.inst      3444249                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      3518179                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       697938                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       697938                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2821                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2821                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       146000                       # number of SCUpgradeReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        74500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst  11956741678                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11966332678                       # number of overall miss cycles
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+system.cpu.l2cache.Writeback_accesses::total       699279                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::total      3813983                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001403                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000418                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010897                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.010696                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.984048                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984048                       # miss rate for UpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.445227                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.445227                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001403                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000418                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.045249                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044398                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001403                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000418                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.045249                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.044398                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77512.886598                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.443071                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.443071                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000223                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.044982                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.044118                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.044982                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.044118                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74048.963579                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74057.916135                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   368.139769                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   368.139769                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        23249                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        23249                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70348.568193                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70348.568193                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77512.886598                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74016.496133                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74027.549518                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   303.345612                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   303.345612                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        73000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        73000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.188861                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.188861                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71169.252929                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71172.926151                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77512.886598                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71023.976769                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71169.252929                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71172.926151                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71023.976769                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -837,92 +853,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88794                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88794                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          168                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst          168                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst          168                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          168                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           97                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37365                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        37464                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2776                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2776                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        88299                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88299                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          156                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total          156                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst          156                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          156                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2769                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2769                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131700                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       131700                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           97                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::total       169164                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           97                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       169065                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       169164                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      6323250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2300603500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2307051750                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27795276                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7582295069                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7582295069                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      6323250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9882898569                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9889346819                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      6323250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9882898569                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9889346819                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545290750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545290750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4106643000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4106643000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9651933750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9651933750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001403                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000418                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010849                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010649                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.984048                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984048                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131123                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131123                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          123                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.inst       168203                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2281616000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2289681000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27874769                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27874769                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       122000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       122000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7547217572                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9828833572                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9836898572                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9828833572                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545306500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545306500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4107046000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107046000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652352500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652352500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010758                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010560                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.982612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982612                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.445227                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.445227                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001403                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000418                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.045204                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044354                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001403                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000418                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.045204                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044354                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.443071                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443071                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044077                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044077                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61571.082564                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61580.497277                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.707493                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.707493                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57572.475847                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57572.475847                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        61000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        61000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58456.206601                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.114557                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58456.206601                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.114557                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -930,59 +946,60 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3576313                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3576217                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        3581708                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3581608                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27607                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27607                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       697938                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2821                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       699279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2818                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2823                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295804                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5802238                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2505111                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15298                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       156293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8478940                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185670592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98744797                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        19124                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       276596                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          284711109                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       60360                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4574965                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.007969                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.088914                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2820                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5804102                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2510082                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14997                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161563                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8490744                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185730048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98946845                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17972                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       286516                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          284981381                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       60946                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4581834                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.007957                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.088847                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            4538506     99.20%     99.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6              36459      0.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            4545376     99.20%     99.20% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6              36458      0.80%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4574965                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3011909666                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4581834                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3016682672                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       208500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       202500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4357140777                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4358543218                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1340495452                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1342977701                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10517000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10504000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      87146500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      89938750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1073,42 +1090,44 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326584349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347024164                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36804753                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36804504                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.031563                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.033420                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         269946820000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.031563                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064473                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064473                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270180945000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.033420                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064589                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064589                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     27956377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     27956377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     27956377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     27956377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     27956377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     27956377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     27950377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     27950377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9603131283                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9603131283                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     27950377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     27950377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     27950377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     27950377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1119,104 +1138,114 @@ system.iocache.overall_accesses::realview.ide          234
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119471.696581                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119471.696581                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119471.696581                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119471.696581                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119471.696581                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119446.055556                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119446.055556                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119446.055556                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56022                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7210                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.770042                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     15787377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     15787377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2211427725                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2211427725                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     15787377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     15787377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     15787377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     15787377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     15781377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     15781377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     15781377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     15781377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     15781377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     15781377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67467.423077                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67467.423077                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               71836                       # Transaction distribution
-system.membus.trans_dist::ReadResp              71836                       # Transaction distribution
+system.membus.trans_dist::ReadReq               71576                       # Transaction distribution
+system.membus.trans_dist::ReadResp              71576                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27607                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27607                       # Transaction distribution
-system.membus.trans_dist::Writeback             88794                       # Transaction distribution
+system.membus.trans_dist::Writeback            124489                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4595                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4592                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4597                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129881                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129881                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4594                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129300                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129300                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       448536                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       556168                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 628865                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446065                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 662584                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16604248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16768029                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19087325                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              219                       # Total snoops (count)
-system.membus.snoop_fanout::samples            297195                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16500440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16664221                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21299677                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              507                       # Total snoops (count)
+system.membus.snoop_fanout::samples            332045                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  297195    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  332045    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              297195                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87032500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              332045                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87455500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1706500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1699000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1386266250                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1718628403                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1675329000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1688631909                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38334247                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38334496                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 7a2aefe62..d32247ca8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,125 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.826844                       # Number of seconds simulated
-sim_ticks                                2826844351500                       # Number of ticks simulated
-final_tick                               2826844351500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827042                       # Number of seconds simulated
+sim_ticks                                2827042159500                       # Number of ticks simulated
+final_tick                               2827042159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74392                       # Simulator instruction rate (inst/s)
-host_op_rate                                    90233                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1857645684                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 566256                       # Number of bytes of host memory used
-host_seconds                                  1521.74                       # Real time elapsed on the host
-sim_insts                                   113204796                       # Number of instructions simulated
-sim_ops                                     137311416                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  73670                       # Simulator instruction rate (inst/s)
+host_op_rate                                    89358                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1840258315                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 564112                       # Number of bytes of host memory used
+host_seconds                                  1536.22                       # Real time elapsed on the host
+sim_insts                                   113173742                       # Number of instructions simulated
+sim_ops                                     137273263                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst           1324048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9514916                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9496932                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10841588                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10823604                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1324048                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5800064                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      8116352                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8135924                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8133876                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              22933                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             149190                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             148909                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                172164                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           90626                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                171883                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126818                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               131231                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               131199                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            430                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468384                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3365914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               468351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3359317                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3835226                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2051780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3828597                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          468351                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             468351                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2870970                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          820114                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2878094                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2051780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2877168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2870970                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           430                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3372113                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          820454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6713320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        172165                       # Number of read requests accepted
-system.physmem.writeReqs                       131231                       # Number of write requests accepted
-system.physmem.readBursts                      172165                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     131231                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11009408                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8149760                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10841652                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8135924                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4545                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10989                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10130                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11201                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11419                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13122                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10546                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11171                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11539                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10356                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11056                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10496                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9259                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10183                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10761                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10049                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9745                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8312                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7765                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8704                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8604                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7611                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7949                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8258                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8579                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7843                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8531                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7842                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6872                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7611                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8198                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7118                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              468351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3365516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6705765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        171884                       # Number of read requests accepted
+system.physmem.writeReqs                       167423                       # Number of write requests accepted
+system.physmem.readBursts                      171884                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     167423                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10992576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10315392                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10823668                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10452212                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6228                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4543                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10965                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10116                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11197                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11389                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13120                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10535                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11120                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11540                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10348                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11053                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10478                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9244                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10124                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10758                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10029                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9743                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10407                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9909                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10642                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10446                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9703                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10218                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10399                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10626                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10202                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10761                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9802                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9030                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9755                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10443                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9720                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9115                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2826844140500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827041948500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2993                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  168617                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  168336                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 126850                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16016                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 163042                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151765                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     15965                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -162,156 +159,174 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10773                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9486                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7681                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::33                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      347                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::39                      250                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.286868                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.931959                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.707872                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23391     37.64%     37.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14782     23.79%     61.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6350     10.22%     71.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3679      5.92%     77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2602      4.19%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1532      2.47%     84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1126      1.81%     86.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1130      1.82%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7555     12.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62147                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6420                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.793614                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      556.638433                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6418     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6420                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6420                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.834891                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.369444                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.492928                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5612     87.41%     87.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              54      0.84%     88.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.47%     88.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             211      3.29%     92.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             221      3.44%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              14      0.22%     95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.20%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              15      0.23%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              17      0.26%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.06%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.05%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.08%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             167      2.60%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.11%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.06%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              10      0.16%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               5      0.08%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.05%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6420                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2072280000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5297692500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    860110000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12046.60                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64399                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.873212                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     190.977516                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.816153                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23539     36.55%     36.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14785     22.96%     59.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6319      9.81%     69.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3687      5.73%     75.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2636      4.09%     79.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1562      2.43%     81.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1140      1.77%     83.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1107      1.72%     85.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9624     14.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64399                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6814                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.206340                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      540.339482                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6812     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6814                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6814                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.653948                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.805353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.459775                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5702     83.68%     83.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              39      0.57%     84.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              26      0.38%     84.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             231      3.39%     88.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             131      1.92%     89.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              61      0.90%     90.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              35      0.51%     91.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              27      0.40%     91.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             123      1.81%     93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              13      0.19%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              19      0.28%     94.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.16%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              31      0.45%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              13      0.19%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              13      0.19%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.38%     95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              61      0.90%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              10      0.15%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               9      0.13%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              11      0.16%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              89      1.31%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             7      0.10%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            18      0.26%     98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.06%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             5      0.07%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             4      0.06%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            26      0.38%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             4      0.06%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.06%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             5      0.07%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            11      0.16%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            11      0.16%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.04%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             3      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             3      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6814                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2084525750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5305007000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    858795000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12136.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30796.60                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30886.34                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.88                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.88                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.07                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     142002                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95212                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9317341.50                       # Average gap between requests
-system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2694665773000                       # Time in different power states
-system.physmem.memoryStateTime::REF       94394300000                       # Time in different power states
+system.physmem.avgWrQLen                        25.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     141721                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    126816                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8331811.45                       # Average gap between requests
+system.physmem.pageHitRate                      80.65                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2694668588500                       # Time in different power states
+system.physmem.memoryStateTime::REF       94401060000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37784264500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       37972497000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 245987280                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 223844040                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 134219250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 122137125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                702912600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                638851200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               426267360                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               398895840                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184635250800                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184635250800                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           80264555415                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           79079779350                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625694839250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1626734116500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1892104031955                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1891832874855                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.336036                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.240113                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 254499840                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 232356600                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 138864000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 126781875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                701859600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                637852800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               533628000                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               510805440                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          184648473360                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          184648473360                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           80377758270                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           79142156730                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1625717004000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1626800865000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1892372087070                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1892099291805                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.382923                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.286428                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
@@ -330,15 +345,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46964274                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24050124                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1232745                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29560624                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21375180                       # Number of BTB hits
+system.cpu.branchPred.lookups                46933448                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24039449                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232882                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29542848                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21360620                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.309637                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11765118                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33710                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.303862                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11754095                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33720                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -363,25 +378,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24601402                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8241                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19645330                       # DTB write hits
+system.cpu.checker.dtb.read_hits             24594187                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8246                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19641862                       # DTB write hits
 system.cpu.checker.dtb.write_misses              1441                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             4295                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             4296                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1773                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1766                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24609643                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19646771                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24602433                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19643303                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44246732                       # DTB hits
-system.cpu.checker.dtb.misses                    9682                       # DTB misses
-system.cpu.checker.dtb.accesses              44256414                       # DTB accesses
+system.cpu.checker.dtb.hits                  44236049                       # DTB hits
+system.cpu.checker.dtb.misses                    9687                       # DTB misses
+system.cpu.checker.dtb.accesses              44245736                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -403,7 +418,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits            115909165                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115876249                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4826                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -420,11 +435,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115913991                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115909165                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115881075                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115876249                       # DTB hits
 system.cpu.checker.itb.misses                    4826                       # DTB misses
-system.cpu.checker.itb.accesses             115913991                       # DTB accesses
-system.cpu.checker.numCycles                139167829                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115881075                       # DTB accesses
+system.cpu.checker.numCycles                139127814                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -450,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25471879                       # DTB read hits
-system.cpu.dtb.read_misses                      60408                       # DTB read misses
-system.cpu.dtb.write_hits                    19919747                       # DTB write hits
-system.cpu.dtb.write_misses                      9388                       # DTB write misses
+system.cpu.dtb.read_hits                     25465003                       # DTB read hits
+system.cpu.dtb.read_misses                      60438                       # DTB read misses
+system.cpu.dtb.write_hits                    19916425                       # DTB write hits
+system.cpu.dtb.write_misses                      9382                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4324                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       351                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2316                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       344                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2309                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1300                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25532287                       # DTB read accesses
-system.cpu.dtb.write_accesses                19929135                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25525441                       # DTB read accesses
+system.cpu.dtb.write_accesses                19925807                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45391626                       # DTB hits
-system.cpu.dtb.misses                           69796                       # DTB misses
-system.cpu.dtb.accesses                      45461422                       # DTB accesses
+system.cpu.dtb.hits                          45381428                       # DTB hits
+system.cpu.dtb.misses                           69820                       # DTB misses
+system.cpu.dtb.accesses                      45451248                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -490,8 +505,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     66240582                       # ITB inst hits
-system.cpu.itb.inst_misses                      11936                       # ITB inst misses
+system.cpu.itb.inst_hits                     66294026                       # ITB inst hits
+system.cpu.itb.inst_misses                      11939                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -500,98 +515,98 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3096                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2163                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2177                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66252518                       # ITB inst accesses
-system.cpu.itb.hits                          66240582                       # DTB hits
-system.cpu.itb.misses                           11936                       # DTB misses
-system.cpu.itb.accesses                      66252518                       # DTB accesses
-system.cpu.numCycles                        260548868                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66305965                       # ITB inst accesses
+system.cpu.itb.hits                          66294026                       # DTB hits
+system.cpu.itb.misses                           11939                       # DTB misses
+system.cpu.itb.accesses                      66305965                       # DTB accesses
+system.cpu.numCycles                        260580731                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104909639                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184558460                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46964274                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33140298                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     145575332                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6162234                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     168611                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8187                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        338898                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       503455                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          112                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66240894                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1039458                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4991                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          254585351                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.884453                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.237226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104873538                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184739295                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46933448                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33114715                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     145635789                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6158762                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     168952                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8750                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        338958                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       503648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66294321                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1128854                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4994                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          254609122                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.884999                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.237560                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                155338707     61.02%     61.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29243843     11.49%     72.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14083345      5.53%     78.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55919456     21.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                155317216     61.00%     61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29235163     11.48%     72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14076452      5.53%     78.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55980291     21.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            254585351                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.180251                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.708345                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78108823                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             105363724                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64680632                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3828797                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2603375                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422156                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                485996                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157495015                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3691306                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2603375                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83949795                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10013130                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74489960                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62673363                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              20855728                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146845952                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                950144                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                437842                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  62734                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16405                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               18093439                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150530803                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678954009                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164472740                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10951                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141875467                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8655333                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2847772                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2651529                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13851116                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26418132                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21304063                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1686589                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2099460                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143580575                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2120859                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143376028                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            269119                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6250781                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14651223                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125281                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     254585351                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.563175                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.882138                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            254609122                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.180111                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.708952                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78085586                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             105431733                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64660886                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3829260                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2601657                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422216                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485978                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157447803                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3691485                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2601657                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83925210                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10033565                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74541150                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62655394                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              20852146                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146807646                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                950357                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                437123                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62766                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16447                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               18089237                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150492315                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678770164                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164434086                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10967                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141835122                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8657190                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2845976                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2649716                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13845319                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26411369                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21300781                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1686386                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2189128                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143541895                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2120957                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143337283                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            269192                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6251828                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14653372                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125306                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     254609122                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.562970                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.882443                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           166207835     65.29%     65.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45306594     17.80%     83.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31956972     12.55%     95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10300343      4.05%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              813574      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           166344309     65.33%     65.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45117660     17.72%     83.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32035421     12.58%     95.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10298180      4.04%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813519      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -599,9 +614,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       254585351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       254609122                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7371879     32.63%     32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7370311     32.63%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.63% # attempts to use FU when none available
@@ -630,13 +645,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5632028     24.93%     57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9586948     42.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5632420     24.93%     57.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9586874     42.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96038086     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113978      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              96009315     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113982      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -660,100 +675,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8590      0.01%     67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8594      0.01%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26200986     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21012051     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26194290     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21008765     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143376028                       # Type of FU issued
-system.cpu.iq.rate                           0.550285                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22590887                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157564                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          564161758                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         151957264                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140260479                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35655                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13185                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              143337283                       # Type of FU issued
+system.cpu.iq.rate                           0.550069                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22589637                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157598                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          564106761                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         151919680                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140223084                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35756                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13217                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11431                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165941227                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23351                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           324401                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165901147                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23436                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           324147                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1489874                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1490308                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          533                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18271                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       701002                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18251                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       701176                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87957                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6348                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88081                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6304                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2603375                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  948323                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                290944                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145902361                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2601657                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  950737                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                291154                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145863821                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26418132                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21304063                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096021                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17856                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                256072                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18271                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317509                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471618                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789127                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142433599                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25799978                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            872737                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26411369                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21300781                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096076                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17895                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                256263                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18251                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317548                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471732                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789280                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142394540                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25793108                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            873030                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200927                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46682549                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26544085                       # Number of branches executed
-system.cpu.iew.exec_stores                   20882571                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.546668                       # Inst execution rate
-system.cpu.iew.wb_sent                      142046516                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140271910                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63301578                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95887209                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200969                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46672402                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26533167                       # Number of branches executed
+system.cpu.iew.exec_stores                   20879294                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.546451                       # Inst execution rate
+system.cpu.iew.wb_sent                      142007306                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140234515                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63283849                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95860591                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.538371                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660167                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.538161                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660165                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7591975                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995578                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755003                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    251649065                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.546262                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.145555                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7591533                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995651                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755158                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    251674404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.546055                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.146686                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    178084267     70.77%     70.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43398054     17.25%     88.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15481884      6.15%     94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4357721      1.73%     95.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6462022      2.57%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1589357      0.63%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       777637      0.31%     99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       414343      0.16%     99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1083780      0.43%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    178222235     70.81%     70.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43294364     17.20%     88.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15476639      6.15%     94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4357303      1.73%     95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6369018      2.53%     98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1679088      0.67%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       777340      0.31%     99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       414271      0.16%     99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1084146      0.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    251649065                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113359701                       # Number of instructions committed
-system.cpu.commit.committedOps              137466321                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    251674404                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113328647                       # Number of instructions committed
+system.cpu.commit.committedOps              137428168                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45531319                       # Number of memory references committed
-system.cpu.commit.loads                      24928258                       # Number of loads committed
-system.cpu.commit.membars                      814674                       # Number of memory barriers committed
-system.cpu.commit.branches                   26060472                       # Number of branches committed
+system.cpu.commit.refs                       45520666                       # Number of memory references committed
+system.cpu.commit.loads                      24921061                       # Number of loads committed
+system.cpu.commit.membars                      814701                       # Number of memory barriers committed
+system.cpu.commit.branches                   26049415                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120282111                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4896381                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120247607                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4892692                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91813423     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91785919     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112990      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -778,43 +793,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8589      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8593      0.01%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24928258     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20603061     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24921061     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20599605     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137466321                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1083780                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         137428168                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1084146                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    373370450                       # The number of ROB reads
-system.cpu.rob.rob_writes                   293050441                       # The number of ROB writes
-system.cpu.timesIdled                          892831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5963517                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5393139836                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113204796                       # Number of Instructions Simulated
-system.cpu.committedOps                     137311416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.301571                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.301571                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.434486                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.434486                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155870535                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88662744                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9591                       # number of floating regfile reads
+system.cpu.rob.rob_reads                    373381031                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292971684                       # The number of ROB writes
+system.cpu.timesIdled                          892930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5971609                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5393503589                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113173742                       # Number of Instructions Simulated
+system.cpu.committedOps                     137273263                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.302484                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.302484                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.434314                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.434314                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155831391                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88636025                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9607                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 503158962                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53196475                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               444136009                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521560                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837744                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.958486                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40170152                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838256                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.921103                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 503020698                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53185327                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               444130548                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521619                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837995                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.958491                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40159583                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838507                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.894154                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         244924250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.958486                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.958491                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -822,170 +837,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          125
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179419983                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179419983                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23329792                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23329792                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15588565                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15588565                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346643                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346643                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441991                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441991                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460300                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460300                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38918357                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38918357                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39265000                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39265000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       700458                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        700458                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3573865                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3573865                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177072                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177072                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26735                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26735                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179379502                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179379502                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23322864                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23322864                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15584894                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15584894                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       346636                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        346636                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       442009                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       442009                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460310                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460310                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38907758                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38907758                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39254394                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39254394                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       700618                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        700618                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3574058                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3574058                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177109                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177109                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26740                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26740                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4274323                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4274323                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4451395                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4451395                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9897569146                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9897569146                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 135184782788                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    357043749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    357043749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        91502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        91502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145082351934                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145082351934                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145082351934                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145082351934                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24030250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24030250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19162430                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19162430                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523715                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523715                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468726                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468726                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460305                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460305                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43192680                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43192680                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43716395                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43716395                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029149                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029149                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186504                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.186504                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338108                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.338108                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057038                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057038                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      4274676                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4274676                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4451785                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4451785                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9939142148                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9939142148                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 135148977049                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    356483749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    356483749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       189500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       189500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145088119197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145088119197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145088119197                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145088119197                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24023482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24023482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19158952                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19158952                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523745                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523745                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468749                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468749                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460315                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460315                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43182434                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43182434                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43706179                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43706179                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029164                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029164                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186548                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.186548                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338159                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.338159                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057045                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057045                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.098959                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.098959                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.101824                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.101824                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33942.767529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32592.558498                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       504099                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.098991                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.098991                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.101857                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.101857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        37900                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        37900                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33941.313727                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32590.998711                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       505021                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6928                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6926                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.762558                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.916691                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695413                       # number of writebacks
-system.cpu.dcache.writebacks::total            695413                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286304                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       286304                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274603                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3274603                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18411                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18411                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3560907                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3560907                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3560907                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3560907                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414154                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414154                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299262                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299262                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119306                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119306                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8324                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8324                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       695574                       # number of writebacks
+system.cpu.dcache.writebacks::total            695574                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286297                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       286297                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274736                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3274736                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18417                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18417                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3561033                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3561033                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3561033                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3561033                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414321                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414321                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299322                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299322                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119334                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119334                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8323                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8323                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832722                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832722                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5341815166                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5341815166                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11883724205                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11883724205                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1479869001                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1479869001                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110184750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110184750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17225539371                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17225539371                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18705408372                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18705408372                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792724250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792724250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440459453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440459453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233183703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233183703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017235                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017235                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227807                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227807                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017759                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017759                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       713643                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       713643                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832977                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832977                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5358688665                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5358688665                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11888843709                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11888843709                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1476460251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1476460251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110246000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110246000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       179500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       179500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17247532374                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17247532374                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18723992625                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18723992625                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792718250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792718250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440457453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440457453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233175703                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233175703                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017247                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017247                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017756                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017756                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019048                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019048                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019059                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019059                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        35900                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        35900                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -993,13 +1008,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1894031                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.373814                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64256441                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1894543                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.916591                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1894210                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.373832                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64309690                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1894722                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.941491                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       13186180250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.373814                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.373832                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1008,250 +1023,250 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          170
 system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68132454                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68132454                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64256441                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64256441                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64256441                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64256441                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64256441                       # number of overall hits
-system.cpu.icache.overall_hits::total        64256441                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981452                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981452                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981452                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981452                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981452                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981452                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26762198879                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26762198879                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26762198879                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26762198879                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26762198879                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26762198879                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66237893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66237893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66237893                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66237893                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66237893                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66237893                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029914                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029914                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029914                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029914                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029914                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029914                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13506.357398                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13506.357398                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1929                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68186062                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68186062                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64309690                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64309690                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64309690                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64309690                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64309690                       # number of overall hits
+system.cpu.icache.overall_hits::total        64309690                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1981630                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1981630                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1981630                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1981630                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1981630                       # number of overall misses
+system.cpu.icache.overall_misses::total       1981630                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26770075875                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26770075875                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26770075875                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26770075875                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  26770075875                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26770075875                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66291320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66291320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66291320                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66291320                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66291320                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66291320                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029893                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029893                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029893                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029893                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029893                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029893                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13509.119197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13509.119197                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1592                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               105                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               104                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    18.371429                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    15.307692                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86889                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        86889                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        86889                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        86889                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        86889                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        86889                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894563                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1894563                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1894563                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1894563                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1894563                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1894563                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22159944091                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  22159944091                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22159944091                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  22159944091                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22159944091                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  22159944091                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86886                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        86886                       # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_hits::total        86886                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894744                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::total      1894744                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22166113097                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  22166113097                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22166113097                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  22166113097                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total  22166113097                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    202549500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    202549500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028602                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028602                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028602                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028582                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028582                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028582                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.737717                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            98619                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65077.788294                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3020947                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           163832                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.439298                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            98615                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65077.693225                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3021592                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           163828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            18.443685                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218344                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798460                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5191.617940                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756264                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218373                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798544                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5192.626837                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.756260                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000156                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157327                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.079218                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.993008                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_percent::total     0.993007                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2968                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7006                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2969                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7003                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55048                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         28437271                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        28437271                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53838                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11660                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1874564                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       528034                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2468096                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       695413                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       695413                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           34                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           34                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.tag_accesses         28442992                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        28442992                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53902                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        2468583                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       695574                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       695574                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           36                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           36                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       159688                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       159688                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        53838                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        11660                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1874564                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.dtb.walker        53838                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        11660                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1874564                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       687722                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2627784                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.inst      1874744                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       687980                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2628333                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           19                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        19966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        13620                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        33612                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2733                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2733                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        19968                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        13616                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        33610                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2734                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2734                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
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 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75113.593108                       # average overall miss latency
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 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75113.593108                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73076.528757                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73315.561452                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75315.204327                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 73433.597435                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1260,8 +1275,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        90626                       # number of writebacks
-system.cpu.l2cache.writebacks::total            90626                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        90628                       # number of writebacks
+system.cpu.l2cache.writebacks::total            90628                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
@@ -1273,96 +1288,96 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data          112
 system.cpu.l2cache.overall_mshr_hits::total          137                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19941                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2733                       # number of UpgradeReq MSHR misses
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+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2734                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2734                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           19                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           19                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1223500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19943                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       150438                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       170407                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       451250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1247817250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    902981250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2152473250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27396733                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27396733                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8210001310                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8210001310                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1223500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1251787750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    914145000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2167621250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27559234                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27559234                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8214311559                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8214311559                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       451250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1247817250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9112982560                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10362474560                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1223500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1251787750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9128456559                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10381932809                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       451250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1247817250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9112982560                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10362474560                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1251787750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9128456559                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10381932809                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387482250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545359250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107341000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107341000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387474750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545351750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107339500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107339500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157877000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494823250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652700250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494814250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652691250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024938                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013381                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987712                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987712                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024922                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013377                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987004                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987004                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461650                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461650                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461548                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461548                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179469                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060898                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060884                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179469                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060898                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060884                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1372,31 +1387,31 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2564949                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2564884                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2565344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2565278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27608                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27608                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       695413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36229                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2767                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       695574                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2770                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2772                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296625                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495164                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31180                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128717                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6450154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121297808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98349473                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215428                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219909377                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       65488                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3561849                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        9.010233                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.100640                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296684                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296684                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795456                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495832                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31236                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128794                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6451318                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121309456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98375777                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215684                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219947773                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       65392                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3562462                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        9.010230                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.100625                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
@@ -1407,28 +1422,29 @@ system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Re
 system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9            3525400     98.98%     98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::10             36449      1.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9            3526018     98.98%     98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10             36444      1.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3561849                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2502926529                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3562462                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2503396529                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2849434655                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2849706150                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1334430859                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1334755109                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19518240                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19527240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74882707                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74897454                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1519,42 +1535,44 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326556349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347066130                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36779263                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36776516                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                0.999676                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000725                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         251942463000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.999676                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062480                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062480                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         251942535000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000725                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062545                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062545                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
 system.iocache.tags.data_accesses              327996                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          220                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               220                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          220                       # number of overall misses
 system.iocache.overall_misses::total              220                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     26406377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     26406377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     26406377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     26406377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     26406377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     26406377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     26411377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     26411377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9622478237                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9622478237                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     26411377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     26411377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     26411377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     26411377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1565,104 +1583,114 @@ system.iocache.overall_accesses::realview.ide          220
 system.iocache.overall_accesses::total            220                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120028.986364                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120028.986364                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120028.986364                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120028.986364                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120028.986364                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120051.713636                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120051.713636                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120051.713636                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56749                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7275                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.800550                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          220                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          220                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          220                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          220                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          220                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          220                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     14965377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     14965377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2230292235                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2230292235                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     14965377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     14965377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     14965377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     14965377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     14970377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     14970377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     14970377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     14970377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     14970377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     14970377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68024.440909                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68024.440909                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               67834                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67833                       # Transaction distribution
+system.membus.trans_dist::ReadReq               67832                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67831                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
-system.membus.trans_dist::Writeback             90626                       # Transaction distribution
+system.membus.trans_dist::Writeback            126818                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4543                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4545                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135127                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135127                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135125                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135125                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452777                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560413                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72683                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72683                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 633096                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452492                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 669001                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16658216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16821681                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19140977                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              205                       # Total snoops (count)
-system.membus.snoop_fanout::samples            300222                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16640360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16803825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21439281                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              484                       # Total snoops (count)
+system.membus.snoop_fanout::samples            336405                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  300222    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  336405    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              300222                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            94200000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              336405                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            94190000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1697000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1357984749                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1678025205                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1683660499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1677935457                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38219737                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38220484                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1696,6 +1724,6 @@ system.realview.ethernet.coalescedTotal           nan                       # av
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3038                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                     3039                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index b13980f34..8bea05f5e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,169 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.824366                       # Number of seconds simulated
-sim_ticks                                2824365837500                       # Number of ticks simulated
-final_tick                               2824365837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.824570                       # Number of seconds simulated
+sim_ticks                                2824570221000                       # Number of ticks simulated
+final_tick                               2824570221000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93434                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113356                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2196532158                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669668                       # Number of bytes of host memory used
-host_seconds                                  1285.83                       # Real time elapsed on the host
-sim_insts                                   120140086                       # Number of instructions simulated
-sim_ops                                     145755972                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  42227                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51230                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              992732164                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 776620                       # Number of bytes of host memory used
+host_seconds                                  2845.25                       # Real time elapsed on the host
+sim_insts                                   120145307                       # Number of instructions simulated
+sim_ops                                     145762315                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           286496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1047804                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     10514048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           286752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1037180                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     10498560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            32208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           549728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      1343808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            31952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           549024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      1342912                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13778252                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       286496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        32208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             13750604                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       286752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        31952                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          318704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7259968                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      9574272                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9596048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9592016                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6722                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             16897                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       164282                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6726                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             16731                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       164040                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8613                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        20997                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               566                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8602                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        20983                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                218146                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          113437                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                217714                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149598                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               154097                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               154034                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           113                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              101437                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              370987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3722623                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              101521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              367199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3716870                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               11404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              194638                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       475791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               11312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              194374                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       475439                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4878352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         101437                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          11404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2570477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4868211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         101521                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          11312                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             112833                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3389639                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6268                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          820834                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3397594                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2570477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3395921                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3389639                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             101437                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             377256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3722623                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             101521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             373467                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3716870                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              11404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             194652                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       475791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          821174                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8275946                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        218146                       # Number of read requests accepted
-system.physmem.writeReqs                       154097                       # Number of write requests accepted
-system.physmem.readBursts                      218146                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     154097                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 13946112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     15232                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9610368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  13778252                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9596048                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      238                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3916                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          13753                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               13737                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13637                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14389                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               14286                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15951                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               13008                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13922                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13905                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13614                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13369                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12796                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11719                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              13344                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst              11312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             194389                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       475439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                8264132                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        217714                       # Number of read requests accepted
+system.physmem.writeReqs                       190258                       # Number of write requests accepted
+system.physmem.readBursts                      217714                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     190258                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 13924352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  11782272                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  13750604                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11910352                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6131                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          13778                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               13720                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               13621                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               14360                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               14230                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15917                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12969                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               13917                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13922                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               13602                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               13356                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12792                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11688                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              13275                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              14168                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              13355                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12708                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9678                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9778                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10288                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9945                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9066                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9050                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9464                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9420                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9418                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9295                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9149                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8660                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9452                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9588                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9180                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8731                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              13342                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12689                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               11837                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               11937                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               12245                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               12130                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               11220                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               11075                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11642                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               11554                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               11490                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               11375                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              11404                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              11050                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              11716                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11527                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              11100                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10796                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2824364779500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2824568625000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3083                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  214476                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  214044                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149661                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     53531                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     76693                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     20729                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     15217                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     11073                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      9725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8854                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      8206                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      7203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1095                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      641                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      479                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      216                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 185822                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     53286                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     76786                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     20725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     15275                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     11050                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      9711                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8821                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      8169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      7162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      285                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -191,152 +188,172 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    10773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    11406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4872                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10762                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    12258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    13286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    12907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    12909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    12445                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    12840                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    10190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    10077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     9379                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      267                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      143                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::48                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::56                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        92847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      253.712882                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     143.703009                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     308.429657                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46968     50.59%     50.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18903     20.36%     70.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6762      7.28%     78.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3669      3.95%     82.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3165      3.41%     85.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2101      2.26%     87.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1261      1.36%     89.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1081      1.16%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8937      9.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          92847                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.938645                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      528.498472                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7529     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::57                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        95193                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      270.047419                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     149.647814                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.885603                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47290     49.68%     49.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18811     19.76%     69.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6810      7.15%     76.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3608      3.79%     80.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3189      3.35%     83.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2125      2.23%     85.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1286      1.35%     87.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1091      1.15%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10983     11.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          95193                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7956                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.345777                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      514.192665                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7955     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7530                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7530                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.941833                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.646034                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       10.689402                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6119     81.26%     81.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             568      7.54%     88.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              91      1.21%     90.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             218      2.90%     92.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             217      2.88%     95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              12      0.16%     95.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              20      0.27%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.33%     96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              26      0.35%     96.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.11%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.08%     97.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.07%     97.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             157      2.08%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.09%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.11%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.05%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.17%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               6      0.08%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.09%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7530                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8946488000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13032263000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1089540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       41056.26                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7956                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7956                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.139517                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.869319                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.452539                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6216     78.13%     78.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             561      7.05%     85.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              92      1.16%     86.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             246      3.09%     89.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             152      1.91%     91.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              55      0.69%     92.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              34      0.43%     92.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.47%     92.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             126      1.58%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              18      0.23%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              19      0.24%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.11%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              35      0.44%     95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              15      0.19%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.11%     95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              35      0.44%     96.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              47      0.59%     96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              11      0.14%     97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               5      0.06%     97.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               9      0.11%     97.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              88      1.11%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             8      0.10%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            17      0.21%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             6      0.08%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             8      0.10%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            29      0.36%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            10      0.13%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.05%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.09%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             7      0.09%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             5      0.06%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             6      0.08%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.01%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.06%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7956                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8935367250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13014767250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1087840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       41069.31                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  59806.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.94                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.40                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.88                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.40                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  59819.31                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.93                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.22                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.08                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     185273                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89950                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.89                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7587422.14                       # Average gap between requests
-system.physmem.pageHitRate                      74.77                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2697372741500                       # Time in different power states
-system.physmem.memoryStateTime::REF       94311620000                       # Time in different power states
+system.physmem.avgRdQLen                         2.29                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.31                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     184937                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    121536                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.00                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                      6923437.45                       # Average gap between requests
+system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2697464747500                       # Time in different power states
+system.physmem.memoryStateTime::REF       94318380000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       32676864750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       32780541250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 364906080                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 337017240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 199105500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 183888375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                880113000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                819569400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               496944720                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               476105040                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184473528720                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184473528720                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           78935898240                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           78466357035                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625374711500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1625786589750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1890725207760                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1890543055560                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.434632                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.370138                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 374477040                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 345182040                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 204327750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 188343375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                878716800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                818313600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               606787200                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               586167840                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          184486751280                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          184486751280                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           79037968995                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           78368155155                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1625406641250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1625994197250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1890995670315                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1890787110540                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.482406                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.408568                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
@@ -361,15 +378,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               24027931                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         15718166                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           977317                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            14657289                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               10772949                       # Number of BTB hits
+system.cpu0.branchPred.lookups               24032454                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         15719473                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           977282                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            14661590                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               10774814                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.498919                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3877670                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             32392                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            73.490078                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3879582                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             32449                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -394,25 +411,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    17722563                       # DTB read hits
-system.cpu0.dtb.read_misses                     56347                       # DTB read misses
-system.cpu0.dtb.write_hits                   14648246                       # DTB write hits
-system.cpu0.dtb.write_misses                     8736                       # DTB write misses
+system.cpu0.dtb.read_hits                    17723797                       # DTB read hits
+system.cpu0.dtb.read_misses                     56461                       # DTB read misses
+system.cpu0.dtb.write_hits                   14648555                       # DTB write hits
+system.cpu0.dtb.write_misses                     8741                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3529                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      316                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2360                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3527                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      309                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2355                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      858                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                17778910                       # DTB read accesses
-system.cpu0.dtb.write_accesses               14656982                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      868                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17780258                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14657296                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         32370809                       # DTB hits
-system.cpu0.dtb.misses                          65083                       # DTB misses
-system.cpu0.dtb.accesses                     32435892                       # DTB accesses
+system.cpu0.dtb.hits                         32372352                       # DTB hits
+system.cpu0.dtb.misses                          65202                       # DTB misses
+system.cpu0.dtb.accesses                     32437554                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -434,8 +451,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    37749898                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10270                       # ITB inst misses
+system.cpu0.itb.inst_hits                    37754755                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10287                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -444,108 +461,108 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2361                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2369                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1943                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1949                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                37760168                       # ITB inst accesses
-system.cpu0.itb.hits                         37749898                       # DTB hits
-system.cpu0.itb.misses                          10270                       # DTB misses
-system.cpu0.itb.accesses                     37760168                       # DTB accesses
-system.cpu0.numCycles                       126937172                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                37765042                       # ITB inst accesses
+system.cpu0.itb.hits                         37754755                       # DTB hits
+system.cpu0.itb.misses                          10287                       # DTB misses
+system.cpu0.itb.accesses                     37765042                       # DTB accesses
+system.cpu0.numCycles                       126967483                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          18140410                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     112713647                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   24027931                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          14650619                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    104775763                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2822832                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    131776                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               38634                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       364177                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       430173                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        37568                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 37750515                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               265085                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3932                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         125329917                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.084963                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.263075                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          18140354                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     112726031                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   24032454                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          14654396                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    104803073                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2823208                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    134368                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               38414                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       364228                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       430065                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles        37874                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 37755386                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               265155                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3922                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         125359980                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.084816                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.263057                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                62773644     50.09%     50.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                21461872     17.12%     67.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 8766803      6.99%     74.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                32327598     25.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                62797458     50.09%     50.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                21463892     17.12%     67.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 8767294      6.99%     74.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                32331336     25.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           125329917                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.189290                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.887948                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                19211260                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58677383                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 41416135                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4957927                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1067212                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3055574                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               348409                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             110727822                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3998029                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1067212                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                24961632                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12004838                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      36556596                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 40485229                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10254410                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             105647594                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1060765                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1435224                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                161199                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 61281                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6055537                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          109729609                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            482383818                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       120922156                       # Number of integer rename lookups
+system.cpu0.fetch.rateDist::total           125359980                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.189280                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.887834                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                19213877                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             58702572                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 41417912                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4958150                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1067469                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3055480                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               348347                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             110732586                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3998245                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1067469                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                24964892                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12028946                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      36555738                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 40486723                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10256212                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             105650222                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1060720                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1433198                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                161272                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 61252                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               6057790                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          109732658                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            482396625                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       120923658                       # Number of integer rename lookups
 system.cpu0.rename.fp_rename_lookups             9389                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             98138163                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                11591443                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1228785                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1087461                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12318010                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            18735902                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           16202980                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1699572                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2289990                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 102687216                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1694558                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                100671408                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           483936                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9020941                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     22487287                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        122833                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    125329917                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.803251                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.034851                       # Number of insts issued each cycle
+system.cpu0.rename.CommittedMaps             98143798                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11588857                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1229050                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1087734                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12319550                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            18736791                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           16202841                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1700720                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2277601                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 102690318                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1694621                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                100676052                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           483863                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9017764                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     22481770                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        122874                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    125359980                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.803096                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.034807                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           69186063     55.20%     55.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           23179586     18.49%     73.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           22515563     17.97%     91.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            9334163      7.45%     99.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1114503      0.89%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 39      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           69212985     55.21%     55.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           23181797     18.49%     73.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           22515986     17.96%     91.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            9334603      7.45%     99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1114571      0.89%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 38      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      125329917                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      125359980                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                9379139     40.75%     40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                9379077     40.75%     40.75% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntMult                    80      0.00%     40.75% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.75% # attempts to use FU when none available
 system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.75% # attempts to use FU when none available
@@ -574,15 +591,15 @@ system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.75% # at
 system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.75% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.75% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5583986     24.26%     65.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8051096     34.98%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5582793     24.26%     65.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8054863     35.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             66410061     65.97%     65.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               93146      0.09%     66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             66413118     65.97%     65.97% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               93141      0.09%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
@@ -604,101 +621,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.06% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.06% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8111      0.01%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8113      0.01%     66.07% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.07% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.07% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            18430824     18.31%     84.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           15726990     15.62%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            18432239     18.31%     84.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           15727166     15.62%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             100671408                       # Type of FU issued
-system.cpu0.iq.rate                          0.793081                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   23014301                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228608                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         350139117                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        113410576                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     98583429                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              31853                       # Number of floating instruction queue reads
+system.cpu0.iq.FU_type_0::total             100676052                       # Type of FU issued
+system.cpu0.iq.rate                          0.792928                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   23016813                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228623                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         350180984                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        113410550                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     98587478                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              31776                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes             11293                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9723                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             123662855                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  20581                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          365420                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         9721                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             123670062                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  20530                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          365459                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2006460                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2583                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        19225                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1022371                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2006136                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2602                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        19208                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1021760                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       106487                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       336614                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       106419                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       336961                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1067212                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1617559                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               190582                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          104556500                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               1067469                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1620814                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               189225                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          104559654                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             18735902                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            16202980                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            876211                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 27258                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               139659                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         19225                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        291750                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       400567                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              692317                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             99574081                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             17974103                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1032379                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             18736791                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            16202841                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            876235                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 27148                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               138418                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         19208                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        291783                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       400552                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              692335                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             99578675                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             17975392                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1032310                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       174726                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    33509859                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                16843488                       # Number of branches executed
-system.cpu0.iew.exec_stores                  15535756                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.784436                       # Inst execution rate
-system.cpu0.iew.wb_sent                      99043344                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     98593152                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 51321674                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 84801576                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       174715                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    33511345                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                16844732                       # Number of branches executed
+system.cpu0.iew.exec_stores                  15535953                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.784285                       # Inst execution rate
+system.cpu0.iew.wb_sent                      99047596                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     98597199                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 51323656                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 84802398                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.776708                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.605197                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.776555                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.605215                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        8525747                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1571725                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           633113                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    123576047                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.768210                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.481297                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        8524425                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1571747                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           633147                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    123606126                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.768066                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.480848                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     79251877     64.13%     64.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     24711108     20.00%     84.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      8248464      6.67%     90.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3214478      2.60%     93.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      3439388      2.78%     96.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      1513562      1.22%     97.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1143910      0.93%     98.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       534023      0.43%     98.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1519237      1.23%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     79269760     64.13%     64.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     24721020     20.00%     84.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      8248963      6.67%     90.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3214548      2.60%     93.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      3440916      2.78%     96.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      1523839      1.23%     97.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1135185      0.92%     98.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       534039      0.43%     98.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1517856      1.23%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    123576047                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            78902307                       # Number of instructions committed
-system.cpu0.commit.committedOps              94932349                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    123606126                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            78906627                       # Number of instructions committed
+system.cpu0.commit.committedOps              94937680                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      31910051                       # Number of memory references committed
-system.cpu0.commit.loads                     16729442                       # Number of loads committed
-system.cpu0.commit.membars                     647161                       # Number of memory barriers committed
-system.cpu0.commit.branches                  16205593                       # Number of branches committed
+system.cpu0.commit.refs                      31911736                       # Number of memory references committed
+system.cpu0.commit.loads                     16730655                       # Number of loads committed
+system.cpu0.commit.membars                     647181                       # Number of memory barriers committed
+system.cpu0.commit.branches                  16206992                       # Number of branches committed
 system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 81881586                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             1929479                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 81886422                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             1929931                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        62923469     66.28%     66.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          90718      0.10%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        62927104     66.28%     66.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          90727      0.10%     66.38% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
@@ -722,222 +739,222 @@ system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% #
 system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8111      0.01%     66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8113      0.01%     66.39% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.39% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.39% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       16729442     17.62%     84.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      15180609     15.99%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       16730655     17.62%     84.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      15181081     15.99%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         94932349                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1519237                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         94937680                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1517856                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   221333052                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  208669303                       # The number of ROB writes
-system.cpu0.timesIdled                         109478                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        1607255                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5521794529                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   78780256                       # Number of Instructions Simulated
-system.cpu0.committedOps                     94810298                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.611282                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.611282                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.620624                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.620624                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               110616528                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               59738270                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8164                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                    2269                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                350776322                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                41073406                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              245816614                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1224552                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           712837                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          493.082878                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28842463                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           713349                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            40.432471                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                   221365586                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  208677314                       # The number of ROB writes
+system.cpu0.timesIdled                         109557                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        1607503                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5522172985                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   78784576                       # Number of Instructions Simulated
+system.cpu0.committedOps                     94815629                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.611578                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.611578                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.620510                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.620510                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               110621221                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               59741549                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     8143                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                350793071                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                41074475                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              246484638                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1224545                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           712867                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          493.083932                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28844186                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           713379                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            40.433186                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        256881000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.082878                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.963052                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.963052                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.083932                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.963055                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.963055                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63484078                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63484078                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15589241                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15589241                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12071944                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12071944                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       310964                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       310964                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363200                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       363200                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360654                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       360654                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27661185                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27661185                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     27972149                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       27972149                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       638343                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       638343                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1832165                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1832165                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       146120                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       146120                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24976                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        24976                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20612                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20612                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2470508                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2470508                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2616628                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2616628                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8099233830                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8099233830                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24956974532                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  24956974532                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    395327755                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    395327755                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    453888287                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    453888287                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       344500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       344500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  33056208362                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  33056208362                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  33056208362                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  33056208362                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     16227584                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     16227584                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13904109                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13904109                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457084                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       457084                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388176                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       388176                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381266                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381266                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     30131693                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     30131693                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     30588777                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     30588777                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039337                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.039337                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.131771                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.131771                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.319679                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.319679                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064342                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064342                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054062                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054062                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081990                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.081990                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085542                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.085542                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         63487140                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63487140                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15590249                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15590249                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     12072536                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      12072536                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       311110                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       311110                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363193                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       363193                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360660                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       360660                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27662785                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27662785                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     27973895                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       27973895                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       638253                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       638253                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1832121                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1832121                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       146008                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       146008                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25001                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25001                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20609                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20609                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2470374                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2470374                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2616382                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2616382                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8112547038                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   8112547038                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24972133492                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  24972133492                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    394969003                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    394969003                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    454279790                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    454279790                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       381000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       381000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  33084680530                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  33084680530                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  33084680530                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  33084680530                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16228502                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16228502                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13904657                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13904657                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457118                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       457118                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388194                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       388194                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381269                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381269                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     30133159                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     30133159                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30590277                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30590277                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039329                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.039329                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.131763                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.131763                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.319410                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.319410                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064403                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064403                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054054                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054054                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081982                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.081982                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085530                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.085530                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.550578                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.550578                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13630.176987                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 13630.176987                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15798.128195                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15798.128195                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22042.786647                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22042.786647                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1355                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      3366874                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               70                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         191323                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    19.357143                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    17.597853                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1345                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      3372122                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               71                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         191319                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.943662                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    17.625651                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       513073                       # number of writebacks
-system.cpu0.dcache.writebacks::total           513073                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       248142                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       248142                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1519584                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1519584                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18421                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18421                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1767726                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1767726                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1767726                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1767726                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       390201                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       390201                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312581                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312581                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101511                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       101511                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6555                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6555                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20612                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20612                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       702782                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       702782                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       804293                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       804293                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4170777489                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4170777489                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4999843092                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4999843092                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1415062493                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1415062493                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97847997                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97847997                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    411963713                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    411963713                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       324500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       324500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9170620581                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9170620581                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10585683074                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10585683074                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4217063246                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4217063246                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3187063995                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3187063995                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7404127241                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7404127241                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.022481                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022481                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222084                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222084                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016887                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016887                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054062                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054062                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023324                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023324                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026294                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026294                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       512814                       # number of writebacks
+system.cpu0.dcache.writebacks::total           512814                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       248043                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       248043                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1519569                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1519569                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18426                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18426                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1767612                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1767612                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1767612                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1767612                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       390210                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       390210                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312552                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       312552                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101508                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       101508                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6575                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6575                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20609                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20609                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       702762                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       702762                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       804270                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       804270                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4184101504                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4184101504                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5001279356                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5001279356                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1410085492                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1410085492                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97668747                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97668747                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    412365210                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    412365210                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       359000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       359000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9185380860                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9185380860                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10595466352                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10595466352                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4216928747                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4216928747                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3186876498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3186876498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7403805245                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7403805245                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024045                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024045                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.022478                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022478                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222061                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222061                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016937                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016937                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054054                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054054                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023322                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023322                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026292                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026292                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -945,427 +962,420 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1263629                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.774279                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           36446507                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1264141                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            28.831046                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1263628                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.774293                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36451354                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1264140                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            28.834903                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       6311559000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774279                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774293                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999559                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999559                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         76758780                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        76758780                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     36446507                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       36446507                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     36446507                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        36446507                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     36446507                       # number of overall hits
-system.cpu0.icache.overall_hits::total       36446507                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1300794                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1300794                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1300794                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1300794                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1300794                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1300794                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11016728605                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11016728605                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11016728605                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11016728605                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11016728605                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11016728605                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     37747301                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     37747301                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     37747301                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     37747301                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     37747301                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     37747301                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034461                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.034461                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034461                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.034461                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034461                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.034461                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8469.233872                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8469.233872                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8469.233872                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8469.233872                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8469.233872                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8469.233872                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       724171                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         76768570                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        76768570                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36451354                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36451354                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36451354                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36451354                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36451354                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36451354                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1300843                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1300843                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1300843                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1300843                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1300843                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1300843                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11016228057                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11016228057                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11016228057                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11016228057                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11016228057                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11016228057                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     37752197                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     37752197                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     37752197                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     37752197                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     37752197                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     37752197                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034457                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.034457                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034457                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.034457                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034457                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.034457                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8468.530066                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8468.530066                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8468.530066                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8468.530066                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs       721640                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs            96135                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs            96102                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.532855                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.509105                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets           42                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        36615                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        36615                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        36615                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        36615                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        36615                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        36615                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264179                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1264179                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264179                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1264179                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264179                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1264179                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8918143809                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8918143809                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8918143809                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8918143809                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8918143809                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8918143809                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        36666                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        36666                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        36666                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        36666                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        36666                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        36666                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264177                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1264177                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264177                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1264177                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264177                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1264177                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8917861032                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   8917861032                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8917861032                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   8917861032                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8917861032                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   8917861032                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    244130748                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    244130748                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033491                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.033491                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033491                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.033491                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7054.494505                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7054.494505                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7054.494505                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7054.494505                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033486                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.033486                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.033486                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7054.281981                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     11567606                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       525705                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     10416149                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       118627                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     11568415                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       525589                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     10417206                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       118474                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit        25546                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       481574                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       882370                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit        25510                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       481631                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       881553                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          396542                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16205.769061                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2244815                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          412792                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.438126                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle    2809084521500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4618.987809                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     8.979975                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     2.443926                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   942.112111                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1410.719068                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9222.526172                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.281921                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000548                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000149                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.057502                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.086103                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.562898                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989122                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8075                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8170                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           46                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          189                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3306                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4046                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          488                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          491                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3813                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3549                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          254                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.492859                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.498657                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        43582688                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       43582688                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        54105                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12184                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1242379                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       407374                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1716042                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       513072                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       513072                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        15340                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        15340                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2133                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2133                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       216716                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       216716                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        54105                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12184                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1242379                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       624090                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1932758                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        54105                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12184                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1242379                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       624090                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1932758                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          529                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          208                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        21771                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        90784                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       113292                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27958                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27958                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18479                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18479                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        52756                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        52756                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          529                       # number of demand (read+write) misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total    501186435                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       314500                       # number of SCUpgradeFailReq miss cycles
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-system.cpu0.l2cache.ReadReq_accesses::total      1829334                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       513073                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       513073                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        43298                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        43298                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20612                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.overall_accesses::cpu0.data       767630                       # number of overall (read+write) accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009683                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016785                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.017222                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.182239                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.061931                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.645711                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.645711                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.896517                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.896517                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.195775                       # miss rate for ReadExReq accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37240.603785                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29683.621101                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.255658                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17926.405143                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17926.405143                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19597.667082                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19597.667082                       # average SCUpgradeReq miss latency
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+system.cpu0.l2cache.tags.avg_refs            5.440162                       # Average number of references to valid blocks.
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    10.817381                       # Average occupied blocks per requestor
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   942.420690                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1398.445665                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9228.171558                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.282232                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.085354                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.563243                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          199                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3272                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4134                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          440                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3581                       # Occupied blocks per task id
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+system.cpu0.l2cache.Writeback_hits::writebacks       512814                       # number of Writeback hits
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.182080                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.061884                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.645932                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.645932                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.897521                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.897521                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.195928                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.195928                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.017244                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.186941                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.079087                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.017244                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.186941                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.079087                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.686866                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29803.987146                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31197.702249                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17932.450095                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17932.450095                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19586.975185                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19586.975185                       # average SCUpgradeReq miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49238.252919                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49238.252919                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37240.603785                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36870.636262                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 36869.116539                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26315.215501                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23778.846154                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37240.603785                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36870.636262                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 36869.116539                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        65149                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49252.405921                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49252.405921                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 36938.066195                       # average overall miss latency
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+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 36938.066195                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs        63742                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            1474                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs            1448                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    44.198779                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    44.020718                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       211864                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          211864                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       211838                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          211838                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         5535                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         3178                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         8714                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8807                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         8807                       # number of ReadExReq MSHR hits
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 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         5535                       # number of demand (read+write) MSHR hits
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 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
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-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       481571                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       481571                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27958                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27958                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18479                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18479                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43949                       # number of ReadExReq MSHR misses
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-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    481827867                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    481827867                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    249217743                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       244500                       # number of SCUpgradeFailReq MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    218713750                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4272573983                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7094126183                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7312839933                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7093849178                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7312562928                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.175860                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.057167                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.175694                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.057105                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.645711                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.645711                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.896517                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.896517                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163093                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163093                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.645932                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.645932                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.897521                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.897521                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163160                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163160                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for demand accesses
 system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171378                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.070767                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009683                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.016704                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.070716                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171378                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.300217                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22931.145641                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24957.897062                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45602.758858                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17233.989091                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17233.989091                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13486.538395                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13486.538395                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.300100                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237                       # average SCUpgradeReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29984.001024                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29984.001024                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25287.315617                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26445.116511                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19304.822306                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16830.917874                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36181.618810                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25287.315617                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45602.758858                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41086.910300                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1375,67 +1385,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       2021884                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1920690                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        19107                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19107                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       513073                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       646583                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        80962                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43193                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       104964                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq       2021847                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1920670                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       512814                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       646384                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        80933                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43154                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       104914                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       291894                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       281156                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2534332                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2360691                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        28712                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       120464                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          5044199                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80953568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86204446                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        49568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       218536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         167426118                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1040274                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3610797                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.254659                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.435670                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       291875                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       281146                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2534329                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2360353                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29069                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       120916                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5044667                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80953504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86188042                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50924                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       220524                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         167412994                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1039110                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3610193                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.254626                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.435651                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           2691274     74.53%     74.53% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            919523     25.47%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2690945     74.54%     74.54% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            919248     25.46%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3610797                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1890423984                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3610193                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    1889992000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    117333499                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    117303500                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1901305348                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1901297082                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1220101128                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1220075844                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     16329482                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     16351973                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     65866183                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     65816442                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               33911271                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         11563003                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           305102                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            18755199                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               14959397                       # Number of BTB hits
+system.cpu1.branchPred.lookups               33910806                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         11562772                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           305112                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            18755942                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               14959399                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            79.761334                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               12490268                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              7230                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            79.758185                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               12490105                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7221                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1459,25 +1469,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    10163694                       # DTB read hits
-system.cpu1.dtb.read_misses                     18763                       # DTB read misses
-system.cpu1.dtb.write_hits                    6542250                       # DTB write hits
-system.cpu1.dtb.write_misses                     2833                       # DTB write misses
+system.cpu1.dtb.read_hits                    10163643                       # DTB read hits
+system.cpu1.dtb.read_misses                     18794                       # DTB read misses
+system.cpu1.dtb.write_hits                    6541990                       # DTB write hits
+system.cpu1.dtb.write_misses                     2867                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2049                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       53                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.flush_entries                    2050                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       58                       # Number of TLB faults due to alignment restrictions
 system.cpu1.dtb.prefetch_faults                   373                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      411                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                10182457                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6545083                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      409                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                10182437                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6544857                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         16705944                       # DTB hits
-system.cpu1.dtb.misses                          21596                       # DTB misses
-system.cpu1.dtb.accesses                     16727540                       # DTB accesses
+system.cpu1.dtb.hits                         16705633                       # DTB hits
+system.cpu1.dtb.misses                          21661                       # DTB misses
+system.cpu1.dtb.accesses                     16727294                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1499,8 +1509,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    43642438                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7000                       # ITB inst misses
+system.cpu1.itb.inst_hits                    43641889                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7003                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1513,94 +1523,94 @@ system.cpu1.itb.flush_entries                    1205                       # Nu
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      538                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      544                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                43649438                       # ITB inst accesses
-system.cpu1.itb.hits                         43642438                       # DTB hits
-system.cpu1.itb.misses                           7000                       # DTB misses
-system.cpu1.itb.accesses                     43649438                       # DTB accesses
-system.cpu1.numCycles                       104622324                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                43648892                       # ITB inst accesses
+system.cpu1.itb.hits                         43641889                       # DTB hits
+system.cpu1.itb.misses                           7003                       # DTB misses
+system.cpu1.itb.accesses                     43648892                       # DTB accesses
+system.cpu1.numCycles                       104622935                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           9983715                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     109168018                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   33911271                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          27449665                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     91793931                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3775602                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     78298                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               31640                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       200637                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       294928                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         7575                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 43641835                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               116209                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2258                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         104278525                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.296897                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.339782                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           9986788                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     109166158                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   33910806                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          27449504                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     91794015                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3775656                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     78908                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               31556                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       200392                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       294710                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         7499                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 43641278                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               116202                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2270                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         104281696                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.296833                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.339781                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                47329971     45.39%     45.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                14035379     13.46%     58.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 7536372      7.23%     66.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                35376803     33.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                47334317     45.39%     45.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                14034977     13.46%     58.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 7536210      7.23%     66.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                35376192     33.92%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           104278525                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.324130                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.043449                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                13017622                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             61671390                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 26724772                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1111637                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1753104                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              754173                       # Number of times decode resolved a branch
+system.cpu1.fetch.rateDist::total           104281696                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.324124                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.043425                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                13018026                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             61674095                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 26725105                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1111367                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1753103                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              754241                       # Number of times decode resolved a branch
 system.cpu1.decode.BranchMispred               137598                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              68061604                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1168958                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1753104                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                17450100                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2254257                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      56981217                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 23380222                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2459625                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              55156752                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               230613                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               263389                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 35416                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 18082                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1432431                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           55002738                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            260522478                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        58680214                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1689                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             52222609                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 2780129                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1878054                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1805384                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 13101359                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            10457131                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6914141                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           629237                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          831086                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  54264809                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             589071                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 53908897                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           111732                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2292977                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      5809537                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         48790                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    104278525                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.516970                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.852578                       # Number of insts issued each cycle
+system.cpu1.decode.DecodedInsts              68060945                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1169140                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1753103                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                17450583                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2252903                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      56981552                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 23380155                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2463400                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              55156301                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               230486                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               263427                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 35391                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 18241                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1436172                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           55002320                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            260520543                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        58679791                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             1657                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             52223668                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2778652                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1878098                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1805410                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 13101415                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            10456972                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6914054                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           629493                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          831483                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  54264321                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             589116                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 53908666                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           111755                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2291961                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      5808692                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         48780                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    104281696                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.516952                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.852554                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           71027306     68.11%     68.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           16528003     15.85%     83.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           13076309     12.54%     96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3359364      3.22%     99.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             287531      0.28%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           71029795     68.11%     68.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           16529290     15.85%     83.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           13075763     12.54%     96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3359554      3.22%     99.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             287282      0.28%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
@@ -1608,9 +1618,9 @@ system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Nu
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      104278525                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      104281696                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2925381     45.12%     45.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2925282     45.12%     45.12% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntMult                   677      0.01%     45.13% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.13% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.13% # attempts to use FU when none available
@@ -1639,131 +1649,131 @@ system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.13% # at
 system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.13% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.13% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1673591     25.81%     70.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1884116     29.06%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1673331     25.81%     70.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1884639     29.07%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             36727260     68.13%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               46535      0.09%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  2      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 1      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             36727327     68.13%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               46544      0.09%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMisc          3339      0.01%     68.22% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            10380151     19.25%     87.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            6751543     12.52%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            10380092     19.25%     87.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            6751298     12.52%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              53908897                       # Type of FU issued
-system.cpu1.iq.rate                          0.515271                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    6483765                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.120273                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         218686026                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         57154966                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     51920427                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               5790                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2052                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1786                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              60388895                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   3701                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           91393                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              53908666                       # Type of FU issued
+system.cpu1.iq.rate                          0.515266                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    6483929                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.120276                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         218688932                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         57153517                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     51920276                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               5780                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              60388837                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   3692                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           91402                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       490676                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          687                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10193                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       356081                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       490292                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          689                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        10197                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       355874                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        51970                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        70495                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        52006                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        70534                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1753104                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 548003                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               114295                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           54906042                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               1753103                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 547921                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               114364                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           54905583                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             10457131                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6914141                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            301584                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  9824                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                96972                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10193                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         54960                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       127313                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              182273                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             53638837                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             10278190                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           248481                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             10456972                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6914054                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            301613                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  9861                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                97001                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         10197                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         54939                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       127326                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              182265                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             53638641                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             10278143                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           248381                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        52162                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    16965416                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                11807917                       # Number of branches executed
-system.cpu1.iew.exec_stores                   6687226                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.512690                       # Inst execution rate
-system.cpu1.iew.wb_sent                      53497875                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     51922213                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 25229776                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 38490454                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        52146                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    16965109                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                11808008                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6686966                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.512685                       # Inst execution rate
+system.cpu1.iew.wb_sent                      53497702                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     51922060                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 25229975                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 38490431                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.496282                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.655481                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.496278                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.655487                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        3658692                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         540281                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           170405                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    102346479                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.498098                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.159114                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        3657476                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         540336                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           170387                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    102349842                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.498091                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.159102                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     76767559     75.01%     75.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     14288132     13.96%     88.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6080244      5.94%     94.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       703970      0.69%     95.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1980102      1.93%     97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      1566998      1.53%     99.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       444730      0.43%     99.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       123732      0.12%     99.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       391012      0.38%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     76769313     75.01%     75.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     14290135     13.96%     88.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6080073      5.94%     94.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       704006      0.69%     95.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1980080      1.93%     97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      1566587      1.53%     99.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       444714      0.43%     99.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       123770      0.12%     99.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       391164      0.38%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    102346479                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            41392684                       # Number of instructions committed
-system.cpu1.commit.committedOps              50978528                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    102349842                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            41393585                       # Number of instructions committed
+system.cpu1.commit.committedOps              50979540                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      16524515                       # Number of memory references committed
-system.cpu1.commit.loads                      9966455                       # Number of loads committed
-system.cpu1.commit.membars                     209698                       # Number of memory barriers committed
-system.cpu1.commit.branches                  11639872                       # Number of branches committed
+system.cpu1.commit.refs                      16524860                       # Number of memory references committed
+system.cpu1.commit.loads                      9966680                       # Number of loads committed
+system.cpu1.commit.membars                     209721                       # Number of memory barriers committed
+system.cpu1.commit.branches                  11640060                       # Number of branches committed
 system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 45828467                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             3366626                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 45829312                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             3366651                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        34405041     67.49%     67.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          45633      0.09%     67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        34405704     67.49%     67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          45637      0.09%     67.58% # Class of committed instruction
 system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.58% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.58% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.58% # Class of committed instruction
@@ -1791,217 +1801,217 @@ system.cpu1.commit.op_class_0::SimdFloatMisc         3339      0.01%     67.59%
 system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.59% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.59% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        9966455     19.55%     87.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       6558060     12.86%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        9966680     19.55%     87.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       6558180     12.86%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         50978528                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               391012                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         50979540                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               391164                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   136555973                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  111202855                       # The number of ROB writes
-system.cpu1.timesIdled                          53415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         343799                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5543567058                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   41359830                       # Number of Instructions Simulated
-system.cpu1.committedOps                     50945674                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.529564                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.529564                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.395325                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.395325                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                56285102                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               35740910                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1413                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                     520                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                191162273                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                15560809                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              205875708                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                388862                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   136558924                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  111202252                       # The number of ROB writes
+system.cpu1.timesIdled                          53311                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         341239                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5543976372                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   41360731                       # Number of Instructions Simulated
+system.cpu1.committedOps                     50946686                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.529523                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.529523                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.395331                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.395331                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                56284724                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               35740870                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     1381                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                191161936                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                15560884                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              205876605                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                388900                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements           191071                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.558495                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           15741437                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse          472.564441                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           15741519                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs           191395                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            82.245811                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            82.246239                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     102871508500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.558495                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922966                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.922966                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.564441                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922977                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.922977                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         32983767                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        32983767                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      9574609                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        9574609                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      5910607                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       5910607                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49573                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        49573                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79145                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        79145                       # number of LoadLockedReq hits
+system.cpu1.dcache.tags.tag_accesses         32983738                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        32983738                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      9574548                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        9574548                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5910552                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       5910552                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49554                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        49554                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79147                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        79147                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71001                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        71001                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     15485216                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        15485216                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     15534789                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       15534789                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       219415                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       219415                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       398307                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       398307                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30093                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30093                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18121                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        18121                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23394                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23394                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       617722                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        617722                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       647815                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       647815                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3455998019                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3455998019                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8728631208                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8728631208                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363006249                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    363006249                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    542688316                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    542688316                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       504500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       504500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  12184629227                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12184629227                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  12184629227                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12184629227                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9794024                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9794024                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      6308914                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      6308914                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79666                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79666                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97266                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        97266                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94395                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        94395                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     16102938                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     16102938                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     16182604                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     16182604                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022403                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.022403                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.063134                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.063134                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377740                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377740                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186304                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186304                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.247831                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.247831                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038361                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038361                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040032                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.040032                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_hits::cpu1.data     15485100                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        15485100                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     15534654                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       15534654                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       219354                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       219354                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       398461                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       398461                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30111                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30111                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18127                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        18127                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23403                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23403                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       617815                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        617815                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       647926                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       647926                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3453063988                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3453063988                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8746670918                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   8746670918                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363087750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    363087750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    542334299                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    542334299                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       511000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       511000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  12199734906                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  12199734906                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  12199734906                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  12199734906                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9793902                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9793902                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6309013                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6309013                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79665                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79665                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97274                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        97274                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94404                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        94404                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     16102915                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     16102915                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     16182580                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     16182580                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022397                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.063157                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.063157                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377970                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377970                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186350                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186350                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.247903                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.247903                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038367                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.038367                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040038                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.040038                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          357                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1112453                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               37                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          39616                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.648649                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    28.080902                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          358                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1116392                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               38                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          39638                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.421053                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    28.164690                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       117473                       # number of writebacks
-system.cpu1.dcache.writebacks::total           117473                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79558                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        79558                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306502                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       306502                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13187                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13187                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       386060                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       386060                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       386060                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       386060                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139857                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       139857                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91805                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        91805                       # number of WriteReq MSHR misses
+system.cpu1.dcache.writebacks::writebacks       117580                       # number of writebacks
+system.cpu1.dcache.writebacks::total           117580                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79511                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        79511                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306644                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       306644                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13188                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13188                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       386155                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       386155                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       386155                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       386155                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139843                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       139843                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91817                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        91817                       # number of WriteReq MSHR misses
 system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28628                       # number of SoftPFReq MSHR misses
 system.cpu1.dcache.SoftPFReq_mshr_misses::total        28628                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4934                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4934                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23394                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23394                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       231662                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       231662                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       260290                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       260290                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1829354050                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1829354050                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2195265722                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2195265722                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    493416244                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    493416244                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87143250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87143250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    494733684                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    494733684                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       482500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       482500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4024619772                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4024619772                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4518036016                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4518036016                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298838492                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298838492                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826630495                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826630495                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125468987                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125468987                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014280                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014280                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014552                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014552                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359350                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359350                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050727                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050727                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.247831                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.247831                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4939                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4939                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23403                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23403                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       231660                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       231660                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       260288                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       260288                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1827288064                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1827288064                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2196971984                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2196971984                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494563997                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494563997                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87258999                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87258999                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    494349701                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    494349701                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       489000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       489000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4024260048                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4024260048                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4518824045                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4518824045                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298813494                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298813494                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826635494                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826635494                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125448988                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125448988                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014279                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014279                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014553                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014553                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359355                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359355                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050774                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050774                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.247903                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.247903                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014386                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.014386                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016085                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.016085                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13080.175107                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13080.175107                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23912.267545                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17235.442364                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17661.785570                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016084                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.016084                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2009,425 +2019,425 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           607164                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.524787                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           43017402                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           607676                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            70.790030                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           607210                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.525690                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           43016771                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           607722                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            70.783633                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle      78589984500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.524787                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975634                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975634                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.525690                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975636                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975636                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         87891037                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        87891037                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     43017402                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       43017402                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     43017402                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        43017402                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     43017402                       # number of overall hits
-system.cpu1.icache.overall_hits::total       43017402                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       624277                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       624277                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       624277                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        624277                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       624277                       # number of overall misses
-system.cpu1.icache.overall_misses::total       624277                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5095487535                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5095487535                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5095487535                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5095487535                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5095487535                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5095487535                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     43641679                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     43641679                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     43641679                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     43641679                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     43641679                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     43641679                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014305                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014305                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014305                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014305                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014305                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014305                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8162.222115                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8162.222115                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8162.222115                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8162.222115                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8162.222115                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8162.222115                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       276500                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses         87889967                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        87889967                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     43016771                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       43016771                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     43016771                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        43016771                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     43016771                       # number of overall hits
+system.cpu1.icache.overall_hits::total       43016771                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       624350                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       624350                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       624350                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        624350                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       624350                       # number of overall misses
+system.cpu1.icache.overall_misses::total       624350                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5095278041                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5095278041                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5095278041                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5095278041                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5095278041                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5095278041                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     43641121                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     43641121                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     43641121                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     43641121                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     43641121                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     43641121                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014306                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014306                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014306                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014306                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014306                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014306                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8160.932235                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8160.932235                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8160.932235                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8160.932235                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       275120                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            36143                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            36110                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.650167                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.618942                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16598                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        16598                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        16598                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        16598                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        16598                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        16598                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       607679                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       607679                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       607679                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       607679                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       607679                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       607679                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4104857215                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4104857215                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4104857215                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4104857215                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4104857215                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4104857215                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16625                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        16625                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        16625                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        16625                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        16625                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        16625                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       607725                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       607725                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       607725                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       607725                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       607725                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       607725                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4103508232                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4103508232                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4103508232                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4103508232                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4103508232                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4103508232                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8190250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      8190250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013924                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.013924                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013924                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.013924                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6754.976254                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6754.976254                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6754.976254                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6754.976254                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013926                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013926                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013926                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6752.245229                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4841342                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43201                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4639993                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        42894                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4841883                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43038                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4641023                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        42756                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         5995                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       109259                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       564002                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         5990                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       109076                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       564189                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           85775                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15600.933964                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            846435                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs          100895                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.389266                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements           85682                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15604.887972                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            847212                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs          100795                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            8.405298                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5997.093337                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.379548                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     1.187782                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   717.531946                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1990.637648                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6884.103702                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.366034                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000634                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000072                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.043795                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.121499                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.420172                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.952205                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks  6001.492372                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     7.158596                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.882758                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   688.413448                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1964.460870                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6940.479928                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.366302                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000437                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000176                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.042017                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.119901                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.423613                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.952447                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9541                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           25                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5554                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          314                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         8089                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1138                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5548                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          308                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         8077                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1156                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4157                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          969                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4190                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          941                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.582336                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001526                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.338989                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        16876081                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       16876081                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16270                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7392                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       601743                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       101269                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        726674                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       117472                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       117472                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2261                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         2261                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          802                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          802                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28891                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        28891                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16270                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7392                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       601743                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       130160                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         755565                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16270                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7392                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       601743                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       130160                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        755565                       # number of overall hits
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001465                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.338623                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        16881821                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       16881821                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16379                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7476                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst       601754                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data       101261                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        726870                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       117580                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       117580                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2286                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2286                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          847                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total          847                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28888                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        28888                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16379                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7476                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       601754                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       130149                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         755758                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16379                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7476                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       601754                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       130149                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        755758                       # number of overall hits
 system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          463                       # number of ReadReq misses
 system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5933                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        72130                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        78803                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28401                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28401                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22590                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30613.932808                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27539.535684                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 27664.215773                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs        21207                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs             493                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs             485                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    46.622718                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    43.725773                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        40759                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           40759                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           13                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1321                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           73                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total         1407                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1252                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1252                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           13                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1321                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1325                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         2659                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           13                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1321                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1325                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         2659                       # number of overall MSHR hits
+system.cpu1.l2cache.writebacks::writebacks        40787                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           40787                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           14                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1333                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total         1422                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1248                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         1248                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           14                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1333                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1323                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         2670                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1323                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         2670                       # number of overall MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          463                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          264                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4612                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72057                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        77396                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       109257                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       109257                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28401                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28401                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22590                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22590                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31682                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31682                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          263                       # number of ReadReq MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72054                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        77415                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       109072                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       109072                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28394                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28394                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22555                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22555                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31685                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        31685                       # number of ReadExReq MSHR misses
 system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          463                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          264                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4612                       # number of demand (read+write) MSHR misses
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 system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103739                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       109078                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       109100                       # number of demand (read+write) MSHR misses
 system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          463                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          264                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4612                       # number of overall MSHR misses
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 system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103739                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       109257                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       218335                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    126408787                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1106793437                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1243718226                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3470833266                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3470833266                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    417527555                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    417527555                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308789786                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308789786                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       394499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       394499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    943695401                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    943695401                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    126408787                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2050488838                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2187413627                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6946001                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3570001                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    126408787                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2050488838                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3470833266                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   5658246893                       # number of overall MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_misses::total       218172                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    124690282                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1106071688                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1241469220                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3463800362                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3463800362                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    417384045                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    417384045                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308383273                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308383273                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       400999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       400999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    945118400                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    945118400                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    124690282                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2051190088                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2186587620                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    124690282                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2051190088                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3463800362                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   5650387982                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2182197007                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189537757                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737457999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737457999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2182174505                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189515255                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737462500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737462500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3919655006                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3926995756                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.415556                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.096087                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3919637005                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3926977755                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.415560                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.096083                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.926261                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.926261                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.965715                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.965715                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.925489                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.925489                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963807                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963807                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.512446                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.512446                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.441022                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.125767                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027670                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.034424                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.007590                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.441022                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.512528                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.512528                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.125760                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.251740                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.251487                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       400999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       400999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2437,63 +2447,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1294408                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       865128                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq       1294463                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       865156                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq        11871                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp        11871                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       117472                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       157468                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        84838                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41861                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        87109                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       117580                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       157134                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        84893                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41888                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        87131                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        79574                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66376                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1215557                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       825064                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17352                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37871                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2095844                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38892880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25436874                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        30676                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        66932                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          64427362                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     834611                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1797339                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.418381                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.493294                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        79541                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        66364                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1215649                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       825187                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17442                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37966                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2096244                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38895824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25442442                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        31012                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        67368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          64436646                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     834109                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1797203                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.418253                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.493272                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5           1045366     58.16%     58.16% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            751973     41.84%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1045518     58.17%     58.17% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            751685     41.83%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1797339                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     659657903                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1797203                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     659823435                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     81258998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     81245999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    912908354                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    912982594                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    403842529                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    403842731                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      9825216                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      9829718                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     21209360                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     21193613                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31016                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31016                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59408                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59439                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           31                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59439                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              23215                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56654                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -2584,416 +2594,424 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326664315                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347117122                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84753000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36832361                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36830633                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36453                       # number of replacements
-system.iocache.tags.tagsinuse               14.560247                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.560350                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36469                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         254140674000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.560247                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.910015                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.910015                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         254140746000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.560350                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.910022                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.910022                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328487                       # Number of tag accesses
-system.iocache.tags.data_accesses              328487                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328239                       # Number of tag accesses
+system.iocache.tags.data_accesses              328239                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          247                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              247                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           31                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           31                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          247                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               247                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          247                       # number of overall misses
 system.iocache.overall_misses::total              247                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     30832377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     30832377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     30832377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     30832377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     30832377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     30832377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     30846377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30846377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9649955112                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9649955112                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30846377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30846377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30846377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30846377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          247                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            247                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36255                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36255                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          247                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             247                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          247                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            247                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000855                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000855                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124827.437247                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124827.437247                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124827.437247                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124827.437247                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124827.437247                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124884.117409                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124884.117409                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124884.117409                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         57106                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7195                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.936901                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36206                       # number of writebacks
+system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          247                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          247                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          247                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          247                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          247                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          247                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17987377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17987377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2253111299                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2253111299                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17987377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17987377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17987377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17987377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18001377                       # number of ReadReq MSHR miss cycles
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+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18001377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18001377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18001377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18001377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
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 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72823.388664                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72823.388664                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826                       # average ReadReq mshr miss latency
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+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   153470                       # number of replacements
-system.l2c.tags.tagsinuse                64454.116988                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     519887                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   218097                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.383742                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   153362                       # number of replacements
+system.l2c.tags.tagsinuse                64452.240621                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     520061                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   218026                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.385316                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   14115.348135                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.484821                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     2.876495                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1418.724430                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2146.622945                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.503287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.002749                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      292.346121                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      885.503464                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6306.489787                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.215383                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000221                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   14085.588040                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.542715                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     2.877015                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1413.412167                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2156.075780                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.498933                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000005                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      294.129683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      883.808465                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6297.115959                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.214929                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000222                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.inst       0.021648                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.032755                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.599155                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.599658                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000084                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004461                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.013512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.096229                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983492                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        44297                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        20314                       # Occupied blocks per task id
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+system.l2c.tags.occ_percent::cpu1.data       0.013486                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1022        44393                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        20252                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1022::2          411                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         7726                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        36160                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         7759                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        36223                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          331                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4599                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        15358                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.309967                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6595063                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6595063                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker          272                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker          133                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst              12554                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data              38932                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       181919                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           84                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           48                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst               4143                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              11543                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        44205                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 293833                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          252624                       # number of Writeback hits
-system.l2c.Writeback_hits::total               252624                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           11705                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             720                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               12425                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           181                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           174                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               355                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             3713                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1233                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 4946                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           272                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           133                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               12554                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               42645                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       181919                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            84                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            48                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                4143                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               12776                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher        44205                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  298779                       # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.itb.walker          133                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              12554                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              42645                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       181919                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           84                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           48                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst               4143                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              12776                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher        44205                       # number of overall hits
-system.l2c.overall_hits::total                 298779                       # number of overall hits
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+system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4616                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        15266                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_percent::1024     0.309021                       # Percentage of cache occupancy per task id
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+system.l2c.tags.data_accesses                 6595512                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker          297                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker          126                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst              12544                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data              38879                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       182049                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker           77                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker           46                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst               4168                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              11674                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        44095                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 293955                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          252625                       # number of Writeback hits
+system.l2c.Writeback_hits::total               252625                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           11700                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             714                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               12414                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           188                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           168                       # number of SCUpgradeReq hits
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 system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
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 system.l2c.overall_misses::cpu0.dtb.walker           34                       # number of overall misses
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.798489                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.484867                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_latency::cpu0.data      7000718                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      3239366                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     10240084                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1399947                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1250448                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2650395                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total   1277162663                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      2746500                       # number of demand (read+write) miss cycles
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+system.l2c.Writeback_accesses::writebacks       252625                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           252625                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        20569                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         3574                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           24143                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          941                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1380                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2321                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data         8436                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            19881                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          331                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total              513396                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          331                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total             513396                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.229342                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.431183                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800224                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.485814                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.800213                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.878261                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.846618                       # miss rate for SCUpgradeReq accesses
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+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for overall accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94005.564914                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76950                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 102744.306418                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 88245.330460                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::total 114406.636697                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   994.175955                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   803.686960                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1389.128171                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   846.024066                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1054.204708                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91719.302035                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.285080                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85075.547075                       # average ReadExReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1132.645455                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   873.056868                       # average UpgradeReq miss latency
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+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1031.722772                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1348.801527                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 79593.239424                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::total 112359.642684                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 79593.239424                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120546.676041                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 112359.642684                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               853                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 94187.782748                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 90667.795292                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 79788.493133                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 112420.821275                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               117                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       17                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     50.176471                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     19.500000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              113437                       # number of writebacks
-system.l2c.writebacks::total                   113437                       # number of writebacks
+system.l2c.writebacks::writebacks              113392                       # number of writebacks
+system.l2c.writebacks::total                   113392                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
@@ -3010,186 +3028,186 @@ system.l2c.overall_mshr_hits::cpu1.inst             2                       # nu
 system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                24                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            5                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         3728                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         8659                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       164282                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            6                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         3733                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.798489                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.484867                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.873822                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.demand_mshr_miss_rate::total      0.417956                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.111111                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.036232                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.228965                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.278031                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474524                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.106383                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.020408                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.103978                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.402432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.321941                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.417956                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3455077000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10019651249                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.181973                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.105852                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.404316                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.431183                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800224                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.485814                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.800213                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.878261                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.846618                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.677064                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.854670                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.752427                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.417796                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.417796                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76970.747485                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75969.428365                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 102163.161014                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.617657                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10125.469580                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10150.534828                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10408.637450                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.822607                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10198.424936                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79738.846045                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65521.915811                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72886.511866                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 100059.867975                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78278.833577                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67202.369995                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 100121.391300                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        64450                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 100059.867975                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78278.833577                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67202.369995                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 100121.391300                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -3204,57 +3222,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              237839                       # Transaction distribution
-system.membus.trans_dist::ReadResp             237839                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30978                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30978                       # Transaction distribution
-system.membus.trans_dist::Writeback            113437                       # Transaction distribution
+system.membus.trans_dist::ReadReq              237783                       # Transaction distribution
+system.membus.trans_dist::ReadResp             237783                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30976                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30976                       # Transaction distribution
+system.membus.trans_dist::Writeback            149598                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            79519                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40695                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13753                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             31200                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14872                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            79558                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40675                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13780                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             31194                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            14873                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107968                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13742                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       708866                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       830616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72710                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72710                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 903326                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       708374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       830114                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108916                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108916                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 939030                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27484                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21055004                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     21245656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23564952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123021                       # Total snoops (count)
-system.membus.snoop_fanout::samples            500917                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21024476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     21215108                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4636480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4636480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                25851588                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123388                       # Total snoops (count)
+system.membus.snoop_fanout::samples            537032                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  500917    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  537032    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              500917                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81243492                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              537032                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81237991                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               26500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11638997                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11614997                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1642210248                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1967612498                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2114152611                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2113693587                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38560639                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38580367                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -3287,48 +3305,48 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             659694                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            659679                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30978                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30978                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           252624                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36230                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           91840                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41050                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         132890                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           21                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            40171                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           40171                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1298541                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       426600                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1725141                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     40737982                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8560538                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               49298520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          291438                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1083643                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.033661                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.180356                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq             659684                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            659669                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30976                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30976                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           252625                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           91886                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41031                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         132917                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            40129                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           40129                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1298615                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       426559                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1725174                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     40738026                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8562330                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               49300356                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          291348                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1083611                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.033657                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.180345                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1047166     96.63%     96.63% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36477      3.37%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1047140     96.63%     96.63% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36471      3.37%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1083643                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1586607093                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1083611                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1586551162                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy          1044000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2272505602                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2272414912                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         846502909                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         846278221                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1853                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2766                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index b94dfc3eb..b41e9656d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,125 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.826844                       # Number of seconds simulated
-sim_ticks                                2826844351500                       # Number of ticks simulated
-final_tick                               2826844351500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827042                       # Number of seconds simulated
+sim_ticks                                2827042159500                       # Number of ticks simulated
+final_tick                               2827042159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107954                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130942                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2695726613                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 568304                       # Number of bytes of host memory used
-host_seconds                                  1048.64                       # Real time elapsed on the host
-sim_insts                                   113204796                       # Number of instructions simulated
-sim_ops                                     137311416                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 100972                       # Simulator instruction rate (inst/s)
+host_op_rate                                   122474                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2522254422                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 564960                       # Number of bytes of host memory used
+host_seconds                                  1120.84                       # Real time elapsed on the host
+sim_insts                                   113173742                       # Number of instructions simulated
+sim_ops                                     137273263                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst           1324048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9514916                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9496932                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10841588                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10823604                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1324048                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5800064                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      8116352                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8135924                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8133876                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              22933                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             149190                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             148909                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                172164                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           90626                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                171883                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126818                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               131231                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               131199                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            430                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468384                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3365914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               468351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3359317                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3835226                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2051780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3828597                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          468351                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             468351                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2870970                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          820114                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2878094                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2051780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2877168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2870970                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           430                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3372113                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          820454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6713320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        172165                       # Number of read requests accepted
-system.physmem.writeReqs                       131231                       # Number of write requests accepted
-system.physmem.readBursts                      172165                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     131231                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11009408                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8149760                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10841652                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8135924                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4545                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10989                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10130                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11201                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11419                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13122                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10546                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11171                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11539                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10356                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11056                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10496                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9259                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10183                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10761                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10049                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9745                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8312                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7765                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8704                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8604                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7611                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7949                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8258                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8579                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7843                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8531                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7842                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6872                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7611                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8198                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7118                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              468351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3365516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6705765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        171884                       # Number of read requests accepted
+system.physmem.writeReqs                       167423                       # Number of write requests accepted
+system.physmem.readBursts                      171884                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     167423                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10992576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10315392                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10823668                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10452212                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6228                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4543                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10965                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10116                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11197                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11389                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13120                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10535                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11120                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11540                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10348                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11053                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10478                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9244                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10124                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10758                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10029                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9743                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10407                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9909                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10642                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10446                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9703                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10218                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10399                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10626                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10202                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10761                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9802                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9030                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9755                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10443                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9720                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9115                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2826844140500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827041948500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2993                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  168617                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  168336                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 126850                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16016                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 163042                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151765                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     15965                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -162,156 +159,174 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8902                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10773                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9486                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      347                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.286868                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.931959                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.707872                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23391     37.64%     37.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14782     23.79%     61.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6350     10.22%     71.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3679      5.92%     77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2602      4.19%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1532      2.47%     84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1126      1.81%     86.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1130      1.82%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7555     12.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62147                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6420                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.793614                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      556.638433                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6418     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6420                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6420                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.834891                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.369444                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.492928                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5612     87.41%     87.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              54      0.84%     88.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.47%     88.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             211      3.29%     92.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             221      3.44%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              14      0.22%     95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.20%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              15      0.23%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              17      0.26%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.06%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.05%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.08%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             167      2.60%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.11%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.06%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              10      0.16%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               5      0.08%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.05%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6420                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2072280000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5297692500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    860110000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12046.60                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64399                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.873212                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     190.977516                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.816153                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23539     36.55%     36.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14785     22.96%     59.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6319      9.81%     69.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3687      5.73%     75.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2636      4.09%     79.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1562      2.43%     81.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1140      1.77%     83.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1107      1.72%     85.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9624     14.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64399                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6814                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.206340                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      540.339482                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6812     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6814                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6814                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.653948                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.805353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.459775                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5702     83.68%     83.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              39      0.57%     84.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              26      0.38%     84.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             231      3.39%     88.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             131      1.92%     89.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              61      0.90%     90.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              35      0.51%     91.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              27      0.40%     91.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             123      1.81%     93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              13      0.19%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              19      0.28%     94.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.16%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              31      0.45%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              13      0.19%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              13      0.19%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.38%     95.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              61      0.90%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              10      0.15%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               9      0.13%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              11      0.16%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              89      1.31%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             7      0.10%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            18      0.26%     98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.06%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             5      0.07%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             4      0.06%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            26      0.38%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             4      0.06%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.06%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             5      0.07%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            11      0.16%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            11      0.16%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.04%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             3      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             3      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6814                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2084525750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5305007000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    858795000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12136.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30796.60                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30886.34                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.88                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.88                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.07                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     142002                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95212                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9317341.50                       # Average gap between requests
-system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2694665773000                       # Time in different power states
-system.physmem.memoryStateTime::REF       94394300000                       # Time in different power states
+system.physmem.avgWrQLen                        25.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     141721                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    126816                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8331811.45                       # Average gap between requests
+system.physmem.pageHitRate                      80.65                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2694668588500                       # Time in different power states
+system.physmem.memoryStateTime::REF       94401060000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37784264500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       37972497000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 245987280                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 223844040                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 134219250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 122137125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                702912600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                638851200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               426267360                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               398895840                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184635250800                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184635250800                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           80264555415                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           79079779350                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625694839250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1626734116500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1892104031955                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1891832874855                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.336036                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.240113                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 254499840                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 232356600                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 138864000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 126781875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                701859600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                637852800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               533628000                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               510805440                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          184648473360                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          184648473360                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           80377758270                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           79142156730                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1625717004000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1626800865000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1892372087070                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1892099291805                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.382923                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.286428                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
@@ -330,15 +345,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46964274                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24050124                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1232745                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29560624                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21375180                       # Number of BTB hits
+system.cpu.branchPred.lookups                46933448                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24039449                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232882                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29542848                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21360620                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.309637                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11765118                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33710                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.303862                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11754095                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33720                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -363,25 +378,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25471879                       # DTB read hits
-system.cpu.dtb.read_misses                      60408                       # DTB read misses
-system.cpu.dtb.write_hits                    19919747                       # DTB write hits
-system.cpu.dtb.write_misses                      9388                       # DTB write misses
+system.cpu.dtb.read_hits                     25465003                       # DTB read hits
+system.cpu.dtb.read_misses                      60438                       # DTB read misses
+system.cpu.dtb.write_hits                    19916425                       # DTB write hits
+system.cpu.dtb.write_misses                      9382                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4324                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       351                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2316                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       344                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2309                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1300                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25532287                       # DTB read accesses
-system.cpu.dtb.write_accesses                19929135                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25525441                       # DTB read accesses
+system.cpu.dtb.write_accesses                19925807                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45391626                       # DTB hits
-system.cpu.dtb.misses                           69796                       # DTB misses
-system.cpu.dtb.accesses                      45461422                       # DTB accesses
+system.cpu.dtb.hits                          45381428                       # DTB hits
+system.cpu.dtb.misses                           69820                       # DTB misses
+system.cpu.dtb.accesses                      45451248                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -403,8 +418,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     66240582                       # ITB inst hits
-system.cpu.itb.inst_misses                      11936                       # ITB inst misses
+system.cpu.itb.inst_hits                     66294026                       # ITB inst hits
+system.cpu.itb.inst_misses                      11939                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -413,98 +428,98 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3096                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2163                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2177                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66252518                       # ITB inst accesses
-system.cpu.itb.hits                          66240582                       # DTB hits
-system.cpu.itb.misses                           11936                       # DTB misses
-system.cpu.itb.accesses                      66252518                       # DTB accesses
-system.cpu.numCycles                        260548868                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66305965                       # ITB inst accesses
+system.cpu.itb.hits                          66294026                       # DTB hits
+system.cpu.itb.misses                           11939                       # DTB misses
+system.cpu.itb.accesses                      66305965                       # DTB accesses
+system.cpu.numCycles                        260580731                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104909639                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184558460                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46964274                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33140298                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     145575332                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6162234                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     168611                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8187                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        338898                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       503455                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          112                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66240894                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1039458                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4991                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          254585351                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.884453                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.237226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104873538                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184739295                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46933448                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33114715                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     145635789                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6158762                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     168952                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8750                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        338958                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       503648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66294321                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1128854                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4994                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          254609122                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.884999                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.237560                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                155338707     61.02%     61.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29243843     11.49%     72.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14083345      5.53%     78.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55919456     21.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                155317216     61.00%     61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29235163     11.48%     72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14076452      5.53%     78.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55980291     21.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            254585351                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.180251                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.708345                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78108823                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             105363724                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64680632                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3828797                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2603375                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422156                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                485996                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157495015                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3691306                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2603375                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83949795                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10013130                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74489960                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62673363                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              20855728                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146845952                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                950144                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                437842                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  62734                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16405                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               18093439                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150530803                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678954009                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164472740                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10951                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141875467                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8655333                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2847772                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2651529                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13851116                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26418132                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21304063                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1686589                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2099460                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143580575                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2120859                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143376028                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            269119                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6250781                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14651223                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125281                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     254585351                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.563175                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.882138                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            254609122                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.180111                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.708952                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78085586                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             105431733                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64660886                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3829260                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2601657                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422216                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485978                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157447803                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3691485                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2601657                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83925210                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10033565                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74541150                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62655394                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              20852146                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146807646                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                950357                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                437123                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62766                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16447                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               18089237                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150492315                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678770164                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164434086                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10967                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141835122                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8657190                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2845976                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2649716                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13845319                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26411369                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21300781                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1686386                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2189128                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143541895                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2120957                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143337283                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            269192                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6251828                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14653372                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125306                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     254609122                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.562970                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.882443                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           166207835     65.29%     65.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45306594     17.80%     83.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31956972     12.55%     95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10300343      4.05%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              813574      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           166344309     65.33%     65.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45117660     17.72%     83.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32035421     12.58%     95.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10298180      4.04%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813519      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -512,9 +527,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       254585351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       254609122                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7371879     32.63%     32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7370311     32.63%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.63% # attempts to use FU when none available
@@ -543,13 +558,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5632028     24.93%     57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9586948     42.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5632420     24.93%     57.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9586874     42.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96038086     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113978      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              96009315     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113982      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -573,100 +588,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8590      0.01%     67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8594      0.01%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26200986     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21012051     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26194290     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21008765     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143376028                       # Type of FU issued
-system.cpu.iq.rate                           0.550285                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22590887                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157564                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          564161758                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         151957264                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140260479                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35655                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13185                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              143337283                       # Type of FU issued
+system.cpu.iq.rate                           0.550069                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22589637                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157598                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          564106761                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         151919680                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140223084                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35756                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13217                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11431                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165941227                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23351                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           324401                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165901147                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23436                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           324147                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1489874                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1490308                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          533                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18271                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       701002                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18251                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       701176                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87957                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6348                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88081                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6304                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2603375                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  948323                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                290944                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145902361                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2601657                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  950737                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                291154                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145863821                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26418132                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21304063                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096021                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17856                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                256072                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18271                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317509                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471618                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789127                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142433599                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25799978                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            872737                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26411369                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21300781                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096076                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17895                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                256263                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18251                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317548                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471732                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789280                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142394540                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25793108                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            873030                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200927                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46682549                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26544085                       # Number of branches executed
-system.cpu.iew.exec_stores                   20882571                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.546668                       # Inst execution rate
-system.cpu.iew.wb_sent                      142046516                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140271910                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63301578                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95887209                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200969                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46672402                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26533167                       # Number of branches executed
+system.cpu.iew.exec_stores                   20879294                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.546451                       # Inst execution rate
+system.cpu.iew.wb_sent                      142007306                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140234515                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63283849                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95860591                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.538371                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660167                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.538161                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660165                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7591975                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995578                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755003                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    251649065                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.546262                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.145555                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7591533                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995651                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755158                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    251674404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.546055                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.146686                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    178084267     70.77%     70.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43398054     17.25%     88.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15481884      6.15%     94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4357721      1.73%     95.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6462022      2.57%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1589357      0.63%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       777637      0.31%     99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       414343      0.16%     99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1083780      0.43%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    178222235     70.81%     70.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43294364     17.20%     88.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15476639      6.15%     94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4357303      1.73%     95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6369018      2.53%     98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1679088      0.67%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       777340      0.31%     99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       414271      0.16%     99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1084146      0.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    251649065                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113359701                       # Number of instructions committed
-system.cpu.commit.committedOps              137466321                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    251674404                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113328647                       # Number of instructions committed
+system.cpu.commit.committedOps              137428168                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45531319                       # Number of memory references committed
-system.cpu.commit.loads                      24928258                       # Number of loads committed
-system.cpu.commit.membars                      814674                       # Number of memory barriers committed
-system.cpu.commit.branches                   26060472                       # Number of branches committed
+system.cpu.commit.refs                       45520666                       # Number of memory references committed
+system.cpu.commit.loads                      24921061                       # Number of loads committed
+system.cpu.commit.membars                      814701                       # Number of memory barriers committed
+system.cpu.commit.branches                   26049415                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120282111                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4896381                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120247607                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4892692                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91813423     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91785919     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112990      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -691,43 +706,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8589      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8593      0.01%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24928258     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20603061     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24921061     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20599605     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137466321                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1083780                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         137428168                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1084146                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    373370450                       # The number of ROB reads
-system.cpu.rob.rob_writes                   293050441                       # The number of ROB writes
-system.cpu.timesIdled                          892831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5963517                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5393139836                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113204796                       # Number of Instructions Simulated
-system.cpu.committedOps                     137311416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.301571                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.301571                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.434486                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.434486                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155870535                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88662743                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9591                       # number of floating regfile reads
+system.cpu.rob.rob_reads                    373381031                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292971684                       # The number of ROB writes
+system.cpu.timesIdled                          892930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5971609                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5393503589                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113173742                       # Number of Instructions Simulated
+system.cpu.committedOps                     137273263                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.302484                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.302484                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.434314                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.434314                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155831391                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88636024                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9607                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 503158959                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53196475                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               444136009                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521560                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837744                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.958486                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40170152                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838256                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.921103                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 503020695                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53185327                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               444130548                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521619                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837995                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.958491                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40159583                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838507                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.894154                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         244924250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.958486                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.958491                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -735,170 +750,170 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          125
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179419983                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179419983                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23329792                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23329792                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15588565                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15588565                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346643                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346643                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441991                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441991                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460300                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460300                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38918357                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38918357                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39265000                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39265000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       700458                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        700458                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3573865                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3573865                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177072                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177072                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26735                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26735                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179379502                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179379502                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23322864                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23322864                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15584894                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15584894                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       346636                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        346636                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       442009                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       442009                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460310                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460310                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38907758                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38907758                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39254394                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39254394                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       700618                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        700618                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3574058                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3574058                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177109                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177109                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26740                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26740                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4274323                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4274323                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4451395                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4451395                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9897569146                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9897569146                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 135184782788                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    357043749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    357043749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        91502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        91502                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145082351934                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145082351934                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145082351934                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145082351934                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24030250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24030250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19162430                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19162430                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523715                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523715                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468726                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468726                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460305                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460305                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43192680                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43192680                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43716395                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43716395                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029149                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029149                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186504                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.186504                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338108                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.338108                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057038                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057038                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      4274676                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4274676                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4451785                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4451785                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9939142148                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9939142148                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 135148977049                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    356483749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    356483749                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       189500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       189500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145088119197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145088119197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145088119197                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145088119197                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24023482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24023482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19158952                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19158952                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523745                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523745                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468749                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468749                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460315                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460315                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43182434                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43182434                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43706179                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43706179                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029164                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029164                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186548                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.186548                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338159                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.338159                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057045                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057045                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.098959                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.098959                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.101824                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.101824                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33942.767529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32592.558498                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       504099                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.098991                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.098991                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.101857                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.101857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        37900                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        37900                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33941.313727                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32590.998711                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       505021                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6928                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6926                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.762558                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.916691                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695413                       # number of writebacks
-system.cpu.dcache.writebacks::total            695413                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286304                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       286304                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274603                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3274603                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18411                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18411                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3560907                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3560907                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3560907                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3560907                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414154                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414154                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299262                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299262                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119306                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119306                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8324                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8324                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       695574                       # number of writebacks
+system.cpu.dcache.writebacks::total            695574                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286297                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       286297                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274736                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3274736                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18417                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18417                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3561033                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3561033                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3561033                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3561033                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414321                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414321                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299322                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299322                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119334                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119334                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8323                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8323                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832722                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832722                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5341815166                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5341815166                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11883724205                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11883724205                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1479869001                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1479869001                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110184750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110184750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81498                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17225539371                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17225539371                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18705408372                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18705408372                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792724250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792724250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440459453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440459453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233183703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233183703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017235                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017235                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227807                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227807                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017759                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017759                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       713643                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       713643                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832977                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832977                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5358688665                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5358688665                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11888843709                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11888843709                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1476460251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1476460251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110246000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110246000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       179500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       179500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17247532374                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17247532374                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18723992625                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18723992625                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792718250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792718250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440457453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440457453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233175703                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233175703                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017247                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017247                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017756                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017756                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019048                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019048                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019059                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019059                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        35900                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        35900                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -906,13 +921,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1894031                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.373814                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64256441                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1894543                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.916591                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1894210                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.373832                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64309690                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1894722                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.941491                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       13186180250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.373814                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.373832                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -921,250 +936,250 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          170
 system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68132454                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68132454                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64256441                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64256441                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64256441                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64256441                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64256441                       # number of overall hits
-system.cpu.icache.overall_hits::total        64256441                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981452                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981452                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981452                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981452                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981452                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981452                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26762198879                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26762198879                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26762198879                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26762198879                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26762198879                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26762198879                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66237893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66237893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66237893                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66237893                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66237893                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66237893                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029914                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029914                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029914                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029914                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029914                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029914                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13506.357398                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13506.357398                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1929                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68186062                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68186062                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64309690                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64309690                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64309690                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64309690                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64309690                       # number of overall hits
+system.cpu.icache.overall_hits::total        64309690                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1981630                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1981630                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1981630                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1981630                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1981630                       # number of overall misses
+system.cpu.icache.overall_misses::total       1981630                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26770075875                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26770075875                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26770075875                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26770075875                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  26770075875                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26770075875                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66291320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66291320                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66291320                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66291320                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66291320                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66291320                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029893                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029893                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029893                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029893                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029893                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029893                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13509.119197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13509.119197                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1592                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               105                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               104                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    18.371429                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    15.307692                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86889                       # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894563                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1894563                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::cpu.inst      1894563                       # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total  22159944091                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22159944091                       # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211                       # average overall mshr miss latency
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 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            98619                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65077.788294                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3020947                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           163832                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.439298                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            98615                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65077.693225                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3021592                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218344                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798460                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5191.617940                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756264                       # Average percentage of cache occupancy
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
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 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75113.593108                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73076.528757                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 73433.597435                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1173,8 +1188,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        90626                       # number of writebacks
-system.cpu.l2cache.writebacks::total            90626                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        90628                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
@@ -1186,96 +1201,96 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data          112
 system.cpu.l2cache.overall_mshr_hits::total          137                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           19                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           19                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157877000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545351750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107339500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107339500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157877000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494823250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652700250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494814250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652691250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024938                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013381                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987712                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987712                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024922                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013377                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987004                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987004                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461650                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461650                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461548                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461548                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179469                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060898                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000353                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000600                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060884                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179469                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060898                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060884                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1285,59 +1300,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2564949                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2564884                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2565344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2565278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27608                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27608                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       695413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36229                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2767                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       695574                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2770                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2772                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296625                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495164                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31180                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128717                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6450154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121297808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98349473                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215428                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219909377                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       65488                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3561849                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.010233                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.100640                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296684                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296684                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795456                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495832                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31236                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128794                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6451318                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121309456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98375777                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215684                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219947773                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       65392                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3562462                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.010230                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.100625                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            3525400     98.98%     98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6              36449      1.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3526018     98.98%     98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6              36444      1.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3561849                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2502926529                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3562462                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2503396529                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2849434655                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2849706150                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1334430859                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1334755109                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19518240                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19527240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74882707                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74897454                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1428,42 +1444,44 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326556349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347066130                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36779263                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36776516                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                0.999676                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000725                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         251942463000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.999676                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062480                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062480                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         251942535000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000725                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062545                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062545                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
 system.iocache.tags.data_accesses              327996                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          220                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               220                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          220                       # number of overall misses
 system.iocache.overall_misses::total              220                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     26406377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     26406377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     26406377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     26406377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     26406377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     26406377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     26411377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     26411377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9622478237                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9622478237                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     26411377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     26411377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     26411377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     26411377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1474,104 +1492,114 @@ system.iocache.overall_accesses::realview.ide          220
 system.iocache.overall_accesses::total            220                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120028.986364                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120028.986364                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120028.986364                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120028.986364                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120028.986364                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120051.713636                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120051.713636                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120051.713636                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56749                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7275                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.800550                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          220                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          220                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          220                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          220                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          220                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          220                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     14965377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     14965377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2230292235                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2230292235                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     14965377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     14965377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     14965377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     14965377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     14970377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     14970377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     14970377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     14970377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     14970377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     14970377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68024.440909                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68024.440909                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               67834                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67833                       # Transaction distribution
+system.membus.trans_dist::ReadReq               67832                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67831                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
-system.membus.trans_dist::Writeback             90626                       # Transaction distribution
+system.membus.trans_dist::Writeback            126818                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4543                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4545                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135127                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135127                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135125                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135125                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452777                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560413                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72683                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72683                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 633096                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452492                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 669001                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16658216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16821681                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19140977                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              205                       # Total snoops (count)
-system.membus.snoop_fanout::samples            300222                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16640360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16803825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21439281                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              484                       # Total snoops (count)
+system.membus.snoop_fanout::samples            336405                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  300222    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  336405    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              300222                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            94200000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              336405                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            94190000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1697000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1357984749                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1678025205                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1683660499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1677935457                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38219737                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38220484                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1605,6 +1633,6 @@ system.realview.ethernet.coalescedTotal           nan                       # av
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3038                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                     3039                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index de918fa9c..053f94faa 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,156 +1,153 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.817967                       # Number of seconds simulated
-sim_ticks                                2817967230500                       # Number of ticks simulated
-final_tick                               2817967230500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.818075                       # Number of seconds simulated
+sim_ticks                                2818074786500                       # Number of ticks simulated
+final_tick                               2818074786500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 295085                       # Simulator instruction rate (inst/s)
-host_op_rate                                   358305                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6587585543                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 567284                       # Number of bytes of host memory used
-host_seconds                                   427.77                       # Real time elapsed on the host
-sim_insts                                   126228232                       # Number of instructions simulated
-sim_ops                                     153272049                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 252135                       # Simulator instruction rate (inst/s)
+host_op_rate                                   306151                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5631568448                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 564964                       # Number of bytes of host memory used
+host_seconds                                   500.41                       # Real time elapsed on the host
+sim_insts                                   126169808                       # Number of instructions simulated
+sim_ops                                     153199842                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           652964                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4386528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           666212                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4384416                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           130944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1051396                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         6080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           516736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          4232960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           128384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1037892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         6016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           504320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          4231744                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10978952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       652964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       130944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       516736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1300644                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5946048                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10960328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       666212                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       128384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       504320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1298916                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8261760                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8281908                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8279284                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             18656                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             69058                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             18863                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             69025                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2046                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16429                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           95                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              8074                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             66140                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2006                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16218                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           94                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              7880                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             66121                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180519                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           92907                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                180228                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          129090                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133512                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               133471                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            91                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              231715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1556628                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              236407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1555820                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               46468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              373104                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          2158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              183372                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1502132                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               45557                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              368298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker          2135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              178959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1501644                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3896054                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         231715                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          46468                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         183372                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             461554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2110049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3889296                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         236407                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          45557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         178959                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             460923                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2931704                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6216                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          822698                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2938965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2110049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2937922                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2931704                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           91                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             231715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1562844                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             236407                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1562035                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              46468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             373107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         2158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             183372                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1502132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          823039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6835019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         92786                       # Number of read requests accepted
-system.physmem.writeReqs                        67811                       # Number of write requests accepted
-system.physmem.readBursts                       92786                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      67811                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5933952                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      4352                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4338688                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5938244                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4339784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       68                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2462                       # Number of requests that are neither read nor write
+system.physmem.bw_total::cpu1.inst              45557                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             368301                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker         2135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             178959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1501644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6827218                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         92321                       # Number of read requests accepted
+system.physmem.writeReqs                        90302                       # Number of write requests accepted
+system.physmem.readBursts                       92321                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      90302                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5904000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      4544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5704128                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5908484                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5779208                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       71                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1152                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           2483                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                6041                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5815                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5576                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6089                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5555                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5469                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6176                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6795                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6466                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6395                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5737                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5121                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5306                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5463                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5326                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5388                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4259                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                3941                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4227                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4690                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4139                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4140                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4396                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4907                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4559                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4641                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4210                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3556                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4023                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4273                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3931                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3900                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5798                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5558                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6021                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5562                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5457                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6123                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6801                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6403                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6349                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5693                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5092                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5281                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5450                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5307                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5314                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5390                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4962                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5472                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5886                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5376                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5734                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5792                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6324                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6132                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6057                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5626                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4872                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5573                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5712                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5197                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5022                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2816401088000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2816508644000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       1                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   92785                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   92320                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  67809                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     61124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       516                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  90300                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     60706                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     28069                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       505                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,163 +183,182 @@ system.physmem.wrQLenPdf::4                        53                       # Wh
 system.physmem.wrQLenPdf::5                        51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       48                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       49                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       49                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4458                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     3504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        32876                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      312.458450                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.413676                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.664106                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12770     38.84%     38.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7721     23.49%     62.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2991      9.10%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1712      5.21%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1344      4.09%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          774      2.35%     83.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          537      1.63%     84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          552      1.68%     86.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4475     13.61%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          32876                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3255                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.482642                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      540.024143                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           3254     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3788                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4880                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        33954                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.872416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     193.139988                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     360.706061                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12607     37.13%     37.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7646     22.52%     59.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2942      8.66%     68.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1742      5.13%     73.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1359      4.00%     77.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          780      2.30%     79.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          533      1.57%     81.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          565      1.66%     82.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5780     17.02%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          33954                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3432                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.875583                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      525.946384                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3431     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3255                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3255                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.827035                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.877074                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.588559                       # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            3432                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.969406                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.900383                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       25.459060                       # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::0-3                 4      0.12%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.06%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               2      0.06%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            2714     83.38%     83.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              41      1.26%     84.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              32      0.98%     85.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             140      4.30%     90.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             131      4.02%     94.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               8      0.25%     94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               4      0.12%     94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.28%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              18      0.55%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.09%     95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               7      0.22%     95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.12%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              99      3.04%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.06%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.12%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.09%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.09%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.03%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.09%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.06%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.06%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.28%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.03%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.06%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3255                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1187084500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2925547000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    463590000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12803.17                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                3      0.09%      0.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               2      0.06%      0.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            2696     78.55%     78.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              29      0.84%     79.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              30      0.87%     80.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             138      4.02%     84.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              83      2.42%     87.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              30      0.87%     87.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              20      0.58%     88.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              23      0.67%     89.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              73      2.13%     91.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.20%     91.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.15%     91.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.23%     91.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              20      0.58%     92.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               8      0.23%     92.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.23%     92.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              21      0.61%     93.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              41      1.19%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               8      0.23%     94.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.09%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               9      0.26%     95.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              65      1.89%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.12%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             7      0.20%     97.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             5      0.15%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             7      0.20%     97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.09%     97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             8      0.23%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.09%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            22      0.64%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             7      0.20%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.06%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.06%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.06%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.09%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.03%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.09%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             5      0.15%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.09%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.06%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3432                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1184332750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2914020250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    461250000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12838.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31553.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.11                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.54                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31588.30                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.10                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.02                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.10                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      76742                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50891                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.77                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.05                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17537071.60                       # Average gap between requests
-system.physmem.pageHitRate                      79.51                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2704795503250                       # Time in different power states
-system.physmem.memoryStateTime::REF       94097900000                       # Time in different power states
+system.physmem.avgWrQLen                         8.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      76434                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     70988                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.86                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15422529.71                       # Average gap between requests
+system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2704815148250                       # Time in different power states
+system.physmem.memoryStateTime::REF       94101540000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       19068171250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       19154581250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 130016880                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 118525680                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  70941750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  64671750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                370624800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                352544400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               224849520                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               214442640                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184055492400                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184055492400                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           70844118390                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           70005569445                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1628632585500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1629368154750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1884328629240                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1884179401065                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.685154                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.632198                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 134477280                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 122214960                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                  73375500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                  66684750                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                369415800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                350110800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               291185280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               286357680                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          184062612240                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          184062612240                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           70840900170                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           70013903985                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1628700821250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1629426256500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1884472787520                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1884328140915                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.710440                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.659112                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -385,25 +401,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14476193                       # DTB read hits
-system.cpu0.dtb.read_misses                      4879                       # DTB read misses
-system.cpu0.dtb.write_hits                   11073999                       # DTB write hits
-system.cpu0.dtb.write_misses                      930                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         189                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14476474                       # DTB read hits
+system.cpu0.dtb.read_misses                      4869                       # DTB read misses
+system.cpu0.dtb.write_hits                   11056177                       # DTB write hits
+system.cpu0.dtb.write_misses                      893                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         188                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     401                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3272                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3212                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   946                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   944                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      215                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14481072                       # DTB read accesses
-system.cpu0.dtb.write_accesses               11074929                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      196                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14481343                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11057070                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         25550192                       # DTB hits
-system.cpu0.dtb.misses                           5809                       # DTB misses
-system.cpu0.dtb.accesses                     25556001                       # DTB accesses
+system.cpu0.dtb.hits                         25532651                       # DTB hits
+system.cpu0.dtb.misses                           5762                       # DTB misses
+system.cpu0.dtb.accesses                     25538413                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -425,366 +441,366 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    67954476                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2811                       # ITB inst misses
+system.cpu0.itb.inst_hits                    67995752                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2758                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         189                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         188                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     401                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2005                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1969                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                67957287                       # ITB inst accesses
-system.cpu0.itb.hits                         67954476                       # DTB hits
-system.cpu0.itb.misses                           2811                       # DTB misses
-system.cpu0.itb.accesses                     67957287                       # DTB accesses
-system.cpu0.numCycles                        82556827                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                67998510                       # ITB inst accesses
+system.cpu0.itb.hits                         67995752                       # DTB hits
+system.cpu0.itb.misses                           2758                       # DTB misses
+system.cpu0.itb.accesses                     67998510                       # DTB accesses
+system.cpu0.numCycles                        82558276                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   66160398                       # Number of instructions committed
-system.cpu0.committedOps                     80652664                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             70891762                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5582                       # Number of float alu accesses
-system.cpu0.num_func_calls                    7292056                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      8778747                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    70891762                       # number of integer instructions
-system.cpu0.num_fp_insts                         5582                       # number of float instructions
-system.cpu0.num_int_register_reads          131506051                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          49334508                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4358                       # number of times the floating registers were read
+system.cpu0.committedInsts                   66186941                       # Number of instructions committed
+system.cpu0.committedOps                     80639436                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             70858992                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5470                       # Number of float alu accesses
+system.cpu0.num_func_calls                    7266542                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      8791397                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    70858992                       # number of integer instructions
+system.cpu0.num_fp_insts                         5470                       # number of float instructions
+system.cpu0.num_int_register_reads          131380013                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          49295072                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4246                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1228                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           245869189                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           29383374                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     26220572                       # number of memory refs
-system.cpu0.num_load_insts                   14652138                       # Number of load instructions
-system.cpu0.num_store_insts                  11568434                       # Number of store instructions
-system.cpu0.num_idle_cycles              77950738.874403                       # Number of idle cycles
-system.cpu0.num_busy_cycles              4606088.125597                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055793                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944207                       # Percentage of idle cycles
-system.cpu0.Branches                         16465662                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           245776790                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           29457750                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     26204570                       # number of memory refs
+system.cpu0.num_load_insts                   14653679                       # Number of load instructions
+system.cpu0.num_store_insts                  11550891                       # Number of store instructions
+system.cpu0.num_idle_cycles              77949108.406676                       # Number of idle cycles
+system.cpu0.num_busy_cycles              4609167.593324                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055829                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944171                       # Percentage of idle cycles
+system.cpu0.Branches                         16455876                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2193      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 55785323     67.97%     67.97% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58705      0.07%     68.05% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4540      0.01%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.05% # Class of executed instruction
-system.cpu0.op_class::MemRead                14652138     17.85%     85.90% # Class of executed instruction
-system.cpu0.op_class::MemWrite               11568434     14.10%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 55779692     67.98%     67.99% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58849      0.07%     68.06% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4532      0.01%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.06% # Class of executed instruction
+system.cpu0.op_class::MemRead                14653679     17.86%     85.92% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11550891     14.08%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  82071333                       # Class of executed instruction
+system.cpu0.op_class::total                  82049836                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3056                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           833736                       # number of replacements
+system.cpu0.kern.inst.quiesce                    3055                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           833965                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.996800                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           47002068                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           834248                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            56.340642                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           46972085                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           834477                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            56.289251                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.853503                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.630840                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.512458                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.948933                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032482                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018579                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.818118                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.670897                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.507786                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.948864                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032560                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018570                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        198562219                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       198562219                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     13788602                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      4405053                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      8513889                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       26707544                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     10680609                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3155163                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      5163362                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18999134                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190594                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        60628                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       130484                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       381706                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       235265                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        80498                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       135390                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       451153                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236615                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        83018                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       140051                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459684                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     24469211                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      7560216                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     13677251                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        45706678                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     24659805                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      7620844                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     13807735                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       46088384                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       190267                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        59406                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       315886                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       565559                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       145430                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        33947                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data      1529690                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1709067                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        55022                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        20138                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data        65538                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       140698                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4446                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3285                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         9694                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17425                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        198452344                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       198452344                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     13787811                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      4397354                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      8501200                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       26686365                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     10663716                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      3166111                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      5160414                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18990241                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190628                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        60624                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data       130481                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       381733                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       235896                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        80331                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       134984                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       451211                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       237277                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        82832                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data       139583                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459692                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     24451527                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      7563465                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data     13661614                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        45676606                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     24642155                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      7624089                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data     13792095                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       46058339                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       191712                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        58922                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       315531                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       566165                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       143864                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        35394                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data      1531641                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1710899                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54000                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        21214                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data        65487                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       140701                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4460                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3296                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         9679                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        17435                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data           13                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           15                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       335697                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        93353                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1845576                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2274626                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       390719                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       113491                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1911114                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2415324                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    905367250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   5265516623                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6170883873                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1312551865                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  70768535678                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  72081087543                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     46450000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    132109998                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    178559998                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       181001                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       181001                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   2217919115                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  76034052301                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  78251971416                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   2217919115                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  76034052301                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  78251971416                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     13978869                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      4464459                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      8829775                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     27273103                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     10826039                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      3189110                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      6693052                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     20708201                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       245616                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        80766                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       196022                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       522404                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239711                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        83783                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       145084                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       468578                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236617                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        83018                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       140064                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459699                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     24804908                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      7653569                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     15522827                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     47981304                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     25050524                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      7734335                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     15718849                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     48503708                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013611                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013306                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035775                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.020737                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013433                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.010645                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.228549                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.082531                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224016                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.249338                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.334340                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.269328                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018547                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.039208                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066816                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.037187                       # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.demand_miss_latency::total  78174860385                       # number of demand (read+write) miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        81838                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::cpu1.data      7657781                       # number of demand (read+write) accesses
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013714                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013222                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035788                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020775                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013311                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011055                       # miss rate for WriteReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total     0.082648                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.220743                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.259219                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.334172                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.269318                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018556                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.039413                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066907                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.037203                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000093                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000033                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013533                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012197                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.118894                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.047407                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015597                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014674                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.121581                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.049797                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15240.333468                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16669.040803                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10911.123107                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38664.738121                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46263.318501                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 42175.694425                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.030441                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13628.017124                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10247.345653                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23758.412852                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41198.006639                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34402.126510                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19542.687217                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39785.199785                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32398.126055                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       376933                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        24988                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            25127                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            512                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.001114                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    48.804688                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000107                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000037                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013538                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012316                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.119105                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.047485                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015563                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014927                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.121789                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.049875                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056448                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16821.983748                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10963.981973                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37534.226479                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46119.783369                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 42064.106374                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14131.143811                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13679.124496                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10265.356811                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13800.066667                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12176.529412                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23623.265533                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41115.179568                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34331.428710                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19285.483528                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39707.448360                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 32333.523062                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       374153                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        25938                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            24753                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            535                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.115461                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    48.482243                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       692581                       # number of writebacks
-system.cpu0.dcache.writebacks::total           692581                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          108                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       154975                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       155083                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1409869                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1409869                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1934                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6806                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8740                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          108                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      1564844                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1564952                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          108                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      1564844                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1564952                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        59298                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       160911                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       220209                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        33947                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       119821                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       153768                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        19747                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43923                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        63670                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1351                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         2888                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4239                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           13                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        93245                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       280732                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       373977                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       112992                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       324655                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       437647                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    784144250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2133463687                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2917607937                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1238610119                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5440807950                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6679418069                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    253219750                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    658574506                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    911794256                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     21611000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     35862251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57473251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       154999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       154999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2022754369                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7574271637                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9597026006                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2275974119                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8232846143                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10508820262                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1018414500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1694074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2712488500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    777507500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1315307000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2092814500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1795922000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3009381000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4805303000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013282                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018224                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008074                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.010645                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017902                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007425                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.244496                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.224072                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.121879                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.016125                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.009047                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000093                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012183                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.018085                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.007794                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014609                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020654                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.009023                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13223.789167                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13258.656568                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13249.267455                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36486.585530                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45407.799551                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43438.284097                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.200993                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14993.841632                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14320.625978                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12417.676939                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13558.209719                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11923                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11923                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21692.899019                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26980.435565                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25662.075491                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20142.789923                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25358.753578                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24012.092536                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       692650                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692650                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          119                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       155404                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       155523                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1411618                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1411618                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1952                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6678                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8630                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          119                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      1567022                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1567141                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          119                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      1567022                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1567141                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        58803                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       160127                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       218930                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35394                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       120023                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       155417                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20830                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43721                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        64551                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1344                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3001                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4345                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           15                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           15                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        94197                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       280150                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       374347                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       115027                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       323871                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       438898                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    779470500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2130747955                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2910218455                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1251702570                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5436442471                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6688145041                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    266097500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    651596008                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    917693508                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     21534500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     37307002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     58841502                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       176999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       176999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2031173070                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7567190426                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9598363496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2297270570                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8218786434                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10516057004                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1018847500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1696409500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2715257000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    779636500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1318509000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2098145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1798484000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3014918500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4813402500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013196                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018162                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008033                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011055                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017935                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007508                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.254527                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.223103                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.123558                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.016071                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.020745                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.009271                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000107                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012301                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.018064                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.007806                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014862                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020622                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.009054                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13255.624713                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13306.612595                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13292.917622                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35364.823699                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45295.005716                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43033.548717                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12774.723956                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14903.501933                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14216.565320                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16022.693452                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12431.523492                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13542.347986                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11799.933333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11799.933333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21563.033536                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27011.209802                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25640.284271                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19971.576847                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25376.728494                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23960.138811                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -795,142 +811,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1798304                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.545340                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          100886115                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1798815                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            56.084764                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1798241                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.545331                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          100915026                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1798752                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            56.102801                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      10926866250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   477.674781                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    21.513239                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    12.357321                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.932959                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.042018                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.024135                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   477.669310                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    21.516745                       # Average occupied blocks per requestor
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 system.cpu0.icache.tags.occ_percent::total     0.999112                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
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-system.cpu0.icache.overall_avg_miss_latency::total  7270.895923                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         5362                       # number of cycles access was blocked
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+system.cpu0.icache.demand_avg_miss_latency::total  7250.778447                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total  7250.778447                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         5131                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              334                       # number of cycles access was blocked
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.053892                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.915698                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        50167                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        50167                       # number of ReadReq MSHR hits
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-system.cpu0.icache.demand_mshr_hits::total        50167                       # number of demand (read+write) MSHR hits
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-system.cpu0.icache.overall_mshr_miss_latency::total  11092578345                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011412                       # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009076                       # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::total     0.009076                       # mshr miss rate for demand accesses
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-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.053087                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009076                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11544.880172                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.118834                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.240788                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11544.880172                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.118834                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.240788                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11544.880172                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.118834                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.240788                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        50040                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        50040                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        50040                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        50040                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        50040                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        50040                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       248802                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       681413                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       930215                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       248802                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       681413                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       930215                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       248802                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       681413                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       930215                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2869743000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8188546795                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11058289795                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2869743000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8188546795                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11058289795                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2869743000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8188546795                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11058289795                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009052                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009052                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009052                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -955,25 +971,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4634797                       # DTB read hits
-system.cpu1.dtb.read_misses                      1583                       # DTB read misses
-system.cpu1.dtb.write_hits                    3276695                       # DTB write hits
-system.cpu1.dtb.write_misses                      231                       # DTB write misses
+system.cpu1.dtb.read_hits                     4627532                       # DTB read hits
+system.cpu1.dtb.read_misses                      1596                       # DTB read misses
+system.cpu1.dtb.write_hits                    3288935                       # DTB write hits
+system.cpu1.dtb.write_misses                      256                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         166                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     105                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     148                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1209                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1270                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   225                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   238                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       52                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4636380                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3276926                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       69                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 4629128                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3289191                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7911492                       # DTB hits
-system.cpu1.dtb.misses                           1814                       # DTB misses
-system.cpu1.dtb.accesses                      7913306                       # DTB accesses
+system.cpu1.dtb.hits                          7916467                       # DTB hits
+system.cpu1.dtb.misses                           1852                       # DTB misses
+system.cpu1.dtb.accesses                      7918319                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -995,98 +1011,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    21927829                       # ITB inst hits
-system.cpu1.itb.inst_misses                       850                       # ITB inst misses
+system.cpu1.itb.inst_hits                    21872882                       # ITB inst hits
+system.cpu1.itb.inst_misses                       825                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         166                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     105                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     148                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     702                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     668                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                21928679                       # ITB inst accesses
-system.cpu1.itb.hits                         21927829                       # DTB hits
-system.cpu1.itb.misses                            850                       # DTB misses
-system.cpu1.itb.accesses                     21928679                       # DTB accesses
-system.cpu1.numCycles                       158012697                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                21873707                       # ITB inst accesses
+system.cpu1.itb.hits                         21872882                       # DTB hits
+system.cpu1.itb.misses                            825                       # DTB misses
+system.cpu1.itb.accesses                     21873707                       # DTB accesses
+system.cpu1.numCycles                       158012156                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   21219424                       # Number of instructions committed
-system.cpu1.committedOps                     25417661                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22602393                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1642                       # Number of float alu accesses
-system.cpu1.num_func_calls                    2405355                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2700524                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22602393                       # number of integer instructions
-system.cpu1.num_fp_insts                         1642                       # number of float instructions
-system.cpu1.num_int_register_reads           41665364                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15857744                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1194                       # number of times the floating registers were read
+system.cpu1.committedInsts                   21172070                       # Number of instructions committed
+system.cpu1.committedOps                     25390672                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             22586857                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1738                       # Number of float alu accesses
+system.cpu1.num_func_calls                    2402647                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2689176                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    22586857                       # number of integer instructions
+system.cpu1.num_fp_insts                         1738                       # number of float instructions
+system.cpu1.num_int_register_reads           41666783                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          15854927                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1290                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                448                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            92377254                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            9370530                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      8126107                       # number of memory refs
-system.cpu1.num_load_insts                    4682037                       # Number of load instructions
-system.cpu1.num_store_insts                   3444070                       # Number of store instructions
-system.cpu1.num_idle_cycles              151526887.882406                       # Number of idle cycles
-system.cpu1.num_busy_cycles              6485809.117594                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.041046                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.958954                       # Percentage of idle cycles
-system.cpu1.Branches                          5257446                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   36      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 17987711     68.83%     68.83% # Class of executed instruction
-system.cpu1.op_class::IntMult                   19014      0.07%     68.90% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1154      0.00%     68.91% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.91% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.91% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.91% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4682037     17.92%     86.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3444070     13.18%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            92283936                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            9328431                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      8130215                       # number of memory refs
+system.cpu1.num_load_insts                    4674464                       # Number of load instructions
+system.cpu1.num_store_insts                   3455751                       # Number of store instructions
+system.cpu1.num_idle_cycles              151523865.450182                       # Number of idle cycles
+system.cpu1.num_busy_cycles              6488290.549818                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.041062                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.958938                       # Percentage of idle cycles
+system.cpu1.Branches                          5242761                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   34      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 17956106     68.78%     68.78% # Class of executed instruction
+system.cpu1.op_class::IntMult                   18827      0.07%     68.85% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.85% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1169      0.00%     68.86% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.86% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.86% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.86% # Class of executed instruction
+system.cpu1.op_class::MemRead                 4674464     17.91%     86.76% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3455751     13.24%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  26134022                       # Class of executed instruction
+system.cpu1.op_class::total                  26106351                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               17408373                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9463731                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           400017                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            10864152                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                8142904                       # Number of BTB hits
+system.cpu2.branchPred.lookups               17443399                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          9460519                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           398611                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            10920300                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                8161771                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            74.952044                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4071247                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21277                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            74.739439                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4093630                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             21092                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1110,25 +1126,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     9689518                       # DTB read hits
-system.cpu2.dtb.read_misses                     37575                       # DTB read misses
-system.cpu2.dtb.write_hits                    7159699                       # DTB write hits
-system.cpu2.dtb.write_misses                     5670                       # DTB write misses
-system.cpu2.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     370                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits                     9671030                       # DTB read hits
+system.cpu2.dtb.read_misses                     37752                       # DTB read misses
+system.cpu2.dtb.write_hits                    7157940                       # DTB write hits
+system.cpu2.dtb.write_misses                     5738                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva                     368                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2438                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.flush_entries                    2464                       # Number of entries that have been flushed from TLB
 system.cpu2.dtb.align_faults                      439                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   968                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.prefetch_faults                   949                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      417                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 9727093                       # DTB read accesses
-system.cpu2.dtb.write_accesses                7165369                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      419                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 9708782                       # DTB read accesses
+system.cpu2.dtb.write_accesses                7163678                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         16849217                       # DTB hits
-system.cpu2.dtb.misses                          43245                       # DTB misses
-system.cpu2.dtb.accesses                     16892462                       # DTB accesses
+system.cpu2.dtb.hits                         16828970                       # DTB hits
+system.cpu2.dtb.misses                          43490                       # DTB misses
+system.cpu2.dtb.accesses                     16872460                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1150,335 +1166,334 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                    12852348                       # ITB inst hits
-system.cpu2.itb.inst_misses                      6327                       # ITB inst misses
+system.cpu2.itb.inst_hits                    12894617                       # ITB inst hits
+system.cpu2.itb.inst_misses                      6298                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     370                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva                     368                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1763                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                    1799                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1147                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1027                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                12858675                       # ITB inst accesses
-system.cpu2.itb.hits                         12852348                       # DTB hits
-system.cpu2.itb.misses                           6327                       # DTB misses
-system.cpu2.itb.accesses                     12858675                       # DTB accesses
-system.cpu2.numCycles                        69828422                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                12900915                       # ITB inst accesses
+system.cpu2.itb.hits                         12894617                       # DTB hits
+system.cpu2.itb.misses                           6298                       # DTB misses
+system.cpu2.itb.accesses                     12900915                       # DTB accesses
+system.cpu2.numCycles                        69897742                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          26736882                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      69116574                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   17408373                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          12214151                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     39634943                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                2070237                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     91943                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                 882                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              273                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       329325                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       101475                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          454                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 12850788                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               270289                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2773                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          67931271                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.222867                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.347613                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          26768356                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      69154350                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   17443399                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          12255401                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     39728052                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                2075674                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     91833                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                 964                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              303                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       279943                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       102540                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          510                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 12893196                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               269600                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2749                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          68010313                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.222372                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.345734                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                49354668     72.65%     72.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                 2396025      3.53%     76.18% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                 1561758      2.30%     78.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4875455      7.18%     85.66% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                 1102436      1.62%     87.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  704861      1.04%     88.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 3873045      5.70%     94.02% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  751493      1.11%     95.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 3311530      4.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                49396667     72.63%     72.63% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                 2406815      3.54%     76.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                 1558633      2.29%     78.46% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4908408      7.22%     85.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                 1099721      1.62%     87.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  702073      1.03%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 3889062      5.72%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  750470      1.10%     95.15% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 3298464      4.85%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            67931271                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.249302                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.989806                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                18645308                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             36894831                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 10382963                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1080745                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                927203                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved             1311099                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred               109436                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              59339671                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               354865                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                927203                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                19270411                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4356096                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      27085706                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 10825258                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              5466363                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              56871138                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 2407                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                944494                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                157128                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               3862497                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           58808456                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            261172418                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        63777133                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             4183                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             48694532                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10113908                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            954202                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        890607                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  6274956                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            10279229                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            7930666                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          1385426                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores         1931872                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  54639620                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             672070                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 52007794                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            68359                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7304876                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     18433205                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         69298                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     67931271                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.765594                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.467899                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            68010313                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.249556                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.989365                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                18657683                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             36955851                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 10391299                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1075131                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                930120                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved             1306172                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred               109269                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              59268734                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               353681                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                930120                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                19279637                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4349454                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      27177493                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 10831041                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5442328                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              56795330                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2300                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                936981                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                152434                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               3851730                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           58689966                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            260889069                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        63678439                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             4318                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             48634410                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10055540                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            957404                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        893614                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  6253924                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            10259989                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            7928891                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          1377694                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores         1916931                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  54575287                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             669934                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 51950842                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            68646                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7267604                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     18361034                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         68925                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     68010313                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.763867                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.465859                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           47467453     69.88%     69.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6844404     10.08%     79.95% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            5089744      7.49%     87.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4188713      6.17%     93.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1618102      2.38%     95.99% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1074322      1.58%     97.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            1126267      1.66%     99.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             361985      0.53%     99.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             160281      0.24%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           47556715     69.93%     69.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            6835010     10.05%     79.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            5099948      7.50%     87.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4195226      6.17%     93.64% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1610331      2.37%     96.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1069065      1.57%     97.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            1123688      1.65%     99.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             361159      0.53%     99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             159171      0.23%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       67931271                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       68010313                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  78971      9.77%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                376071     46.54%     56.32% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               352950     43.68%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  78624      9.78%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.78% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                373360     46.42%     56.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               352326     43.80%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass              108      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             34454774     66.25%     66.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               39220      0.08%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   1      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc          2865      0.01%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             9972711     19.18%     85.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            7538110     14.49%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass              110      0.00%      0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             34419657     66.25%     66.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               39271      0.08%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  2      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc          2864      0.01%     66.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             9952470     19.16%     85.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            7536463     14.51%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              52007794                       # Type of FU issued
-system.cpu2.iq.rate                          0.744794                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     807993                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.015536                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         172813810                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         62649489                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     50408450                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               9401                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              4928                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         4143                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              52810613                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   5066                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          267388                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              51950842                       # Type of FU issued
+system.cpu2.iq.rate                          0.743241                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     804311                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.015482                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         172775366                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         62545429                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     50354259                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               9588                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              5092                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         4209                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              52749857                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   5186                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          265342                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1612297                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1915                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation        38614                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       794248                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1601303                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1888                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation        38444                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       793651                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       131416                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       121570                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       130825                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       118759                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                927203                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3248790                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               940039                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           55419045                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            93730                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             10279229                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             7930666                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            359745                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 34744                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               896292                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents         38614                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        184316                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       163000                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              347316                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             51571999                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              9796032                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           392652                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                930120                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3238109                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               943841                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           55348166                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            92957                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             10259989                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             7928891                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            358502                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 33985                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               900757                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents         38444                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        183146                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       162363                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              345509                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             51516440                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              9776464                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           391010                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                       107355                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    17260233                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 9488063                       # Number of branches executed
-system.cpu2.iew.exec_stores                   7464201                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.738553                       # Inst execution rate
-system.cpu2.iew.wb_sent                      51114762                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     50412593                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 26484469                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 46017701                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                       102945                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    17239257                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 9485344                       # Number of branches executed
+system.cpu2.iew.exec_stores                   7462793                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.737026                       # Inst execution rate
+system.cpu2.iew.wb_sent                      51063802                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     50358468                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 26440569                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 45930116                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.721949                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.575528                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.720459                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.575670                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        8145270                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         602772                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           292077                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     66207003                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.713906                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.618708                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8108589                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         601009                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           290869                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     66287251                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.712520                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.616760                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     48127722     72.69%     72.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      8087932     12.22%     84.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      3990373      6.03%     90.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      1725495      2.61%     93.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       876020      1.32%     94.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       623327      0.94%     95.81% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      1254839      1.90%     97.70% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       299711      0.45%     98.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1221584      1.85%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     48204047     72.72%     72.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      8094433     12.21%     84.93% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      3998554      6.03%     90.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      1723968      2.60%     93.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       875669      1.32%     94.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       615346      0.93%     95.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      1257319      1.90%     97.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       299111      0.45%     98.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1218804      1.84%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     66207003                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            38912247                       # Number of instructions committed
-system.cpu2.commit.committedOps              47265561                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     66287251                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            38872037                       # Number of instructions committed
+system.cpu2.commit.committedOps              47230974                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                      15803350                       # Number of memory references committed
-system.cpu2.commit.loads                      8666932                       # Number of loads committed
-system.cpu2.commit.membars                     226535                       # Number of memory barriers committed
-system.cpu2.commit.branches                   8911403                       # Number of branches committed
-system.cpu2.commit.fp_insts                      4112                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 41364475                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             1635441                       # Number of function calls committed.
+system.cpu2.commit.refs                      15793926                       # Number of memory references committed
+system.cpu2.commit.loads                      8658686                       # Number of loads committed
+system.cpu2.commit.membars                     225734                       # Number of memory barriers committed
+system.cpu2.commit.branches                   8913791                       # Number of branches committed
+system.cpu2.commit.fp_insts                      4128                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 41344274                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             1642310                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        31421440     66.48%     66.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          37906      0.08%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc         2865      0.01%     66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        31396236     66.47%     66.47% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          37948      0.08%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc         2864      0.01%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        8666932     18.34%     84.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       7136418     15.10%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        8658686     18.33%     84.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       7135240     15.11%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         47265561                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1221584                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         47230974                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1218804                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   113032454                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  112549271                       # The number of ROB writes
-system.cpu2.timesIdled                         280538                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1897151                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  5250079706                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   38848410                       # Number of Instructions Simulated
-system.cpu2.committedOps                     47201724                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.797459                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.797459                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.556341                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.556341                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                56460891                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               31949429                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    15783                       # number of floating regfile reads
+system.cpu2.rob.rob_reads                   112988408                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  112405622                       # The number of ROB writes
+system.cpu2.timesIdled                         280375                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1887429                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  5250225403                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   38810797                       # Number of Instructions Simulated
+system.cpu2.committedOps                     47169734                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.800987                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.800987                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.555251                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.555251                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                56393520                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               31926452                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    15872                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   13692                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                182431289                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                19284860                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads              124219174                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                483131                       # number of misc regfile writes
+system.cpu2.cc_regfile_reads                182232541                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                19215539                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads              124355307                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                481535                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30188                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30188                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              45563                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            9                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        13456                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59019                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22795                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54174                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1551,7 +1566,7 @@ system.iobus.reqLayer19.occupancy                2000                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             2719000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             2807000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy                1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -1559,387 +1574,395 @@ system.iobus.reqLayer25.occupancy            15730000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               25000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           205242577                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           217719639                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            39802000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            39873000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            23020273                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            22974011                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse                0.992769                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.993341                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         245004243009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.992769                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062048                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062048                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.993341                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062084                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062084                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328356                       # Number of tag accesses
-system.iocache.tags.data_accesses              328356                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
+system.iocache.tags.data_accesses              328284                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide            9                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total            9                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     14192930                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     14192930                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     14192930                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     14192930                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     14192930                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     14192930                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     14419928                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     14419928                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6029712700                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   6029712700                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     14419928                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     14419928                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     14419928                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     14419928                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36233                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36233                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000248                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000248                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 56321.150794                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 56321.150794                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 56321.150794                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 56321.150794                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 56321.150794                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 57221.936508                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 57221.936508                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 57221.936508                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 57221.936508                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 57221.936508                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34890                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 4513                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.730999                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::realview.ide          125                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          125                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          125                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          125                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          125                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          125                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide      7692930                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      7692930                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   1401235920                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1401235920                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide      7692930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      7692930                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide      7692930                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      7692930                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.496032                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.496032                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.496032                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.496032                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 61543.440000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 61543.440000                       # average overall mshr miss latency
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          127                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        22720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        22720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          127                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          127                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          127                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          127                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide      7815928                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      7815928                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4848250722                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4848250722                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide      7815928                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      7815928                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide      7815928                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      7815928                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.503968                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.627208                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.627208                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.503968                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.503968                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 61542.740157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 61542.740157                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   100842                       # number of replacements
-system.l2c.tags.tagsinuse                65118.786988                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2894514                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166082                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    17.428222                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   100831                       # number of replacements
+system.l2c.tags.tagsinuse                65118.744874                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2894730                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   166072                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    17.430572                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49797.172619                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939323                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   49795.493403                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939326                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5291.834831                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2854.505423                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969196                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1121.422857                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      949.240769                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    58.966175                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     3505.217048                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1537.518652                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.759845                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     5292.397633                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2853.974292                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969197                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1121.420686                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      949.232304                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    58.100226                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     3505.367496                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     1539.850216                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.759819                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000030                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.080747                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.043556                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.043548                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.inst       0.017112                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.014484                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000900                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.053485                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.023461                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993634                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65193                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           47                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000887                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.053488                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.023496                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1023           45                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           45                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3121                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8094                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53637                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000717                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994766                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27443398                       # Number of tag accesses
-system.l2c.tags.data_accesses                27443398                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4964                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2546                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             856761                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             242820                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         1454                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker          747                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             248185                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              77821                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        27355                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         6441                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             674046                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             203120                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2346260                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          692581                       # number of Writeback hits
-system.l2c.Writeback_hits::total               692581                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
+system.l2c.tags.age_task_id_blocks_1024::2         3290                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7951                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53614                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000687                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 27445059                       # Number of tag accesses
+system.l2c.tags.data_accesses                27445059                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         5016                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         2571                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             858721                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             243218                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         1379                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker          679                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             246795                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              78418                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        27414                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         6412                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             673438                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             202274                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2346335                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          692650                       # number of Writeback hits
+system.l2c.Writeback_hits::total               692650                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data               9                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data               5                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu2.data              41                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  55                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data            12                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            81743                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            19467                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            56360                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               157570                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4964                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          2546                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              856761                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              324563                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          1454                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker           747                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              248185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               97288                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         27355                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker          6441                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              674046                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              259480                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2503830                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4964                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         2546                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             856761                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             324563                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         1454                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker          747                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             248185                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              97288                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        27355                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker         6441                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             674046                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             259480                       # number of overall hits
-system.l2c.overall_hits::total                2503830                       # number of overall hits
+system.l2c.SCUpgradeReq_hits::cpu2.data            14                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                14                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            80155                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            20967                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            56516                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               157638                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5016                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          2571                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              858721                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              323373                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          1379                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker           679                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              246795                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               99385                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         27414                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          6412                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              673438                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              258790                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2503973                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5016                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         2571                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             858721                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             323373                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         1379                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker          679                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             246795                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              99385                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        27414                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         6412                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             673438                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             258790                       # number of overall hits
+system.l2c.overall_hits::total                2503973                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
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+system.l2c.overall_accesses::cpu2.inst         681326                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         325771                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2676773                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000797                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000389                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.011336                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.027797                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.data      0.031602                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003417                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.011577                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.014247                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992707                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988532                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.962761                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.980152                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.076923                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.432876                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.420176                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.525318                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.468463                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000805                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000393                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.011125                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.175966                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.064564                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000805                       # miss rate for overall accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72565.493646                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   307.317669                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   128.813029                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70491.776848                       # average ReadExReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72565.493646                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 71159.632898                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1948,142 +1971,142 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               92907                       # number of writebacks
-system.l2c.writebacks::total                    92907                       # number of writebacks
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-system.l2c.overall_mshr_hits::total                50                       # number of overall MSHR hits
+system.l2c.writebacks::writebacks               92900                       # number of writebacks
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
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 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    813978004                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   3894067274                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4708045278                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    808211990                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   3890249251                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4698461241                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    122615000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    974422504                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      6163250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    514015500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   4202615270                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5819894024                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    119268500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    969137740                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      6087000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    507884250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   4202773246                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5805213236                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    122615000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    974422504                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      6163250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    514015500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   4202615270                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5819894024                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    943135000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1581115000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2524250000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    723317000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1233415500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1956732500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1666452000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2814530500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4480982500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000687                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.008176                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.032029                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003461                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011838                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021867                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.007283                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.989276                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.962896                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.516955                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.076923                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.066667                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.420176                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.525318                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.257990                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000687                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008176                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.146372                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003461                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011838                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.204982                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035049                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000687                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008176                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.146372                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003461                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011838                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.204982                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035049                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst    119268500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    969137740                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      6087000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    507884250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   4202773246                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5805213236                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    943538500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1583240500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2526779000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    725279500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1236367500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1961647000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1668818000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2819608000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4488426000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000725                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.008063                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031602                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003417                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011570                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021829                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.007166                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.988532                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.962761                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.538073                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.066667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.058824                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.400223                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.524832                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.257697                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008063                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.142752                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003417                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011570                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.205476                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034920                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008063                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.142752                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003417                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011570                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.205476                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034920                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59929.130010                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62308.543689                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63655.170279                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67932.187583                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64142.652936                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62886.186010                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69219.046512                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64881.697444                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.169173                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.838102                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10002.886792                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.341382                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57700.290919                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62432.939043                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61559.974346                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57766.563505                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62320.767201                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59929.130010                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58411.611557                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63655.170279                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62806.217981                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62037.180604                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58558.171601                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62786.059428                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 62106.440817                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59929.130010                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58411.611557                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63655.170279                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62806.217981                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62037.180604                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58558.171601                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62786.059428                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 62106.440817                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2094,55 +2117,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74258                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74257                       # Transaction distribution
+system.membus.trans_dist::ReadReq               74228                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27571                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27571                       # Transaction distribution
-system.membus.trans_dist::Writeback             92907                       # Transaction distribution
+system.membus.trans_dist::Writeback            129090                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4549                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4545                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4552                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137040                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137040                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4548                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137060                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137060                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105462                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       471782                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       579244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72827                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72827                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 652071                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       471586                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       579048                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109015                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109015                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 688063                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159119                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16941564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17104683                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2326464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2326464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19431147                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              125                       # Total snoops (count)
-system.membus.snoop_fanout::samples            304876                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16930172                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17093291                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4642496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4642496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21735787                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              288                       # Total snoops (count)
+system.membus.snoop_fanout::samples            341037                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  304876    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  341037    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              304876                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40704500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              341037                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40803000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              459000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              460500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           735607750                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           937458500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          907107038                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          904148767                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           23918727                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           23873989                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2175,54 +2198,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2443155                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2443152                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2443122                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2443118                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27571                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27571                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           692581                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        22776                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2772                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            15                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2787                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296442                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296442                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3615657                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2484160                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        29265                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        88229                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6217311                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115156920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97909811                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        49244                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       155812                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              213271787                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           51771                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3431211                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.010633                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.102567                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback           692650                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        22720                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2771                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            17                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2788                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296527                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296527                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3615529                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2484690                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28930                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        88144                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6217293                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115152760                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97928947                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        48448                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       155392                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              213285547                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           51952                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3431323                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.010630                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.102554                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3394727     98.94%     98.94% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                  36484      1.06%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3394847     98.94%     98.94% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                  36476      1.06%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3431211                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2367804213                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3431323                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2376326693                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           553500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           558000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4198919632                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4188826435                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2015022352                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2020844355                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11862428                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11830425                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          39524153                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          39636892                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index b052ee538..3bffe858b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,142 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.804324                       # Number of seconds simulated
-sim_ticks                                2804324203000                       # Number of ticks simulated
-final_tick                               2804324203000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.814521                       # Number of seconds simulated
+sim_ticks                                2814521286500                       # Number of ticks simulated
+final_tick                               2814521286500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110825                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134512                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2657187313                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 623780                       # Number of bytes of host memory used
-host_seconds                                  1055.37                       # Real time elapsed on the host
-sim_insts                                   116961789                       # Number of instructions simulated
-sim_ops                                     141959973                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 106354                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2558515098                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 570360                       # Number of bytes of host memory used
+host_seconds                                  1100.06                       # Real time elapsed on the host
+sim_insts                                   116996192                       # Number of instructions simulated
+sim_ops                                     142001364                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker         4288                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           739200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5181280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           637568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4639684                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           746368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5095008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           629952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4708740                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11207460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       739200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       637568                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1376768                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6111936                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11189732                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       746368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       629952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1376320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8426816                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8447796                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8444340                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker           67                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             11550                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             81476                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           69                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9962                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             72496                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             11662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             80128                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           68                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9843                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             73575                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175636                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           95499                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175359                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131669                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136104                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1529                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136050                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1524                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              263593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1847604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1575                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              227352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1654475                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3996492                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         263593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         227352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             490945                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2179468                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              265185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1810257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1546                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              223822                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1673016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3975714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         265185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         223822                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             489007                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2994049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6223                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          826700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3012418                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2179468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3000276                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2994049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1524                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             263593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1853850                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1575                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             227352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1654478                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          827043                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7008910                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175637                       # Number of read requests accepted
-system.physmem.writeReqs                       136104                       # Number of write requests accepted
-system.physmem.readBursts                      175637                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136104                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11232064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8461376                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11207524                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8447796                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3870                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4652                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11117                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11147                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11719                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11225                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11363                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11390                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11955                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11820                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10213                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10442                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10593                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             265185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1816481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             223822                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1673019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6975990                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175360                       # Number of read requests accepted
+system.physmem.writeReqs                       172246                       # Number of write requests accepted
+system.physmem.readBursts                      175360                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     172246                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11215872                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10651968                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11189796                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10760884                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5779                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4663                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11102                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11119                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11680                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11222                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11370                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11380                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11917                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11794                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10207                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10426                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10580                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9765                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10406                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11413                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10638                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10295                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8316                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8444                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9040                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8545                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8340                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8537                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8974                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8818                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7762                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7809                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7936                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7396                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7882                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8742                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8045                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7623                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10349                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11405                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10639                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10293                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10392                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10480                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10999                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10520                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10645                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10713                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11169                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10762                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9958                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10000                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9968                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9745                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10100                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10962                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10229                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9795                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2804324017000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2814521100500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  175082                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174805                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131723                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    104376                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8495                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1509                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 167865                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    104183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61033                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1495                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -165,195 +162,218 @@ system.physmem.rdQLenPdf::29                        0                       # Wh
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                       107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2032                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::14                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3840                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9336                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11872                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26                    10729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    10200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      442                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36                      341                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::38                      280                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42                      240                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::46                      157                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64783                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.989874                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.723316                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.460023                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24407     37.68%     37.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15776     24.35%     62.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6538     10.09%     72.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3738      5.77%     77.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2814      4.34%     82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1507      2.33%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1107      1.71%     86.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1104      1.70%     87.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7792     12.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64783                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6707                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.165350                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      477.307058                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6704     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::50                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      325.854595                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.388710                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     345.406571                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24509     36.52%     36.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15902     23.70%     60.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6498      9.68%     69.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3742      5.58%     75.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2828      4.21%     79.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1529      2.28%     81.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1119      1.67%     83.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1119      1.67%     85.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9863     14.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67109                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7131                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.571869                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      462.936248                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7128     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6707                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6707                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.712092                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.230918                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.181787                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.10%      0.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                4      0.06%      0.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               9      0.13%      0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5755     85.81%     86.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             109      1.63%     87.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              46      0.69%     88.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             238      3.55%     92.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             224      3.34%     95.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              22      0.33%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              23      0.34%     96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.10%     96.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              31      0.46%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.03%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.12%     96.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             152      2.27%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.04%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               5      0.07%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              12      0.18%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              13      0.19%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.06%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.06%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.07%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6707                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2727699250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6018343000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    877505000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15542.36                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7131                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7131                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.339924                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.576956                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.763951                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                15      0.21%      0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.10%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                3      0.04%      0.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               7      0.10%      0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5889     82.58%     83.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             114      1.60%     84.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              53      0.74%     85.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             224      3.14%     88.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             142      1.99%     90.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              54      0.76%     91.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              26      0.36%     91.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              40      0.56%     92.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             124      1.74%     93.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.15%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              11      0.15%     94.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.15%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              24      0.34%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              13      0.18%     94.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              13      0.18%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              32      0.45%     95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              59      0.83%     96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               9      0.13%     96.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.08%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               9      0.13%     96.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              92      1.29%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.07%     98.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             8      0.11%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             4      0.06%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            17      0.24%     98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            14      0.20%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            38      0.53%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             9      0.13%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.06%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.13%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.04%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             7      0.10%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             3      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7131                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2737638250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6023538250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    876240000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15621.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34292.36                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.01                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34371.51                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.63                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.66                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145124                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97802                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.69                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.96                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8995685.58                       # Average gap between requests
-system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2678459999250                       # Time in different power states
-system.physmem.memoryStateTime::REF       93642380000                       # Time in different power states
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        11.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144870                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    129705                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.92                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8096871.46                       # Average gap between requests
+system.physmem.pageHitRate                      80.35                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2688100208500                       # Time in different power states
+system.physmem.memoryStateTime::REF       93982980000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       32221812750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       32438087000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 259096320                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 230663160                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 141372000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 125857875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                715533000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                653367000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               447210720                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               409503600                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          183164495280                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          183164495280                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           77871628440                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           76866307470                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1614283197000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1615165057500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1876882532760                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1876615251885                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.282725                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.187414                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 267820560                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 239523480                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 146132250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 130692375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                714347400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                652579200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               555206400                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               523305360                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          183830708880                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          183830708880                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           78196283910                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           77193580095                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1620118404000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1620997968750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1883828903400                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1883568358140                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.325253                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.232681                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::total          640                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu0.inst           10                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             10                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          228                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              228                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          228                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          228                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          228                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             228                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst          227                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              227                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          227                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          227                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          227                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             227                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               27347795                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14227638                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           549324                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            17049849                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12874628                       # Number of BTB hits
+system.cpu0.branchPred.lookups               27454524                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14302225                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           560028                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            17144432                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12924274                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            75.511683                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6769747                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             30174                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            75.384673                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6779174                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             30579                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -378,25 +398,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14276180                       # DTB read hits
-system.cpu0.dtb.read_misses                     49315                       # DTB read misses
-system.cpu0.dtb.write_hits                   10339289                       # DTB write hits
-system.cpu0.dtb.write_misses                     7532                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     475                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14369333                       # DTB read hits
+system.cpu0.dtb.read_misses                     50679                       # DTB read misses
+system.cpu0.dtb.write_hits                   10383293                       # DTB write hits
+system.cpu0.dtb.write_misses                     7631                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3434                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1022                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1284                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3537                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1074                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1312                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      561                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14325495                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10346821                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      596                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14420012                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10390924                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24615469                       # DTB hits
-system.cpu0.dtb.misses                          56847                       # DTB misses
-system.cpu0.dtb.accesses                     24672316                       # DTB accesses
+system.cpu0.dtb.hits                         24752626                       # DTB hits
+system.cpu0.dtb.misses                          58310                       # DTB misses
+system.cpu0.dtb.accesses                     24810936                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -418,158 +438,158 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    20541420                       # ITB inst hits
-system.cpu0.itb.inst_misses                      9178                       # ITB inst misses
+system.cpu0.itb.inst_hits                    20633477                       # ITB inst hits
+system.cpu0.itb.inst_misses                      8891                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     475                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2315                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2375                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1446                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1486                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20550598                       # ITB inst accesses
-system.cpu0.itb.hits                         20541420                       # DTB hits
-system.cpu0.itb.misses                           9178                       # DTB misses
-system.cpu0.itb.accesses                     20550598                       # DTB accesses
-system.cpu0.numCycles                       107861472                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20642368                       # ITB inst accesses
+system.cpu0.itb.hits                         20633477                       # DTB hits
+system.cpu0.itb.misses                           8891                       # DTB misses
+system.cpu0.itb.accesses                     20642368                       # DTB accesses
+system.cpu0.numCycles                       108176623                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          40570754                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     105629295                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   27347795                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19644375                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     61853082                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3245677                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    138610                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                7043                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              456                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       740654                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       142990                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          184                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20540168                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               376427                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3608                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         105076575                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.207830                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.305137                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          40839610                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     106163283                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   27454524                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19703448                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     62043143                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3268003                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    133218                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                6760                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              444                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       566983                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       143911                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          303                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20632158                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               383201                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3475                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         105368337                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.210422                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.308267                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                75967097     72.30%     72.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3896975      3.71%     76.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2393426      2.28%     78.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 8192788      7.80%     86.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1656267      1.58%     87.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1057275      1.01%     88.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6246218      5.94%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1068490      1.02%     95.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4598039      4.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                76140836     72.26%     72.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3909718      3.71%     75.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2409828      2.29%     78.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 8201309      7.78%     86.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1666024      1.58%     87.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1066995      1.01%     88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6252269      5.93%     94.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1076692      1.02%     95.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4644666      4.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           105076575                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.253546                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.979305                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                27994294                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58319975                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15794569                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1493949                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1473513                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1905038                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               151409                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              87407414                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               488746                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1473513                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                28854924                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                7818064                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      44554229                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16415102                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              5960455                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              83576128                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 2157                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1234281                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                240945                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               3763501                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           86207701                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            384903383                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        93172990                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5580                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             72433922                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                13773763                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1548068                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1453832                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8905153                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            15025647                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11465948                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1963626                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2709003                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  80419048                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1054429                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 77104069                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            91403                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10038631                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     24749704                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        115176                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    105076575                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.733789                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.427784                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           105368337                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.253794                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.981388                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                28207041                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             58279935                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15901267                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1497528                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1482288                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1929977                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               153844                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              87989191                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               497994                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1482288                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                29073693                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                7845343                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      44593101                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16518954                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              5854664                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              84134111                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 3122                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1216605                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                229511                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               3673419                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           86811691                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            387318144                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        93734921                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6132                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72788537                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                14023138                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1551068                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1456111                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8913232                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            15130036                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11520954                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1958410                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2751427                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  80936298                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1061855                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 77564111                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            93737                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10215309                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     25112322                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        116543                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    105368337                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.736124                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.430465                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           74341292     70.75%     70.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10185363      9.69%     80.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7872852      7.49%     87.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6575632      6.26%     94.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2323435      2.21%     96.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1484934      1.41%     97.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1562160      1.49%     99.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             492520      0.47%     99.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             238387      0.23%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           74478008     70.68%     70.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10230371      9.71%     80.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7904463      7.50%     87.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6602787      6.27%     94.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2340926      2.22%     96.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1499410      1.42%     97.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1574332      1.49%     99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             494613      0.47%     99.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             243427      0.23%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      105076575                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      105368337                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 112989      9.93%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     4      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                531745     46.73%     56.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               493078     43.34%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 114999     10.01%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     3      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                537121     46.77%     56.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               496300     43.22%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2199      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             51434902     66.71%     66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57707      0.07%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2212      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             51748002     66.72%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57664      0.07%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.79% # Type of FU issued
@@ -579,7 +599,7 @@ system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.79% # Ty
 system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   2      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdMisc                  1      0.00%     66.79% # Type of FU issued
@@ -593,410 +613,410 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.79% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4464      0.01%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14679264     19.04%     85.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10925524     14.17%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4488      0.01%     66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14779498     19.05%     85.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           10972237     14.15%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              77104069                       # Type of FU issued
-system.cpu0.iq.rate                          0.714843                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1137816                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.014757                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         260501553                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91556805                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     74656153                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              12379                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6497                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5408                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              78233021                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   6665                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          345101                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              77564111                       # Type of FU issued
+system.cpu0.iq.rate                          0.717014                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1148423                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014806                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         261725178                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         92258450                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     75089604                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              13541                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              7156                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5898                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              78703023                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7299                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          349741                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2206473                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2440                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        52158                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1126677                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2246191                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2538                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53151                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1141086                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       207379                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       207346                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       210404                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       206292                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1473513                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5378839                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              2159961                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           81600157                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           131532                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             15025647                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11465948                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            550941                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44144                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              2103435                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         52158                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        253796                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       219690                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              473486                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             76500063                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14443562                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           547275                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1482288                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5387849                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              2181647                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           82121235                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           133747                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             15130036                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11520954                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            554131                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 44613                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              2124772                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53151                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        259624                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       223920                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              483544                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             76945762                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14537604                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           560147                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       126680                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25263883                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14430618                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10820321                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.709244                       # Inst execution rate
-system.cpu0.iew.wb_sent                      75840899                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     74661561                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38996929                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 67640251                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       123082                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25403316                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14507602                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10865712                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.711298                       # Inst execution rate
+system.cpu0.iew.wb_sent                      76276982                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     75095502                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 39231378                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 67987446                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.692199                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.576534                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.694193                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.577039                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       11313930                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         939253                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           399962                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    102521377                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.684763                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.574745                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       11493235                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         945312                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           408278                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    102784889                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.686324                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.576953                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     75202228     73.35%     73.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12236708     11.94%     85.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6265954      6.11%     91.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2644751      2.58%     93.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1294412      1.26%     95.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       834681      0.81%     96.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1890114      1.84%     97.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       411979      0.40%     98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1740550      1.70%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     75343720     73.30%     73.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12296354     11.96%     85.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6287520      6.12%     91.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2655547      2.58%     93.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1297923      1.26%     95.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       837088      0.81%     96.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1893538      1.84%     97.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       418210      0.41%     98.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1754989      1.71%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    102521377                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            57875239                       # Number of instructions committed
-system.cpu0.commit.committedOps              70202859                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    102784889                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            58163617                       # Number of instructions committed
+system.cpu0.commit.committedOps              70543777                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23158445                       # Number of memory references committed
-system.cpu0.commit.loads                     12819174                       # Number of loads committed
-system.cpu0.commit.membars                     372518                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13646130                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5383                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 61467682                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2657552                       # Number of function calls committed.
+system.cpu0.commit.refs                      23263713                       # Number of memory references committed
+system.cpu0.commit.loads                     12883845                       # Number of loads committed
+system.cpu0.commit.membars                     375648                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13703294                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5822                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 61764808                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2662565                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        46983958     66.93%     66.93% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55992      0.08%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4464      0.01%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12819174     18.26%     85.27% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10339271     14.73%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        47219648     66.94%     66.94% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55928      0.08%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4488      0.01%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12883845     18.26%     85.29% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10379868     14.71%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         70202859                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1740550                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         70543777                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1754989                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   169629703                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  165592947                       # The number of ROB writes
-system.cpu0.timesIdled                         399199                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        2784897                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2442098527                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   57803575                       # Number of Instructions Simulated
-system.cpu0.committedOps                     70131195                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.866000                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.866000                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.535906                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.535906                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                83223669                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               47570918                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16180                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   12936                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                270428616                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                28197078                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              191501099                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                720417                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           852560                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.984422                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42511963                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           853072                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.833968                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                   170407355                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  166661887                       # The number of ROB writes
+system.cpu0.timesIdled                         403384                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2808286                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2462180041                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   58092959                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70473119                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.862130                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.862130                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.537020                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.537020                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                83669019                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47858513                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16561                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13070                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                272007090                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                28371958                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              192053211                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                725022                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           853093                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.984491                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42526051                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           853605                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.819356                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         91705250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   328.271130                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   183.713292                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.641155                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.358815                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   331.074612                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   180.909879                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.646630                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.353340                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189853089                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189853089                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12598830                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12738851                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25337681                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7730207                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8172441                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15902648                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       180909                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       181454                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       362363                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       207827                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       238877                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446704                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       213772                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       245645                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459417                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20329037                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20911292                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41240329                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20509946                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21092746                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41602692                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       422442                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       405866                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       828308                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1913785                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1789558                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3703343                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        96940                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        84905                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       181845                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13431                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14182                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27613                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        189920314                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189920314                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12675400                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12670649                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25346049                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7759190                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      8148697                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15907887                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181607                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180873                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       362480                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209218                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237638                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446856                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       215214                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       244406                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459620                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20434590                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     20819346                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41253936                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20616197                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     21000219                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41616416                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       429328                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       829991                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1922864                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1781286                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3704150                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        97758                       # number of SoftPFReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total       181879                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13488                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14194                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27682                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data           28                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           49                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           77                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2336227                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2195424                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4531651                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2433167                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2280329                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4713496                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7006933211                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6629197868                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  13636131079                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  84645436904                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  74845310131                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 159490747035                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183007245                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    209517243                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    392524488                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       467508                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       867018                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      1334526                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  91652370115                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  81474507999                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 173126878114                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  91652370115                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  81474507999                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 173126878114                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     13021272                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13144717                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26165989                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9643992                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9961999                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19605991                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       277849                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       266359                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       544208                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       221258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       253059                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474317                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       213800                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       245694                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459494                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22665264                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23106716                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45771980                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22943113                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23373075                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46316188                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032442                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030877                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031656                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198443                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179638                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188888                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.348895                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.318762                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.334146                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060703                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056042                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058216                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000131                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000199                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000168                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103075                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.095012                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099005                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106052                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097562                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.101768                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16586.734300                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16333.464414                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16462.633560                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44229.334488                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41823.349749                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43066.695965                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13625.734867                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14773.462347                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14215.206171                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16696.714286                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17694.244898                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17331.506494                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39230.935228                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37111.058273                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 38203.930116                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37667.932417                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35729.277661                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36730.036074                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1114371                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       157529                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            70035                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2409                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.911630                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    65.391864                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           50                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           78                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2352192                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      2181949                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4534141                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2449950                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2266070                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4716020                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7076789424                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6619917975                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  13696707399                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83693793081                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  75813102630                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 159506895711                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183195494                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    209562743                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    392758237                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       592508                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       853516                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      1446024                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  90770582505                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  82433020605                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 173203603110                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  90770582505                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  82433020605                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 173203603110                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     13104728                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13071312                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26176040                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9682054                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9929983                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19612037                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       279365                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       264994                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       544359                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222706                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251832                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474538                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       215242                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       244456                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459698                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22786782                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23001295                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45788077                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     23066147                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23266289                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46332436                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032761                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030652                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031708                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198601                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179385                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188871                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.349929                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.317445                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.334116                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060564                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056363                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058335                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000205                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000170                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103226                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094862                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099024                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106214                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097397                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.101787                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16483.409943                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16522.409045                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16502.236047                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43525.591556                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42560.881650                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43061.672910                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13582.109579                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14764.178033                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14188.217506                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        21161                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17070.320000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38589.784552                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37779.535913                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 38199.871400                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37049.973471                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36377.084823                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36726.647281                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1109617                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       154794                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            70377                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2390                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.766756                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    64.767364                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       703475                       # number of writebacks
-system.cpu0.dcache.writebacks::total           703475                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       210719                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       192078                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       402797                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1759982                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1643688                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3403670                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9497                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9002                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18499                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1970701                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1835766                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3806467                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1970701                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1835766                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3806467                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       211723                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       213788                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       425511                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       153803                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       145870                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299673                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        63434                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58205                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       121639                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3934                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5180                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9114                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       704003                       # number of writebacks
+system.cpu0.dcache.writebacks::total           704003                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215622                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       188357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       403979                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1768499                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1636007                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3404506                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9539                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8963                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18502                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1984121                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1824364                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3808485                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1984121                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1824364                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3808485                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       213706                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212306                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       426012                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       154365                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       145279                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299644                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        64075                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57558                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       121633                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3949                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5231                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9180                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           28                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           49                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           77                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       365526                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       359658                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       725184                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       428960                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       417863                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       846823                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2861079610                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2922012934                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5783092544                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6787467590                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6168731905                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12956199495                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    979909505                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    899145507                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1879055012                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     46870501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     79520003                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    126390504                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       411492                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       768982                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1180474                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9648547200                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9090744839                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  18739292039                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10628456705                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9989890346                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  20618347051                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3173952500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2610543001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784495501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2430739877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2005307000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436046877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5604692377                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4615850001                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220542378                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016260                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016264                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016262                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015948                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014643                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015285                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228304                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.218521                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223516                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017780                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020470                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019215                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000131                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000199                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000168                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016127                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015565                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015843                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018697                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017878                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018284                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13513.315086                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13667.806116                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13590.935473                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44130.918058                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42289.243196                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43234.457208                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15447.701627                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.908376                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15447.800557                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11914.209710                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15351.351931                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13867.731402                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14696.142857                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15693.510204                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15330.831169                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26396.336239                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.081274                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25840.741162                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24777.267589                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23907.094780                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24347.882676                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           50                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           78                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       368071                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       357585                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       725656                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       432146                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       415143                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       847289                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2880376399                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2931260112                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5811636511                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6719128315                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6232840178                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12951968493                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    978421259                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    894015008                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1872436267                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     46952751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     79934003                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    126886754                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       536492                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       753484                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1289976                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9599504714                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9164100290                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  18763605004                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10577925973                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10058115298                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  20636041271                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3170222000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2614349000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784571000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2418015877                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2018079000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436094877                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5588237877                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4632428000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220665877                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016308                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016242                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016275                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015943                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014630                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.229359                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.217205                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223443                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017732                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020772                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019345                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000205                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000170                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016153                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015546                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018735                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017843                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018287                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1007,150 +1027,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1944459                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.580154                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39104715                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1944971                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.105552                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1945413                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.581807                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           39117111                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1945925                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.102065                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       9481344250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   279.534125                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   232.046029                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.545965                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.453215                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999180                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.889096                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   233.692710                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.542752                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.456431                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999183                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          158                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43134734                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43134734                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19500172                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19604543                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39104715                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19500172                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19604543                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39104715                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19500172                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19604543                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39104715                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1039333                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1045617                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2084950                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1039333                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1045617                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2084950                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1039333                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1045617                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2084950                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14213949952                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14204519409                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  28418469361                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14213949952                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  14204519409                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  28418469361                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14213949952                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  14204519409                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  28418469361                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20539505                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20650160                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41189665                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20539505                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20650160                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41189665                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20539505                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20650160                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41189665                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050602                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050635                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050618                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050602                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050635                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050618                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050602                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050635                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050618                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13676.030639                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.820646                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13630.288190                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13676.030639                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.820646                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13630.288190                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13676.030639                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.820646                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13630.288190                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         9244                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         43149539                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        43149539                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19581058                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19536053                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       39117111                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19581058                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19536053                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        39117111                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19581058                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19536053                       # number of overall hits
+system.cpu0.icache.overall_hits::total       39117111                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1050436                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1035972                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2086408                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1050436                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1035972                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2086408                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1050436                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1035972                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2086408                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14355946637                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14071596928                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  28427543565                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14355946637                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  14071596928                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  28427543565                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14355946637                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  14071596928                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  28427543565                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20631494                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20572025                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41203519                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20631494                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20572025                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     41203519                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20631494                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20572025                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     41203519                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050914                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050358                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050637                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050914                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050358                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050637                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050914                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050358                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050637                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13666.655215                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13582.989625                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13625.112425                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13625.112425                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13625.112425                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         9173                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              502                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              525                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.414343                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.472381                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        69295                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        70585                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       139880                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        69295                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        70585                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       139880                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        69295                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        70585                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       139880                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       970038                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       975032                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1945070                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       970038                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       975032                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1945070                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       970038                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       975032                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1945070                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11608622245                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11596487286                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  23205109531                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11608622245                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11596487286                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  23205109531                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11608622245                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11596487286                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  23205109531                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70447                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        69940                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       140387                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        70447                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        69940                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       140387                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        70447                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        69940                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       140387                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       979989                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       966032                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1946021                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       979989                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       966032                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1946021                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       979989                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       966032                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1946021                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11725666308                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11493227261                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  23218893569                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11725666308                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11493227261                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  23218893569                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11725666308                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11493227261                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  23218893569                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     49455500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total     49455500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047228                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.047217                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047222                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047228                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.047217                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047222                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047228                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.047217                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047222                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.182981                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11893.442765                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11930.218209                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.182981                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11893.442765                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11930.218209                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.182981                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11893.442765                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11930.218209                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047229                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047229                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047229                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11931.471227                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27351704                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14236490                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           554287                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17308437                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               12845549                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27255758                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14164958                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           545624                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17245755                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               12796801                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            74.215534                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6761805                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29778                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            74.202614                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6756979                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29539                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1174,25 +1194,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14383095                       # DTB read hits
-system.cpu1.dtb.read_misses                     49639                       # DTB read misses
-system.cpu1.dtb.write_hits                   10688826                       # DTB write hits
-system.cpu1.dtb.write_misses                     9570                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14301761                       # DTB read hits
+system.cpu1.dtb.read_misses                     48555                       # DTB read misses
+system.cpu1.dtb.write_hits                   10652785                       # DTB write hits
+system.cpu1.dtb.write_misses                    10002                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         175                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3468                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      807                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1316                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3340                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      749                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1278                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      561                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14432734                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10698396                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      539                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14350316                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10662787                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         25071921                       # DTB hits
-system.cpu1.dtb.misses                          59209                       # DTB misses
-system.cpu1.dtb.accesses                     25131130                       # DTB accesses
+system.cpu1.dtb.hits                         24954546                       # DTB hits
+system.cpu1.dtb.misses                          58557                       # DTB misses
+system.cpu1.dtb.accesses                     25013103                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1214,333 +1234,334 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    20651947                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7444                       # ITB inst misses
+system.cpu1.itb.inst_hits                    20573712                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7567                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         175                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2253                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2209                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1346                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1224                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20659391                       # ITB inst accesses
-system.cpu1.itb.hits                         20651947                       # DTB hits
-system.cpu1.itb.misses                           7444                       # DTB misses
-system.cpu1.itb.accesses                     20659391                       # DTB accesses
-system.cpu1.numCycles                       107242437                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20581279                       # ITB inst accesses
+system.cpu1.itb.hits                         20573712                       # DTB hits
+system.cpu1.itb.misses                           7567                       # DTB misses
+system.cpu1.itb.accesses                     20581279                       # DTB accesses
+system.cpu1.numCycles                       106992745                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          40725111                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     106781914                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27351704                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19607354                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     61789362                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3232365                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    107163                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                4234                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              436                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       251985                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       137059                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          228                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20650163                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               382444                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3144                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         104631724                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.228100                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.325979                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          40476291                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     106336791                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27255758                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19553780                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     61749013                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3214085                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    109935                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                4125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              398                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       310457                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       137038                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20572028                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               377209                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3305                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         104394378                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.225923                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.323476                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                75276621     71.94%     71.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3919456      3.75%     75.69% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2502030      2.39%     78.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8106690      7.75%     85.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1591855      1.52%     87.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1179587      1.13%     88.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6153020      5.88%     94.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1148569      1.10%     95.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4753896      4.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                75141351     71.98%     71.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3905835      3.74%     75.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2486724      2.38%     78.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8099869      7.76%     85.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1581267      1.51%     87.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1170303      1.12%     88.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6153110      5.89%     94.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1141979      1.09%     95.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4713940      4.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           104631724                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.255046                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.995706                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                27872686                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             57819434                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15751164                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1722324                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1465861                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1979467                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               152392                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              89250616                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               494405                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1465861                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                28821025                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                6714609                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      45327507                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16516394                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              5786062                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              85371989                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 2599                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1571177                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                234219                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               3175787                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           88221695                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            393591898                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        95352384                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6204                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             74304877                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13916818                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1590220                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1488950                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10060689                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15200897                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11860337                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2181365                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2795831                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  82084086                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1161665                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 78697860                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            94798                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       10134538                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25514104                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        106722                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    104631724                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.752141                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.431263                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           104394378                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.254744                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.993869                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                27669699                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             57891094                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15657559                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1717451                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1458318                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1956668                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               150768                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              88739686                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               487490                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1458318                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                28613011                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                6694397                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      45325373                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16423590                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              5879419                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              84880856                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 2064                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1581177                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                275105                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               3240122                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           87684483                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            391488803                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94864107                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5764                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             73992323                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13692160                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1588753                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1487965                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 10049323                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15109971                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11816534                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2163704                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2733219                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  81632312                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1156422                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78295274                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            93656                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        9981310                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     25207475                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        106198                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    104394378                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.749995                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.429509                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           72948361     69.72%     69.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10716718     10.24%     79.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8047314      7.69%     87.65% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6681191      6.39%     94.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2496863      2.39%     96.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1548306      1.48%     97.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1467102      1.40%     99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             495605      0.47%     99.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             230264      0.22%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           72878860     69.81%     69.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10639333     10.19%     80.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8017923      7.68%     87.68% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6659758      6.38%     94.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2479715      2.38%     96.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1538380      1.47%     97.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1459445      1.40%     99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             494321      0.47%     99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             226643      0.22%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      104631724                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      104394378                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 103418      8.95%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                534479     46.25%     55.20% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               517677     44.80%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 101103      8.77%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                535174     46.44%     55.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               516045     44.78%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass              138      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             52546114     66.77%     66.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               58878      0.07%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              1      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4118      0.01%     66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14788040     18.79%     85.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11300566     14.36%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass              125      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52268288     66.76%     66.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59024      0.08%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              1      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4106      0.01%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14700600     18.78%     85.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11263124     14.39%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              78697860                       # Type of FU issued
-system.cpu1.iq.rate                          0.733831                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1155578                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014684                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         263263981                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         93425233                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     76303202                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              13839                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              7410                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6119                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              79845879                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7421                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          368633                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78295274                       # Type of FU issued
+system.cpu1.iq.rate                          0.731781                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1152326                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014718                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         262217922                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         92814464                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     75924804                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              12986                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6859                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5648                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79440457                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7018                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          366358                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2206977                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2711                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        53558                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1154048                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2171723                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2780                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        52487                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1144439                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       194646                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       154093                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       191401                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       154292                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1465861                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4319089                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2154851                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           83386940                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           137036                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15200897                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11860337                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            585271                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 47319                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2094987                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         53558                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        256552                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       222245                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              478797                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             78084459                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14546039                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           554355                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1458318                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                4304329                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2156600                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           82933418                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           134740                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15109971                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11816534                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            582996                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 47778                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2096463                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         52487                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        251579                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       218702                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              470281                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77694436                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14463933                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           542445                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       141189                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25737628                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14524352                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11191589                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.728112                       # Inst execution rate
-system.cpu1.iew.wb_sent                      77455792                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     76309321                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 39942887                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 70003346                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       144684                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25618626                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14454326                       # Number of branches executed
+system.cpu1.iew.exec_stores                  11154693                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.726165                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77075073                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     75930452                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39739983                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69711076                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.711559                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.570585                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.709679                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.570067                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       11462178                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls        1054943                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           403929                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    102065282                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.704569                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.588134                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       11308333                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls        1050224                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           396863                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    101852612                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.703099                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.586744                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     73979562     72.48%     72.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12596710     12.34%     84.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6446210      6.32%     91.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2677597      2.62%     93.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1413220      1.38%     95.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       933927      0.92%     96.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1825426      1.79%     97.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       426013      0.42%     98.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1766617      1.73%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     73894552     72.55%     72.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12525380     12.30%     84.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6426003      6.31%     91.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2662589      2.61%     93.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1410437      1.38%     95.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       930996      0.91%     96.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1822810      1.79%     97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       425009      0.42%     98.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1754836      1.72%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    102065282                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            59241455                       # Number of instructions committed
-system.cpu1.commit.committedOps              71912019                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    101852612                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            58987480                       # Number of instructions committed
+system.cpu1.commit.committedOps              71612492                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23700209                       # Number of memory references committed
-system.cpu1.commit.loads                     12993920                       # Number of loads committed
-system.cpu1.commit.membars                     441872                       # Number of memory barriers committed
-system.cpu1.commit.branches                  13745651                       # Number of branches committed
-system.cpu1.commit.fp_insts                      6045                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 63021281                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2683532                       # Number of function calls committed.
+system.cpu1.commit.refs                      23610343                       # Number of memory references committed
+system.cpu1.commit.loads                     12938248                       # Number of loads committed
+system.cpu1.commit.membars                     439261                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13694369                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5606                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 62760739                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2679383                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        48150599     66.96%     66.96% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57094      0.08%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4117      0.01%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       12993920     18.07%     85.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10706289     14.89%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        47940825     66.94%     66.94% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57221      0.08%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4103      0.01%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       12938248     18.07%     85.10% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10672095     14.90%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         71912019                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1766617                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         71612492                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1754836                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   171199210                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  169319306                       # The number of ROB writes
-system.cpu1.timesIdled                         392561                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2610713                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2951410695                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   59158214                       # Number of Instructions Simulated
-system.cpu1.committedOps                     71828778                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.812807                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.812807                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.551631                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.551631                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                84962024                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48578648                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    16598                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13166                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                275767015                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29005141                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              192510337                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                799392                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   170535238                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168387616                       # The number of ROB writes
+system.cpu1.timesIdled                         388789                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2598367                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2951659136                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   58903233                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71528245                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.816415                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.816415                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.550535                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.550535                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84575323                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48329446                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    16299                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13042                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                274393748                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                28845956                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              191595742                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                795775                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30210                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30210                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1631,42 +1652,46 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326614949                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347069959                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36834534                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36834574                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                0.982055                       # Cycle average of tags in use
-system.iocache.tags.total_refs                     16                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000439                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         234012764000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.982055                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.061378                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.061378                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36411                       # number of replacements
+system.iocache.tags.tagsinuse                1.036467                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     28                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36427                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000769                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         234012835000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.036467                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064779                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064779                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328241                       # Number of tag accesses
-system.iocache.tags.data_accesses              328241                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328229                       # Number of tag accesses
+system.iocache.tags.data_accesses              328229                       # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::realview.ide           27                       # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total           27                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36197                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36197                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29659377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29659377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29659377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29659377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29659377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29659377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29650777                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29650777                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9620896608                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9620896608                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29650777                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29650777                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29650777                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29650777                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1677,296 +1702,306 @@ system.iocache.overall_accesses::realview.ide          249
 system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.999255                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total     0.999255                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119113.963855                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119113.963855                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119113.963855                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119113.963855                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119113.963855                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119079.425703                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119079.425703                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119079.425703                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56505                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7228                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.817515                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36162                       # number of writebacks
+system.iocache.writebacks::total                36162                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36197                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36197                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16710377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16710377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2225221106                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2225221106                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16710377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16710377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16710377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16710377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16701777                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16701777                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16701777                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16701777                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16701777                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16701777                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67109.947791                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67109.947791                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67075.409639                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67075.409639                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213788.566898                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213788.566898                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104249                       # number of replacements
-system.l2c.tags.tagsinuse                65131.495439                       # Cycle average of tags in use
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-system.l2c.tags.avg_refs                    18.335180                       # Average number of references to valid blocks.
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-system.l2c.Writeback_accesses::writebacks       703475                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           703475                       # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data         1506                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.SCUpgradeReq_accesses::cpu0.data           28                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001816                       # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.969357                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.961487                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.965190                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.285714                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.367347                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu0.data     0.490251                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.454192                       # miss rate for ReadExReq accesses
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-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001816                       # miss rate for demand accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.966667                       # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   337.347376                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   299.258652                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14624.375000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9055.166667                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 77084.045914                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 78397.840236                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 77529.456632                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1975,166 +2010,166 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95499                       # number of writebacks
-system.l2c.writebacks::total                    95499                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            73                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            66                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               150                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             73                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001816                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000108                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.185622                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001869                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010193                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.178151                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.061018                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001796                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000112                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.011238                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.189690                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001875                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010219                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.174210                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.061041                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.185622                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001869                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010193                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.178151                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.061018                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62939.311927                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68249.154993                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62482.734391                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69566.014635                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 65322.906692                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.781804                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10044.162983                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.500546                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68457.461561                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71153.569434                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 65815.992635                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.127916                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.450387                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.454182                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20050.800000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64274.914919                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65547.461649                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 64869.592247                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13866.307692                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64141.581463                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65701.749106                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 64881.275293                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62939.311927                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64620.091520                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62482.734391                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65977.465861                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 64962.074596                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62939.311927                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64620.091520                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62482.734391                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65977.465861                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 64962.074596                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -2147,57 +2182,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               68015                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68014                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
-system.membus.trans_dist::Writeback             95499                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
+system.membus.trans_dist::ReadReq               68031                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68030                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27609                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27609                       # Transaction distribution
+system.membus.trans_dist::Writeback            131669                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36196                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4639                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4652                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138449                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138449                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4665                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138446                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138446                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       464808                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       572448                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 645160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       464572                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       572218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 681038                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17335960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17499937                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19819233                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              234                       # Total snoops (count)
-system.membus.snoop_fanout::samples            311043                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17318744                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17482733                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4631872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22114605                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              524                       # Total snoops (count)
+system.membus.snoop_fanout::samples            347207                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  311043    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  347207    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              311043                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81528999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              347207                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81506999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               15812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1699500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1714000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1433996498                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1759264748                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1730108850                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1730266590                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38499466                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38512426                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2230,57 +2265,57 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2655847                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2655761                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             27608                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            27608                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           703475                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2657108                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2657013                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             27609                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            27609                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           704003                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2844                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            77                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            78                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2921                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296861                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296861                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3891199                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2533159                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        43047                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169738                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6637143                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124509952                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99813985                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        66376                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       294776                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224685089                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           69111                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3663534                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.009957                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.099284                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadExReq           296844                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296844                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3893099                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2534750                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42773                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169663                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6640285                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124570688                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99881325                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        65944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       294780                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              224812737                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           68939                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3665274                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.009944                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.099221                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3627058     99.00%     99.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                  36476      1.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3628828     99.01%     99.01% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                  36446      0.99%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3663534                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4671361722                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3665274                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4674358232                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           738000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           697500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        8762587438                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        8766890883                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3909721674                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3912089949                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          26515368                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          26359345                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          96849116                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          96778607                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3039                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    3042                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 0d43a2133..120ee67e1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,140 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.904683                       # Number of seconds simulated
-sim_ticks                                2904682547500                       # Number of ticks simulated
-final_tick                               2904682547500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.904915                       # Number of seconds simulated
+sim_ticks                                2904914753500                       # Number of ticks simulated
+final_tick                               2904914753500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 744036                       # Simulator instruction rate (inst/s)
-host_op_rate                                   897074                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            19213049576                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 562336                       # Number of bytes of host memory used
-host_seconds                                   151.18                       # Real time elapsed on the host
-sim_insts                                   112485415                       # Number of instructions simulated
-sim_ops                                     135622211                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 754235                       # Simulator instruction rate (inst/s)
+host_op_rate                                   909375                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19474929667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 559844                       # Number of bytes of host memory used
+host_seconds                                   149.16                       # Real time elapsed on the host
+sim_insts                                   112502966                       # Number of instructions simulated
+sim_ops                                     135643907                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           557732                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4265248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           552740                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4263328                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           631552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4773892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           636352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4758276                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10229960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       557732                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       631552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1189284                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5300352                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10212232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       552740                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       636352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1189092                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7616448                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7636212                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7633972                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             17168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             67163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             17090                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             67133                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9868                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             74593                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9943                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74349                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168816                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           82818                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                168539                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          119007                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123423                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123388                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              192011                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1468404                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              190278                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1467626                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           154                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              217425                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1643516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3521886                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         192011                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         217425                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             409437                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1824761                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              219060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1638009                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3515501                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         190278                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         219060                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             409338                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2621918                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6030                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          798137                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2628932                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1824761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2627950                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2621918                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             192011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1474434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             190278                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1473656                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          154                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             217425                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1643519                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          798468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6150817                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        168816                       # Number of read requests accepted
-system.physmem.writeReqs                       123423                       # Number of write requests accepted
-system.physmem.readBursts                      168816                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123423                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10794880                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7651200                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10229960                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7636212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4511                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9768                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9653                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10324                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9994                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18675                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10148                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10372                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10429                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10451                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9811                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9561                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9986                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9803                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9966                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9791                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7253                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7191                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8157                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7614                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7092                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7380                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7560                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7725                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7575                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8007                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7415                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7436                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7462                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7248                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7309                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7126                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             219060                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1638012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6143452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168539                       # Number of read requests accepted
+system.physmem.writeReqs                       159612                       # Number of write requests accepted
+system.physmem.readBursts                      168539                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     159612                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10780160                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6336                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9866880                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10212232                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9952308                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       99                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5435                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4495                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9752                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9630                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10293                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9989                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18671                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10140                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10341                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10423                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9932                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10445                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9791                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9555                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9939                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9802                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9961                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9776                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9466                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9312                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10445                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9717                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9000                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9463                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9580                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9878                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9939                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10290                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9717                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9744                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9808                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9372                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9292                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9147                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2904682181000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2904914374000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159244                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  158967                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 119042                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    167845                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       557                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 155231                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167646                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       538                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       244                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -164,170 +161,194 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7493                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58500                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      315.315419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.678002                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.865134                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21233     36.30%     36.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14762     25.23%     61.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5741      9.81%     71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3177      5.43%     76.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2294      3.92%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1562      2.67%     83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1019      1.74%     85.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1097      1.88%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7615     13.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58500                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5866                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.752472                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      562.127013                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5865     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                       200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9589                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     9964                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26                     9659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8698                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29                     7070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6530                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::59                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60664                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      340.349730                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     196.021429                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     354.920810                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21349     35.19%     35.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14624     24.11%     59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5778      9.52%     68.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3154      5.20%     74.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2318      3.82%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1542      2.54%     80.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1044      1.72%     82.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1115      1.84%     83.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9740     16.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60664                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6204                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.148614                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      546.636063                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6203     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5866                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.380157                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.599784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.515949                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                16      0.27%      0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                10      0.17%      0.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               13      0.22%      0.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              18      0.31%      0.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4930     84.04%     85.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              59      1.01%     86.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              57      0.97%     86.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             249      4.24%     91.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             210      3.58%     94.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.34%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              11      0.19%     95.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.14%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              30      0.51%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               5      0.09%     96.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.07%     96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.05%     96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             157      2.68%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.09%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.07%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.05%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              19      0.32%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               6      0.10%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             6      0.10%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             6      0.10%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.05%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.12%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5866                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1486855250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4649417750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    843350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8815.17                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6204                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6204                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.850097                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.346548                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.047003                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                14      0.23%      0.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                12      0.19%      0.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                8      0.13%      0.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              18      0.29%      0.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4939     79.61%     80.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              68      1.10%     81.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              50      0.81%     82.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             255      4.11%     86.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             123      1.98%     88.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              43      0.69%     89.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              46      0.74%     89.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              38      0.61%     90.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             127      2.05%     92.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.18%     92.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              16      0.26%     92.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.13%     93.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              34      0.55%     93.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              17      0.27%     93.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              13      0.21%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              28      0.45%     94.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              70      1.13%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              11      0.18%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               7      0.11%     96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              13      0.21%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              92      1.48%     97.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     97.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            13      0.21%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             5      0.08%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            13      0.21%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.06%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             6      0.10%     98.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.05%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            29      0.47%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            12      0.19%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             7      0.11%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.10%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             6      0.10%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             4      0.06%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.06%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             6      0.10%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6204                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1487388750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4645638750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    842200000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8830.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27565.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.72                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.63                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27580.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.40                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.63                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.43                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139006                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     90713                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.41                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9939406.38                       # Average gap between requests
-system.physmem.pageHitRate                      79.70                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2756105768250                       # Time in different power states
-system.physmem.memoryStateTime::REF       96993520000                       # Time in different power states
+system.physmem.avgWrQLen                        11.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138839                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    123106                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.85                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8852370.93                       # Average gap between requests
+system.physmem.pageHitRate                      81.19                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2756204372250                       # Time in different power states
+system.physmem.memoryStateTime::REF       97001320000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       51577106750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       51708967750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 224736120                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 217523880                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 122623875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 118688625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                697031400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                618579000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               388618560                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               386065440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          189719325120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          189719325120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           86946648885                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           86006740545                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1666536838500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1667361319500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1944635822460                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1944428242110                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.484503                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.413038                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 232462440                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 226157400                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 126839625                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 123399375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                696064200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                617760000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               498059280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               500962320                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          189734581920                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          189734581920                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           86971409685                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           86091461640                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1666655279250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1667427163500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1944914696400                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1944721486155                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.526666                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.460155                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -370,25 +391,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12289553                       # DTB read hits
-system.cpu0.dtb.read_misses                      5977                       # DTB read misses
-system.cpu0.dtb.write_hits                    9834643                       # DTB write hits
-system.cpu0.dtb.write_misses                     1047                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2938                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     467                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    12308215                       # DTB read hits
+system.cpu0.dtb.read_misses                      6223                       # DTB read misses
+system.cpu0.dtb.write_hits                    9796614                       # DTB write hits
+system.cpu0.dtb.write_misses                     1025                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2937                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     436                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    4657                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    4667                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   865                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   862                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      233                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12295530                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9835690                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      219                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12314438                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9797639                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         22124196                       # DTB hits
-system.cpu0.dtb.misses                           7024                       # DTB misses
-system.cpu0.dtb.accesses                     22131220                       # DTB accesses
+system.cpu0.dtb.hits                         22104829                       # DTB hits
+system.cpu0.dtb.misses                           7248                       # DTB misses
+system.cpu0.dtb.accesses                     22112077                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -410,224 +431,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    58032770                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3465                       # ITB inst misses
+system.cpu0.itb.inst_hits                    58194599                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3600                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2938                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     467                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                        2937                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     436                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2699                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2765                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                58036235                       # ITB inst accesses
-system.cpu0.itb.hits                         58032770                       # DTB hits
-system.cpu0.itb.misses                           3465                       # DTB misses
-system.cpu0.itb.accesses                     58036235                       # DTB accesses
-system.cpu0.numCycles                      2905319694                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                58198199                       # ITB inst accesses
+system.cpu0.itb.hits                         58194599                       # DTB hits
+system.cpu0.itb.misses                           3600                       # DTB misses
+system.cpu0.itb.accesses                     58198199                       # DTB accesses
+system.cpu0.numCycles                      2905784484                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   56513131                       # Number of instructions committed
-system.cpu0.committedOps                     68067849                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             60172046                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  6287                       # Number of float alu accesses
-system.cpu0.num_func_calls                    4924583                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7649378                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    60172046                       # number of integer instructions
-system.cpu0.num_fp_insts                         6287                       # number of float instructions
-system.cpu0.num_int_register_reads          109432768                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41532346                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4990                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1298                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           245794871                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           26123486                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     22763364                       # number of memory refs
-system.cpu0.num_load_insts                   12450622                       # Number of load instructions
-system.cpu0.num_store_insts                  10312742                       # Number of store instructions
-system.cpu0.num_idle_cycles              2685746001.120693                       # Number of idle cycles
-system.cpu0.num_busy_cycles              219573692.879307                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.075576                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.924424                       # Percentage of idle cycles
-system.cpu0.Branches                         12983457                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2204      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46789630     67.21%     67.21% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58620      0.08%     67.30% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4273      0.01%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::MemRead                12450622     17.88%     85.19% # Class of executed instruction
-system.cpu0.op_class::MemWrite               10312742     14.81%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   56652370                       # Number of instructions committed
+system.cpu0.committedOps                     68154355                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             60226518                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5995                       # Number of float alu accesses
+system.cpu0.num_func_calls                    4919534                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7679282                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    60226518                       # number of integer instructions
+system.cpu0.num_fp_insts                         5995                       # number of float instructions
+system.cpu0.num_int_register_reads          109459523                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41576844                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4468                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1530                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           246082665                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           26221599                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     22745945                       # number of memory refs
+system.cpu0.num_load_insts                   12471278                       # Number of load instructions
+system.cpu0.num_store_insts                  10274667                       # Number of store instructions
+system.cpu0.num_idle_cycles              2686990403.807933                       # Number of idle cycles
+system.cpu0.num_busy_cycles              218794080.192067                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.075296                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.924704                       # Percentage of idle cycles
+system.cpu0.Branches                         13013332                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2203      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46892920     67.27%     67.28% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58660      0.08%     67.36% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4258      0.01%     67.37% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.37% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.37% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.37% # Class of executed instruction
+system.cpu0.op_class::MemRead                12471278     17.89%     85.26% # Class of executed instruction
+system.cpu0.op_class::MemWrite               10274667     14.74%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  69618091                       # Class of executed instruction
+system.cpu0.op_class::total                  69703986                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3031                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           822992                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.850755                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43241503                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           823504                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            52.509160                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           822947                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.850765                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43250055                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           823459                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.522415                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        876905250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   320.068917                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   191.781838                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.625135                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.374574                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   320.083666                       # Average occupied blocks per requestor
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 system.cpu0.dcache.tags.occ_percent::total     0.999709                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
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-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
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 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        177151535                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       177151535                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11581583                       # number of ReadReq hits
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 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019312                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.019007                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14651.776540                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14834.078102                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14743.759808                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.575527                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40381.579838                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39434.538871                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12145.488857                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12484.405877                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12318.750824                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        75500                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        75500                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        75500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.665837                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25719.208451                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25259.327321                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21314.605485                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21869.904186                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21596.414362                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs           38                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
@@ -636,109 +661,113 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs            2
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       686960                       # number of writebacks
-system.cpu0.dcache.writebacks::total           686960                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          287                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          328                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          615                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7032                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7182                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14214                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          287                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          328                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          615                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          287                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          328                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          615                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       197010                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       205198                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       402208                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       150193                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148466                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       298659                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57639                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        59222                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       116861                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4095                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4463                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8558                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       686899                       # number of writebacks
+system.cpu0.dcache.writebacks::total           686899                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          272                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          344                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          616                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7030                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7175                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14205                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          272                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          344                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          616                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          272                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          344                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          616                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       199245                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       202851                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       402096                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       147894                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       150849                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       298743                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55774                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        61059                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       116833                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4098                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4464                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8562                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       347203                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       353664                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       700867                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       404842                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       412886                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       817728                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2467868750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2647702500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5115571250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5416592829                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5704580119                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11121172948                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    696038250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    742244000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1438282250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     48274750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52699750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100974500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        47998                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        47998                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7884461579                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8352282619                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16236744198                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8580499829                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9094526619                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  17675026448                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2688395000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3103027500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5791422500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2165315000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2264487500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4429802500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4853710000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5367515000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10221225000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016726                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017479                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017102                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015665                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015565                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015615                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.223162                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.234333                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228687                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017195                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019582                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018362                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       347139                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       353700                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       700839                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       402913                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       414759                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       817672                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2517898250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2600172750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5118071000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5366137441                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5759365015                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11125502456                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    677278250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    762448500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1439726750                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     48257750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52710750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100968500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        73500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        73500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       147000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7884035691                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8359537765                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16243573456                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8561313941                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9121986265                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  17683300206                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2688812000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3102617000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5791429000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2186315500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2243484000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4429799500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4875127500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5346101000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10221228500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016885                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017304                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017094                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015487                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015745                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.218539                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.238633                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228599                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017166                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019626                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018366                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016250                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016621                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016435                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018721                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019177                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018948                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        23999                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        23999                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016260                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016603                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016431                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018649                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019238                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018943                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36283.672367                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38179.669835                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37241.048179                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12143.261197                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12487.078072                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12322.946000                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11775.927282                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11807.963710                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11792.630227                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        73500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        73500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        73500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -749,79 +778,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1698167                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.774848                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          113885267                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1698679                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.043430                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1699785                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.774941                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          113901535                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1700297                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            66.989200                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      25359588250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   419.089773                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    91.685075                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.818535                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.179072                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   418.326028                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    92.448913                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.817043                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.180564                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.997607                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        117282637                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       117282637                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     57188138                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     56697129                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      113885267                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     57188138                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     56697129                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       113885267                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     57188138                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     56697129                       # number of overall hits
-system.cpu0.icache.overall_hits::total      113885267                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       844632                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       854053                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1698685                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       844632                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       854053                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1698685                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       844632                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       854053                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1698685                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11522232749                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11755811000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  23278043749                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11522232749                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  11755811000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  23278043749                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11522232749                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  11755811000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  23278043749                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     58032770                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     57551182                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115583952                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     58032770                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     57551182                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115583952                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     58032770                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     57551182                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115583952                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014554                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014840                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014697                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014554                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014840                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014697                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014554                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014840                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014697                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.719410                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.732400                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.567023                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.719410                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.732400                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13703.567023                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.719410                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.732400                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13703.567023                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        117302141                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       117302141                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     57346605                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     56554930                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      113901535                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     57346605                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     56554930                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       113901535                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     57346605                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     56554930                       # number of overall hits
+system.cpu0.icache.overall_hits::total      113901535                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       847994                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       852309                       # number of ReadReq misses
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+system.cpu0.icache.demand_misses::cpu1.inst       852309                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1700303                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       847994                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       852309                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1700303                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11562218249                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11735358750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  23297576999                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11562218249                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  11735358750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  23297576999                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11562218249                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  11735358750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  23297576999                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     58194599                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     57407239                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115601838                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     58194599                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     57407239                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115601838                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     58194599                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     57407239                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115601838                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014572                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014847                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014708                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014572                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014847                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014708                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014572                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014847                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014708                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13634.787804                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13768.901596                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.014876                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13634.787804                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13768.901596                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13702.014876                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13634.787804                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13768.901596                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13702.014876                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -830,46 +859,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       844632                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       854053                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1698685                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       844632                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       854053                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1698685                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       844632                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       854053                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1698685                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9830027251                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10044094000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  19874121251                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9830027251                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10044094000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  19874121251                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9830027251                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10044094000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  19874121251                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       847994                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       852309                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1700303                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       847994                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       852309                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1700303                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       847994                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       852309                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1700303                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9863343751                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10027058250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  19890402001                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9863343751                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10027058250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  19890402001                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9863343751                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10027058250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  19890402001                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    597905000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    597905000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    597905000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    597905000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014554                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014840                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014697                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014554                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014840                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014697                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014554                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014840                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014697                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014708                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014708                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014708                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11698.151448                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11698.151448                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
@@ -898,25 +927,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12236392                       # DTB read hits
-system.cpu1.dtb.read_misses                      5657                       # DTB read misses
-system.cpu1.dtb.write_hits                    9775692                       # DTB write hits
-system.cpu1.dtb.write_misses                      790                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2934                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     450                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    12222550                       # DTB read hits
+system.cpu1.dtb.read_misses                      5478                       # DTB read misses
+system.cpu1.dtb.write_hits                    9817405                       # DTB write hits
+system.cpu1.dtb.write_misses                      801                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2935                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    4044                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    4101                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   918                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   936                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      212                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12242049                       # DTB read accesses
-system.cpu1.dtb.write_accesses                9776482                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      226                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12228028                       # DTB read accesses
+system.cpu1.dtb.write_accesses                9818206                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         22012084                       # DTB hits
-system.cpu1.dtb.misses                           6447                       # DTB misses
-system.cpu1.dtb.accesses                     22018531                       # DTB accesses
+system.cpu1.dtb.hits                         22039955                       # DTB hits
+system.cpu1.dtb.misses                           6279                       # DTB misses
+system.cpu1.dtb.accesses                     22046234                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -938,93 +967,94 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    57551182                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3277                       # ITB inst misses
+system.cpu1.itb.inst_hits                    57407239                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3155                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2934                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     450                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                        2935                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2396                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2356                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                57554459                       # ITB inst accesses
-system.cpu1.itb.hits                         57551182                       # DTB hits
-system.cpu1.itb.misses                           3277                       # DTB misses
-system.cpu1.itb.accesses                     57554459                       # DTB accesses
-system.cpu1.numCycles                      2904045401                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                57410394                       # ITB inst accesses
+system.cpu1.itb.hits                         57407239                       # DTB hits
+system.cpu1.itb.misses                           3155                       # DTB misses
+system.cpu1.itb.accesses                     57410394                       # DTB accesses
+system.cpu1.numCycles                      2904045023                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   55972284                       # Number of instructions committed
-system.cpu1.committedOps                     67554362                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             59752131                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5003                       # Number of float alu accesses
-system.cpu1.num_func_calls                    4972365                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      7584533                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    59752131                       # number of integer instructions
-system.cpu1.num_fp_insts                         5003                       # number of float instructions
-system.cpu1.num_int_register_reads          108688988                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          41135378                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3588                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1418                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           244071190                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           25783552                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     22653716                       # number of memory refs
-system.cpu1.num_load_insts                   12397911                       # Number of load instructions
-system.cpu1.num_store_insts                  10255805                       # Number of store instructions
-system.cpu1.num_idle_cycles              2693922745.089012                       # Number of idle cycles
-system.cpu1.num_busy_cycles              210122655.910988                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.072355                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.927645                       # Percentage of idle cycles
-system.cpu1.Branches                         12941389                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                  133      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 46411475     67.14%     67.14% # Class of executed instruction
-system.cpu1.op_class::IntMult                   56055      0.08%     67.22% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4164      0.01%     67.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.23% # Class of executed instruction
-system.cpu1.op_class::MemRead                12397911     17.94%     85.16% # Class of executed instruction
-system.cpu1.op_class::MemWrite               10255805     14.84%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   55850596                       # Number of instructions committed
+system.cpu1.committedOps                     67489552                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             59717976                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5231                       # Number of float alu accesses
+system.cpu1.num_func_calls                    4978644                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      7556287                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    59717976                       # number of integer instructions
+system.cpu1.num_fp_insts                         5231                       # number of float instructions
+system.cpu1.num_int_register_reads          108697708                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          41105654                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4046                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1186                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           243864682                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           25692319                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     22680019                       # number of memory refs
+system.cpu1.num_load_insts                   12382292                       # Number of load instructions
+system.cpu1.num_store_insts                  10297727                       # Number of store instructions
+system.cpu1.num_idle_cycles              2693854199.172201                       # Number of idle cycles
+system.cpu1.num_busy_cycles              210190823.827799                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.072379                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.927621                       # Percentage of idle cycles
+system.cpu1.Branches                         12914403                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  134      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 46321486     67.07%     67.07% # Class of executed instruction
+system.cpu1.op_class::IntMult                   56040      0.08%     67.15% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4215      0.01%     67.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.16% # Class of executed instruction
+system.cpu1.op_class::MemRead                12382292     17.93%     85.09% # Class of executed instruction
+system.cpu1.op_class::MemWrite               10297727     14.91%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69125543                       # Class of executed instruction
+system.cpu1.op_class::total                  69061894                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1115,38 +1145,40 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326584349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347067538                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36804759                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36804503                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.083103                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084296                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         309429741000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.083103                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067694                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067694                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         309429812000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.084296                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067768                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067768                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     28034377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     28034377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9591408658                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9591408658                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     28034377                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     28034377                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     28034377                       # number of overall miss cycles
@@ -1161,288 +1193,303 @@ system.iocache.overall_accesses::realview.ide          234
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119805.029915                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 119805.029915                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 119805.029915                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs         55572                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
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 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.744147                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
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-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2203719731                       # number of WriteInvalidateReq MSHR miss cycles
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-system.l2c.tags.avg_refs                    17.882748                       # Average number of references to valid blocks.
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 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        74500                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 72581.002331                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70161.559614                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 70080.518220                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80928.571429                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72727.655047                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 69399.025052                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        74500                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 72581.002331                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70161.559614                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 72746.655518                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70080.518220                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80928.571429                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72727.655047                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 69399.025052                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70084.165387                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72449.497235                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 69593.422321                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70133.163519                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1451,147 +1498,151 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82818                       # number of writebacks
-system.l2c.writebacks::total                    82818                       # number of writebacks
+system.l2c.writebacks::writebacks               82817                       # number of writebacks
+system.l2c.writebacks::total                    82817                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         8151                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         9868                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1297                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1431                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2728                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        62336                       # number of ReadExReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
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 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    474215000                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000161                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009651                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001313                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026104                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.013445                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991684                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991639                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.423860                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.459800                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.442008                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000155                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000289                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009520                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.166762                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001337                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011668                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.180281                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063345                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000155                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000289                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009520                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.166762                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001337                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011668                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.180281                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063345                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        62500                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59942.185008                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63830.860824                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60112.752384                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64077.284218                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60084.515606                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62861.376264                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61330.336427                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56856.845964                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55979.022115                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56397.243053                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59800.427350                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.730466                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61469.007922                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.370370                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.045222                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.391768                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        60500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        60500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        60500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56703.765702                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56174.712113                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56425.862345                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        62500                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59942.185008                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57386.469559                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60112.752384                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57307.407335                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60084.515606                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56618.658303                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57321.604441                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59800.427350                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56812.065606                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57370.855040                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        62500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57321.604441                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57370.855040                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -1604,57 +1655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               70576                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70576                       # Transaction distribution
+system.membus.trans_dist::ReadReq               70575                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70575                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27613                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27613                       # Transaction distribution
-system.membus.trans_dist::Writeback             82818                       # Transaction distribution
+system.membus.trans_dist::Writeback            119007                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4509                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4495                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129059                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129059                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4497                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129060                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129060                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438204                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       545868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 618565                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       437896                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       545560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 654447                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15546876                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     15710301                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18029597                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              219                       # Total snoops (count)
-system.membus.snoop_fanout::samples            283019                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15529084                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     15692509                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20327965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              498                       # Total snoops (count)
+system.membus.snoop_fanout::samples            319191                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  283019    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  319191    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              283019                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87171000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              319191                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87172500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1736000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1735000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1336695000                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1640329489                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1662315000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1640286255                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38340241                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38333497                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1687,54 +1738,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2301469                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2301454                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2303097                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2303082                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27613                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27613                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           686960                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36226                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2751                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           686899                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2744                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2753                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295908                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295908                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3415392                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2457281                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18122                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34351                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5925146                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108750520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96868901                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24732                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        46156                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              205690309                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           53730                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3283144                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.011105                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.104794                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp           2746                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295999                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295999                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3418625                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2457116                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18180                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34622                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5928543                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108853880                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96862117                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24836                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        46784                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205787617                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           53694                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3284793                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.011099                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.104766                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3246684     98.89%     98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                  36460      1.11%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3248335     98.89%     98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                  36458      1.11%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3283144                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4418882248                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3284793                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4419462750                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           985500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        7658490749                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        7665779999                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3782924511                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3782690745                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11939000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11971000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          22834207                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          22951201                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 864e98054..ecc4cd446 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,165 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.349475                       # Number of seconds simulated
-sim_ticks                                47349475204500                       # Number of ticks simulated
-final_tick                               47349475204500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.349389                       # Number of seconds simulated
+sim_ticks                                47349388766500                       # Number of ticks simulated
+final_tick                               47349388766500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 170024                       # Simulator instruction rate (inst/s)
-host_op_rate                                   200007                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9521770968                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 827688                       # Number of bytes of host memory used
-host_seconds                                  4972.76                       # Real time elapsed on the host
-sim_insts                                   845490438                       # Number of instructions simulated
-sim_ops                                     994586036                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 148460                       # Simulator instruction rate (inst/s)
+host_op_rate                                   174619                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7799944718                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 883812                       # Number of bytes of host memory used
+host_seconds                                  6070.48                       # Real time elapsed on the host
+sim_insts                                   901223526                       # Number of instructions simulated
+sim_ops                                    1060022042                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        457024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       242432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       409152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst         13269720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     28432512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       254656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       419648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst         10291040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     23441792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             77217976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3825664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       566400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4392064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     33722560                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6830592                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.inst      56250828                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst      43534148                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         140338128                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           7141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         3788                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         6393                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            207361                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       444258                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3979                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         6557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst            160812                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       366278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1206567                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          526915                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106728                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.inst           881196                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst           680222                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2195061                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             9652                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          5120                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          8641                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              280251                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       600482                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          5378                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8863                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              217342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       495080                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1630810                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          80796                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          11962                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              92758                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            712206                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          144259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst            1187993                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst             919422                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2963879                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            712206                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          153911                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         5120                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         8641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst            1468243                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       600482                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         5378                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8863                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            1136764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       495080                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4594689                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1206567                       # Number of read requests accepted
-system.physmem.writeReqs                      2195061                       # Number of write requests accepted
-system.physmem.readBursts                     1206567                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2195061                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 76928704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    291584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 135133184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  77217976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              140338128                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     4556                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   83588                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          93227                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               68916                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               78372                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               66961                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74483                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               67860                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               84994                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               78873                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74831                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               70689                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              121049                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              55712                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              71204                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              68805                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              80552                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              71313                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              67397                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              131295                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              120115                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              136218                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              122111                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              136290                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              134780                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              183921                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              113990                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              112648                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              120303                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             105255                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             150368                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             133266                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             132701                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             112511                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             165684                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker       126592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       108352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst         12219800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     55224576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       171840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       160768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst         11630176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     36221056                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        451968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            116315128                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4075008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       659840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4734848                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     84862912                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.inst         20812                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.inst             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          84883728                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1978                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            190956                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       862884                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2685                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2512                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst            181736                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       565954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           7062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1817460                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1325983                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.inst             2602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.inst                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1328586                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2674                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2288                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              258077                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      1166321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3629                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              245625                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       764974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2456529                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          86063                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          13936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              99998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1792270                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst                440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.inst                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1792710                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1792270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2288                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             258517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      1166321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3629                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             245625                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       764974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4249239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1817460                       # Number of read requests accepted
+system.physmem.writeReqs                      1459105                       # Number of write requests accepted
+system.physmem.readBursts                     1817460                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1459105                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                116259968                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     57472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  92884608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 116315128                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               93236944                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      898                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7766                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          92270                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              109521                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              125500                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              109858                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118807                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              114750                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              133958                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              108183                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              109296                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              104951                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              157608                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              96466                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             111139                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             103753                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             116262                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              95073                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             101437                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               88391                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               94888                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               89089                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               94540                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               92096                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              104028                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               87215                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               89925                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               85891                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               90043                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              85085                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              94536                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              86659                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              94890                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              85144                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              88902                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47349473266500                       # Total gap between requests
+system.physmem.totGap                    47349386828500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1206525                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1817418                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2192458                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    701586                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    159041                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     78388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     62534                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     48409                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     42357                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     36825                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     30566                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     24739                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      6356                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     3319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2365                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1772                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1348                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      953                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      286                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      212                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1456502                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -183,158 +180,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       691339                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      306.739519                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.472793                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.323128                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         329714     47.69%     47.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       128094     18.53%     66.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        46159      6.68%     72.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24419      3.53%     76.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        20272      2.93%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13585      1.97%     81.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10457      1.51%     82.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        11430      1.65%     84.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       107209     15.51%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         691339                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         99075                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.132152                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      222.564559                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          99072    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-59391            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           99075                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         99075                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.311693                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.731664                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.258880                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           33791     34.11%     34.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23           48957     49.41%     83.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27           10331     10.43%     93.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            2038      2.06%     96.01% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::76-79              38      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              24      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.00%     99.94% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total           99075                       # Writes before turning the bus around for reads
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-system.physmem.totMemAccLat               55002186524                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6010055000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27008.47                       # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::total         894898                       # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::0-1023          77788    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::total           77790                       # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::total           77790                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   101322311265                       # Total ticks spent queuing
+system.physmem.totMemAccLat              135382848765                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9082810000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       55776.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45758.47                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.62                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.63                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.96                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  74526.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.46                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.96                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.46                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.40                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     944165                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1677959                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.47                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13919650.61                       # Average gap between requests
-system.physmem.pageHitRate                      79.13                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     45391806829500                       # Time in different power states
-system.physmem.memoryStateTime::REF      1581102900000                       # Time in different power states
+system.physmem.avgWrQLen                        27.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1479200                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    893785                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  61.58                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14450922.48                       # Average gap between requests
+system.physmem.pageHitRate                      72.61                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     45452153624500                       # Time in different power states
+system.physmem.memoryStateTime::REF      1581100040000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      376561525500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      316134376000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2682083880                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2544438960                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1463438625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1388334750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               4643184000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               4732392600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              6990105600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              6692129280                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3092637272400                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3092637272400                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1220178523320                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1215644323230                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          27339350706750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          27343328075250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            31667945314575                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            31666966966470                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.813072                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.792410                       # Core power per rank (mW)
+system.physmem.actEnergy::0                3577346640                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                3188082240                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1951925250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1739529000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               7253009400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               6916111800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              4796314560                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              4608252000                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3092631678240                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3092631678240                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1196963299980                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1185023558430                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          27359663548500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          27370137006000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            31666837122570                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            31664244217710                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.790877                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.736116                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          584                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
@@ -353,703 +348,22 @@ system.realview.nvmem.bw_inst_read::total           27                       # I
 system.realview.nvmem.bw_total::cpu0.inst           16                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           12                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              28                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq             1114990                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1114990                       # Transaction distribution
-system.membus.trans_dist::WriteReq              37937                       # Transaction distribution
-system.membus.trans_dist::WriteResp             37937                       # Transaction distribution
-system.membus.trans_dist::Writeback            526915                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1665543                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1665543                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           343558                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         290459                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           93233                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145423                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131308                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122918                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        23584                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6789962                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6936516                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229526                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       229526                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7166042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        47168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    210268488                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    210473028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7287616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7287616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               217760644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           556693                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3996553                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3996553    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3996553                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106711482                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               35984                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20060995                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         21791270978                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        13392760110                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          187374753                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   893379                       # number of replacements
-system.l2c.tags.tagsinuse                64139.353797                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6866398                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   953433                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     7.201762                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   10411.534254                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   170.665758                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   236.653363                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5522.014615                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   145.004713                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   188.005532                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     6322.307070                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.158867                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002604                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003611                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.084259                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.392204                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002213                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.002869                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.096471                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.235591                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.978689                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        36012                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          260                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        23782                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1           41                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          716                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1957                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        33290                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           51                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          190                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          112                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1450                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3907                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        18298                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.549500                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003967                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.362885                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 80317062                       # Number of tag accesses
-system.l2c.tags.data_accesses                80317062                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         7070                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4466                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             557041                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      2033838                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         7318                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         4580                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             521752                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1881001                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                5017066                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1844732                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1844732                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.inst           30097                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst           27244                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               57341                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst          7329                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst          7124                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             14453                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.inst            51408                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst            52005                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               103413                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          7070                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4466                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              608449                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher      2033838                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          7318                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4580                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              573757                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher      1881001                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 5120479                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         7070                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4466                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             608449                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher      2033838                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         7318                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4580                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             573757                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher      1881001                       # number of overall hits
-system.l2c.overall_hits::total                5120479                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         3788                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         6393                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            87512                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       444466                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         3979                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         6557                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            97026                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       366468                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total              1016189                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.inst         36620                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.inst         34601                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             71221                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.inst         9478                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.inst         8512                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           17990                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.inst          69660                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.inst          65667                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             135327                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3788                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         6393                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst            157172                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       444466                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         3979                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         6557                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst            162693                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       366468                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1151516                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3788                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         6393                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst           157172                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       444466                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         3979                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         6557                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst           162693                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       366468                       # number of overall misses
-system.l2c.overall_misses::total              1151516                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    295641239                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    507564744                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   6935191428                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  45326284922                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    312400496                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    512318742                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   7688372365                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  38103566034                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    99681339970                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.inst    177719564                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.inst    161535756                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    339255320                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.inst     49426933                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.inst     49799411                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     99226344                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.inst   5124274653                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.inst   4787449538                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9911724191                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    295641239                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    507564744                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst  12059466081                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  45326284922                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    312400496                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    512318742                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst  12475821903                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  38103566034                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    109593064161                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    295641239                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    507564744                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst  12059466081                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  45326284922                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    312400496                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    512318742                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst  12475821903                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  38103566034                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   109593064161                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        10858                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        10859                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         644553                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2478304                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        11297                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        11137                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         618778                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2247469                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            6033255                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1844732                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1844732                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.inst        66717                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.inst        61845                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          128562                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.inst        16807                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.inst        15636                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         32443                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.inst       121068                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.inst       117672                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           238740                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10858                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        10859                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          765621                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2478304                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        11297                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        11137                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          736450                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2247469                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             6271995                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10858                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        10859                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         765621                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2478304                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        11297                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        11137                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         736450                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2247469                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            6271995                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.348867                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.588728                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.135772                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.179343                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.352217                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.588758                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.156803                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.163058                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.168431                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.548886                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.559479                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.553982                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.563932                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.544385                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.554511                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.inst     0.575379                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.inst     0.558051                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.566838                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.348867                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.588728                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.205287                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.179343                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.352217                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.588758                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.220915                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.163058                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.183596                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.348867                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.588728                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.205287                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.179343                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.352217                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.588758                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.220915                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.163058                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.183596                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78046.789599                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79393.828250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79248.462245                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78512.313647                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78133.100808                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79240.331097                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 98093.307416                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  4853.073839                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  4668.528540                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4763.416970                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  5214.911690                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  5850.494713                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5515.638911                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 73561.220973                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 72904.952838                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73242.768930                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78046.789599                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79393.828250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76727.827355                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78512.313647                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78133.100808                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 76683.212572                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 95172.854012                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78046.789599                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79393.828250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76727.827355                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78512.313647                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78133.100808                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 76683.212572                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 95172.854012                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              9985                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      293                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     34.078498                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              526915                       # number of writebacks
-system.l2c.writebacks::total                   526915                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst            41                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          208                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            31                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          190                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               470                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             41                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          208                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             31                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          190                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                470                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            41                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          208                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            31                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          190                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               470                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         3788                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         6393                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        87471                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       444258                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         3979                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         6557                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        96995                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       366278                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total         1015719                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst        36620                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst        34601                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        71221                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst         9478                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         8512                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        17990                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst        69660                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.inst        65667                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        135327                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3788                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         6393                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst       157131                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       444258                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         3979                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         6557                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst       162662                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       366278                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1151046                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3788                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         6393                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst       157131                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       444258                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         3979                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         6557                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst       162662                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       366278                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1151046                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    248599239                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    428022244                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   5837610680                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39831799422                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    262923496                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    430600242                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   6471220731                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  33572512037                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  87083288091                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  17889181875                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst  13903512484                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total  31792694359                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst    372768590                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst    351692080                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    724460670                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst     96695300                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     86940850                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    183636150                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   4247852269                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   3960733380                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8208585649                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    248599239                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    428022244                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst  10085462949                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39831799422                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    262923496                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    430600242                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst  10431954111                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  33572512037                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  95291873740                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    248599239                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    428022244                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst  10085462949                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39831799422                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    262923496                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    430600242                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst  10431954111                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  33572512037                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  95291873740                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4946669501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   3170681000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8117350501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   2118382500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst   3125324001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5243706501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   7065052001                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   6296005001                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13361057002                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.348867                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.588728                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.135708                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.179259                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.352217                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.588758                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.156753                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.162974                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.168353                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.548886                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.559479                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.553982                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.563932                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.544385                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.554511                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.575379                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.558051                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.566838                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.348867                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.588728                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.205233                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.179259                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.352217                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.588758                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.220873                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.162974                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.183522                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.348867                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.588728                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.205233                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.179259                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.352217                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.588758                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.220873                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.162974                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.183522                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 82787.198548                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 82787.198548                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            6929805                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           6922247                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             37937                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            37937                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1844732                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1665553                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1558815                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          396880                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        304912                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         701792                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          122                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          122                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           286652                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          286652                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10302950                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9169444                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              19472394                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    332778181                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    290120831                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              622899012                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1503135                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         11338555                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.010201                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.100485                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               11222888     98.98%     98.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115667      1.02%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           11338555                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        19325316227                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          6157500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       17505808152                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       16090621161                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40386                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40386                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136543                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136730                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq          187                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48036                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122918                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231234                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231234                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354232                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48056                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156048                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7497086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36503000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           982100345                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92919000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179226247                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups              130284886                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         91971902                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5996877                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            97983342                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               71203631                       # Number of BTB hits
+system.cpu0.branchPred.lookups              127854962                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         91169153                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5795491                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            97464931                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               70565780                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.669119                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15456951                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1030979                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.401200                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               14662444                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            979053                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1073,25 +387,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    84560824                       # DTB read hits
-system.cpu0.dtb.read_misses                    213472                       # DTB read misses
-system.cpu0.dtb.write_hits                   73762718                       # DTB write hits
-system.cpu0.dtb.write_misses                    44801                       # DTB write misses
+system.cpu0.dtb.read_hits                    80634882                       # DTB read hits
+system.cpu0.dtb.read_misses                    217470                       # DTB read misses
+system.cpu0.dtb.write_hits                   71942682                       # DTB write hits
+system.cpu0.dtb.write_misses                    47848                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              38216                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   35801                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1794                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7921                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34852                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1874                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8493                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10648                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                84774296                       # DTB read accesses
-system.cpu0.dtb.write_accesses               73807519                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    11561                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                80852352                       # DTB read accesses
+system.cpu0.dtb.write_accesses               71990530                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        158323542                       # DTB hits
-system.cpu0.dtb.misses                         258273                       # DTB misses
-system.cpu0.dtb.accesses                    158581815                       # DTB accesses
+system.cpu0.dtb.hits                        152577564                       # DTB hits
+system.cpu0.dtb.misses                         265318                       # DTB misses
+system.cpu0.dtb.accesses                    152842882                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1113,93 +427,294 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   233888906                       # ITB inst hits
-system.cpu0.itb.inst_misses                     61464                       # ITB inst misses
+system.cpu0.itb.inst_hits                   228743332                       # ITB inst hits
+system.cpu0.itb.inst_misses                     63317                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              38216                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   25786                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24510                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   208811                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   202277                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               233950370                       # ITB inst accesses
-system.cpu0.itb.hits                        233888906                       # DTB hits
-system.cpu0.itb.misses                          61464                       # DTB misses
-system.cpu0.itb.accesses                    233950370                       # DTB accesses
-system.cpu0.numCycles                       883850249                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               228806649                       # ITB inst accesses
+system.cpu0.itb.hits                        228743332                       # DTB hits
+system.cpu0.itb.misses                          63317                       # DTB misses
+system.cpu0.itb.accesses                    228806649                       # DTB accesses
+system.cpu0.numCycles                       867293351                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  434327088                       # Number of instructions committed
-system.cpu0.committedOps                    509859279                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     43671037                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     5040                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93815840018                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.034988                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.491403                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  417325536                       # Number of instructions committed
+system.cpu0.committedOps                    490736323                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     44793539                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4342                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93832115526                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.078218                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.481182                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5406                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      675499590                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      208350659                       # Total number of cycles that the object has spent stopped
-system.cpu0.icache.tags.replacements          9024677                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.937426                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          224649292                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9025189                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.891367                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      16724996500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.937426                       # Average occupied blocks per requestor
+system.cpu0.kern.inst.quiesce                    4790                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      682045150                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      185248201                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5375859                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          504.387778                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          144555742                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5376371                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            26.887233                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       4951320000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   504.387778                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.985132                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.985132                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        308078040                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       308078040                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst     74032777                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       74032777                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst     66638302                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      66638302                       # number of WriteReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst       115191                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       115191                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst      1688442                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1688442                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.inst      1614699                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1614699                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst    140671079                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       140671079                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst    140671079                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      140671079                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst      3863790                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3863790                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst      2319255                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2319255                       # number of WriteReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst       742685                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       742685                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst       105957                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       105957                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst       178436                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       178436                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst      6183045                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6183045                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst      6183045                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6183045                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst  54382834533                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54382834533                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  36195221997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36195221997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst  21037893950                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  21037893950                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst   1466052740                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   1466052740                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst   3737583856                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3737583856                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst      3062000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3062000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  90578056530                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  90578056530                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  90578056530                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  90578056530                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst     77896567                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     77896567                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst     68957557                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     68957557                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst       857876                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total       857876                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst      1794399                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1794399                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst      1793135                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1793135                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst    146854124                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    146854124                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst    146854124                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    146854124                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.049602                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.049602                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.033633                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.033633                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst     0.865725                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.865725                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.059049                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059049                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.099511                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099511                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.042103                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.042103                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.042103                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.042103                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14649.425409                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14649.425409                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks      3741617                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3741617                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst       374932                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       374932                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       967778                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       967778                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst           26                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total           26                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           53                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total           53                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst           76                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           76                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst      1342710                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1342710                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst      1342710                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1342710                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst      3488858                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3488858                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst      1351477                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1351477                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst       742659                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       742659                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst       105904                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       105904                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst       178360                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       178360                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst      4840335                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4840335                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst      4840335                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4840335                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst  42020078260                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42020078260                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst  19120911908                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  19120911908                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  19537847050                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  19537847050                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst   1252614238                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1252614238                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst   3369767592                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3369767592                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst      2341000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2341000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst  61140990168                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  61140990168                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst  61140990168                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  61140990168                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2949307890                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2949307890                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   3070097397                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3070097397                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst   6019405287                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6019405287                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.044788                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.044788                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.019599                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019599                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.865695                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.865695                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.059019                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059019                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.099468                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099468                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.032960                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032960                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.032960                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032960                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements          8781546                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.937582                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          219752565                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          8782058                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            25.022901                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      16633914000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.937582                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999878                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999878                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        476374153                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       476374153                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    224649292                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      224649292                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    224649292                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       224649292                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    224649292                       # number of overall hits
-system.cpu0.icache.overall_hits::total      224649292                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9025190                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9025190                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9025190                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9025190                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9025190                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9025190                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  76329373412                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  76329373412                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  76329373412                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  76329373412                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  76329373412                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  76329373412                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    233674482                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    233674482                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    233674482                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    233674482                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    233674482                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    233674482                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038623                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.038623                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038623                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.038623                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038623                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.038623                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8457.370251                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8457.370251                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8457.370251                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8457.370251                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8457.370251                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8457.370251                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        465851331                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       465851331                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    219752565                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      219752565                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    219752565                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       219752565                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    219752565                       # number of overall hits
+system.cpu0.icache.overall_hits::total      219752565                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8782067                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      8782067                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8782067                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       8782067                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8782067                       # number of overall misses
+system.cpu0.icache.overall_misses::total      8782067                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  75181971221                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  75181971221                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  75181971221                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  75181971221                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  75181971221                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  75181971221                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    228534632                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    228534632                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    228534632                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    228534632                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    228534632                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    228534632                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038428                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.038428                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038428                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.038428                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038428                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.038428                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8560.851474                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8560.851474                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8560.851474                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8560.851474                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8560.851474                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8560.851474                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1208,384 +723,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9025190                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9025190                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9025190                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9025190                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9025190                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9025190                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62781832574                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  62781832574                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62781832574                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  62781832574                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62781832574                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  62781832574                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4713380500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4713380500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4713380500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   4713380500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038623                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038623                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038623                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.038623                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038623                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.038623                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6956.289294                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6956.289294                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6956.289294                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  6956.289294                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6956.289294                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  6956.289294                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8782067                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      8782067                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8782067                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      8782067                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8782067                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      8782067                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  61997855741                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  61997855741                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  61997855741                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  61997855741                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  61997855741                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  61997855741                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4713229500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4713229500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4713229500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   4713229500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038428                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.038428                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.038428                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7059.597216                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  7059.597216                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  7059.597216                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      16744363                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     13538941                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        16377                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16377                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      2993146                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      4286145                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1665553                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       878594                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       389729                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       340122                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       446153                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           67                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          122                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1234377                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1099479                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18154960                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15139641                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       334891                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1016427                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         34645919                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    580958656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    555417413                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1211560                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3676024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1141263653                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    9180766                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     27586114                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.321691                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.467125                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          18711910     67.83%     67.83% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6           8874204     32.17%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      27586114                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   13279117937                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    196246989                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  13633302169                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7744080967                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    184135419                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    557460915                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     80006652                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      1538976                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     75387543                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        49644                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     84003023                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      4398912                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     74572645                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      1090360                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2517                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      3027964                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      6795468                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       154166                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      3786940                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      6742713                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         3295318                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16239.521092                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          15183735                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3311433                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            4.585246                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     14515776000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  5108.942549                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.019654                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    70.169979                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2735.324727                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8261.064181                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.311825                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003907                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004283                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.166951                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.504215                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.991182                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022        10731                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         5301                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.replacements         4037603                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16229.874548                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          15269588                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         4053811                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.766724                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     14918796500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  3465.639505                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    40.958286                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    27.625357                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2577.016988                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.211526                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002500                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001686                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.157289                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.617592                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.990593                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022        10250                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         5866                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1022::0          116                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          730                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2564                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4307                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         3014                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           30                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          447                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         1426                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2059                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1321                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.654968                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.323547                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       302494843                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      302494843                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       445653                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       140462                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst     11717958                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total      12304073                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      2993146                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      2993146                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst        70651                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        70651                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst        35155                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        35155                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       863705                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       863705                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       445653                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       140462                       # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       140462                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst     12581663                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      13167778                       # number of overall hits
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-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       913042                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       937875                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst       117562                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       117562                       # number of UpgradeReq misses
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-system.cpu0.l2cache.SCUpgradeReq_misses::total       153389                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            3                       # number of SCUpgradeFailReq misses
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-system.cpu0.l2cache.ReadExReq_misses::total       228005                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13850                       # number of demand (read+write) misses
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-system.cpu0.l2cache.demand_misses::total      1165880                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13850                       # number of overall misses
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-system.cpu0.l2cache.overall_misses::cpu0.inst      1141047                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1165880                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    571410377                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    698481694                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  26359609041                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  27629501112                       # number of ReadReq miss cycles
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2365914343                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst   3101977603                       # number of SCUpgradeReq miss cycles
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-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst      2176500                       # number of SCUpgradeFailReq miss cycles
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-system.cpu0.l2cache.ReadExReq_miss_latency::total   9967705721                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    571410377                       # number of demand (read+write) miss cycles
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-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  36327314762                       # number of demand (read+write) miss cycles
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-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    571410377                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    698481694                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  36327314762                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  37597206833                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       459503                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       151445                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst     12631000                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total     13241948                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      2993146                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      2993146                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst       188213                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       188213                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst       188544                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            3                       # number of SCUpgradeFailReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst      1091710                       # number of ReadExReq accesses(hits+misses)
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-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       151445                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst     13722710                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     14333658                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.030141                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.072521                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.072286                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.070826                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.624622                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.624622                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.813545                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.813545                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1         1048                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         4016                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         3415                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1655                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           22                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          525                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2441                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1975                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          887                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.625610                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.358032                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       311163440                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      311163440                       # Number of data accesses
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+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst  15916059245                       # number of WriteInvalidateReq miss cycles
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+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2454108805                       # number of UpgradeReq miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    354751936                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  37233240764                       # number of overall miss cycles
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+system.cpu0.l2cache.ReadReq_accesses::total     13018213                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3741617                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3741617                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst       741495                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::total       741495                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::total       210011                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst       178353                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       157455                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.076529                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.074597                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst     0.602096                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.602096                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.588388                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.588388                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.795546                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.795546                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.208851                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.208851                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.030141                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.072521                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.083150                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.081339                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.030141                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.072521                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.083150                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.081339                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41257.066931                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63596.621506                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 28870.094739                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29459.683979                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20124.822162                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20124.822162                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20222.946906                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.946906                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst       725500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       725500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 43717.048841                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 43717.048841                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41257.066931                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63596.621506                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31836.825969                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 32247.921598                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41257.066931                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63596.621506                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31836.825969                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 32247.921598                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        62612                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.202559                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.202559                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.087183                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.084924                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.087183                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.084924                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33170.077966                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35165.735131                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29995.762038                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30094.788093                       # average ReadReq miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35650.181644                       # average WriteInvalidateReq miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19860.391080                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20244.625846                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.625846                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 326285.714286                       # average SCUpgradeFailReq miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33170.077966                       # average overall miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31589.359448                       # average overall miss latency
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+system.cpu0.l2cache.blocked_cycles::no_mshrs       196093                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            1060                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs            2541                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    59.067925                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    77.171586                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1001402                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1001402                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        72428                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total        72428                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         6233                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         6233                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        78661                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        78661                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        78661                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        78661                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13850                       # number of ReadReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       840614                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total       865447                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      3027916                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total      3027916                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst       117562                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       117562                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst       153389                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       153389                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst       221772                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       221772                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13850                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10983                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst      1062386                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13850                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst      1062386                       # number of overall MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    473721015                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  19074448661                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  20168472472                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  79252881469                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  79252881469                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  33127814392                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  33127814392                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst   2005449750                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2005449750                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst   2118741906                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2118741906                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst      1770500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1770500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   7853083593                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   7853083593                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    473721015                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    620302796                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  26927532254                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    473721015                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total 107274437534                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6580252048                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6580252048                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   2399021553                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2399021553                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   8979273601                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8979273601                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.030141                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.072521                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.066552                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.065356                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.writebacks::writebacks      1602519                       # number of writebacks
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123568                       # number of UpgradeReq MSHR misses
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+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst   1410635970                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total   1410635970                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst   2082130886                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2082130886                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst   1980278880                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst      1885000                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   6408519883                       # number of ReadExReq MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  26906727163                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total 195992157308                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6920870357                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6920870357                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   2922560102                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2922560102                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   9843430459                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9843430459                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.070068                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.068454                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.624622                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.624622                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.813545                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.813545                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.085266                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.085266                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.588388                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.588388                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.795546                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.795546                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.203142                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.203142                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.030141                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.072521                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.077418                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075851                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.030141                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.072521                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.077418                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.194529                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.194529                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.080589                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.078629                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.080589                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.287096                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22691.090870                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23304.110445                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 26174.068722                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17058.656283                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17058.656283                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13812.867324                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13812.867324                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 590166.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590166.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35410.618081                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35410.618081                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25346.279275                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25773.607769                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25346.279275                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 26068.266906                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.346044                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1593,202 +1077,68 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          5337320                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          473.198574                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          150291577                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5337832                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.155921                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       4951320000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   473.198574                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.924216                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.924216                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          374                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        319289852                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       319289852                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst     77767484                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77767484                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst     68524145                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      68524145                       # number of WriteReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst       878594                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       878594                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst      1744720                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1744720                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst      1671495                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1671495                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst    146291629                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       146291629                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst    146291629                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      146291629                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst      3855307                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3855307                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst      2180509                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2180509                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst       116717                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       116717                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst       188600                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       188600                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst      6035816                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6035816                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst      6035816                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6035816                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst  52949262121                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  52949262121                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  36682258766                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36682258766                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst   1582680255                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   1582680255                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst   3978646923                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3978646923                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst      2553000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2553000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  89631520887                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  89631520887                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  89631520887                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  89631520887                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst     81622791                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     81622791                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst     70704654                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     70704654                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst       878594                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total       878594                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst      1861437                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1861437                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst      1860095                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1860095                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst    152327445                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    152327445                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst    152327445                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    152327445                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.047233                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.047233                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030840                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.030840                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.062703                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.062703                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.101393                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.101393                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.039624                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.039624                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.039624                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.039624                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                 878594                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      2993146                       # number of writebacks
-system.cpu0.dcache.writebacks::total          2993146                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst       365860                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       365860                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       900170                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       900170                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           65                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total           65                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst           53                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           53                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst      1266030                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1266030                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst      1266030                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1266030                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst      3489447                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3489447                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst      1279618                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1279618                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst       116652                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116652                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst       188547                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       188547                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst      4769065                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4769065                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst      4769065                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4769065                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst  40912958493                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40912958493                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst  19695838269                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  19695838269                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  39725259601                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  39725259601                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst   1347811737                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1347811737                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst   3591126546                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3591126546                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst      2234500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2234500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst  60608796762                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  60608796762                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst  60608796762                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  60608796762                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2590105703                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2590105703                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   2521930197                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2521930197                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst   5112035900                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5112035900                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.042751                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.042751                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.018098                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018098                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.062668                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062668                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.101364                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.101364                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.031308                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.031308                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.031308                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031308                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              124419206                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         87805046                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6051921                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            92935126                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               66733716                       # Number of BTB hits
+system.cpu0.toL2Bus.trans_dist::ReadReq      17406363                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13329872                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19688                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19687                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      3741617                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      5530609                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       862152                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       741495                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       486160                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       325301                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       465486                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           67                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1278141                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1152631                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17668715                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15752783                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       346532                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1063511                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         34831541                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    565398848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    598192623                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1259640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3873096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1168724207                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   10729638                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     29561564                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.351841                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.477545                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          19160579     64.82%     64.82% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6          10400985     35.18%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total      29561564                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14119794312                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    225496496                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy  13269247990                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy   7748577182                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy    189385144                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy    579874631                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.cpu1.branchPred.lookups              146637664                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted        104244557                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6464776                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           109760718                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               80092874                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.806774                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               14888837                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1052333                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.970436                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17287162                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1125459                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1812,25 +1162,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    80858392                       # DTB read hits
-system.cpu1.dtb.read_misses                    227532                       # DTB read misses
-system.cpu1.dtb.write_hits                   71539111                       # DTB write hits
-system.cpu1.dtb.write_misses                    46368                       # DTB write misses
+system.cpu1.dtb.read_hits                    95196820                       # DTB read hits
+system.cpu1.dtb.read_misses                    258683                       # DTB read misses
+system.cpu1.dtb.write_hits                   82774540                       # DTB write hits
+system.cpu1.dtb.write_misses                    48918                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              38216                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   35324                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1220                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8196                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   40938                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1166                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8454                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10514                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                81085924                       # DTB read accesses
-system.cpu1.dtb.write_accesses               71585479                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11190                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                95455503                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82823458                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        152397503                       # DTB hits
-system.cpu1.dtb.misses                         273900                       # DTB misses
-system.cpu1.dtb.accesses                    152671403                       # DTB accesses
+system.cpu1.dtb.hits                        177971360                       # DTB hits
+system.cpu1.dtb.misses                         307601                       # DTB misses
+system.cpu1.dtb.accesses                    178278961                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1852,92 +1202,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   221287255                       # ITB inst hits
-system.cpu1.itb.inst_misses                     68040                       # ITB inst misses
+system.cpu1.itb.inst_hits                   262373201                       # ITB inst hits
+system.cpu1.itb.inst_misses                     66107                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              38216                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   25097                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   29545                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202601                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   222220                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               221355295                       # ITB inst accesses
-system.cpu1.itb.hits                        221287255                       # DTB hits
-system.cpu1.itb.misses                          68040                       # DTB misses
-system.cpu1.itb.accesses                    221355295                       # DTB accesses
-system.cpu1.numCycles                       841372178                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               262439308                       # ITB inst accesses
+system.cpu1.itb.hits                        262373201                       # DTB hits
+system.cpu1.itb.misses                          66107                       # DTB misses
+system.cpu1.itb.accesses                    262439308                       # DTB accesses
+system.cpu1.numCycles                       965776076                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  411163350                       # Number of instructions committed
-system.cpu1.committedOps                    484726757                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     42974941                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4643                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93858235376                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.046321                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.488682                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  483897990                       # Number of instructions committed
+system.cpu1.committedOps                    569285719                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     49152054                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5850                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93733878410                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              1.995826                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.501046                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13250                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      646022417                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      195349761                       # Total number of cycles that the object has spent stopped
-system.cpu1.icache.tags.replacements          9199343                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.111645                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          211878543                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9199855                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            23.030639                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8364993861000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.111645                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990452                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990452                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   14403                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      777604637                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      188171439                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5691678                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          432.252247                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          169393329                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5692190                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.758903                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8364525946500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   432.252247                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.844243                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.844243                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        358720623                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       358720623                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst     87552380                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       87552380                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst     77214593                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      77214593                       # number of WriteReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst       211985                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total       211985                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst      1994962                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1994962                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst      1944639                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1944639                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst    164766973                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       164766973                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst    164766973                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      164766973                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst      4362572                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      4362572                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst      2362737                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2362737                       # number of WriteReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst       497251                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       497251                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst       139927                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       139927                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst       188742                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       188742                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst      6725309                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       6725309                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst      6725309                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6725309                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst  63153941750                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  63153941750                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst  37295206516                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  37295206516                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst   9223332559                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total   9223332559                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst   1921743254                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   1921743254                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst   3886161820                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3886161820                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst      3267000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3267000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 100449148266                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 100449148266                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst     91914952                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     91914952                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst     79577330                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     79577330                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst       709236                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       709236                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst      2134889                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2134889                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst      2133381                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2133381                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst    171492282                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    171492282                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst    171492282                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    171492282                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.047463                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.047463                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.029691                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.029691                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst     0.701108                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.701108                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.065543                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.065543                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.088471                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.088471                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.039216                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.039216                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.039216                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.039216                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks      3739270                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3739270                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst       400087                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       400087                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst       959724                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       959724                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst           47                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           47                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           67                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst           75                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           75                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst      1359811                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1359811                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst      1359811                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1359811                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst      3962485                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3962485                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst      1403013                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1403013                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst       497204                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       497204                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst       139860                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       139860                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst       188667                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       188667                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst      5365498                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      5365498                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst      5365498                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5365498                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst  49100377691                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  49100377691                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst  20233474919                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20233474919                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   8220345441                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total   8220345441                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst   1640188222                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1640188222                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst   3498307132                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3498307132                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst      2504000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2504000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst  69333852610                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  69333852610                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst  69333852610                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  69333852610                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3411173732                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3411173732                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst   3123925989                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3123925989                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst   6535099721                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6535099721                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.043110                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043110                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.017631                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017631                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.701042                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.701042                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.065512                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065512                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.088436                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.088436                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.031287                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031287                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.031287                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031287                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements         10003641                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          507.113561                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          252141010                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs         10004153                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.203634                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8364450905000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.113561                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990456                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990456                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        451356678                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       451356678                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    211878543                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      211878543                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    211878543                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       211878543                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    211878543                       # number of overall hits
-system.cpu1.icache.overall_hits::total      211878543                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9199864                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9199864                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9199864                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9199864                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9199864                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9199864                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  77780449816                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  77780449816                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  77780449816                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  77780449816                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  77780449816                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  77780449816                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    221078407                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    221078407                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    221078407                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    221078407                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    221078407                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    221078407                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.041614                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.041614                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.041614                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.041614                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.041614                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.041614                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8454.521699                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8454.521699                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8454.521699                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8454.521699                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8454.521699                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8454.521699                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        534294484                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       534294484                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    252141010                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      252141010                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    252141010                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       252141010                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    252141010                       # number of overall hits
+system.cpu1.icache.overall_hits::total      252141010                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst     10004155                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total     10004155                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst     10004155                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total      10004155                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst     10004155                       # number of overall misses
+system.cpu1.icache.overall_misses::total     10004155                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  85019530358                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  85019530358                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  85019530358                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  85019530358                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  85019530358                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  85019530358                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    262145165                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    262145165                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    262145165                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    262145165                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    262145165                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    262145165                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038163                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.038163                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038163                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.038163                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038163                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.038163                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8498.421941                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8498.421941                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8498.421941                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8498.421941                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8498.421941                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8498.421941                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1946,380 +1498,353 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9199864                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9199864                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9199864                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9199864                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9199864                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9199864                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  63970402202                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  63970402202                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  63970402202                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  63970402202                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  63970402202                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  63970402202                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8551999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8551999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8551999                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8551999                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.041614                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.041614                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.041614                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.041614                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.041614                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.041614                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6953.407377                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6953.407377                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6953.407377                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6953.407377                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6953.407377                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6953.407377                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst     10004155                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total     10004155                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst     10004155                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total     10004155                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst     10004155                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total     10004155                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  70001431618                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  70001431618                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  70001431618                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  70001431618                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  70001431618                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  70001431618                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8751000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8751000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8751000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8751000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038163                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.038163                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.038163                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6997.235810                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  6997.235810                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  6997.235810                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      16974832                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13523495                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        21560                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        21560                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      2756922                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      3912463                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1665553                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       680221                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       382477                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       337171                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       432582                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          122                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1151878                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1012928                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18399906                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     13962178                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       374507                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1077414                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         33814005                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    588796992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    509690879                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1369000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3931224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1103788095                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    9217690                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     27159033                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.328913                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.469818                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          18226076     67.11%     67.11% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6           8932957     32.89%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      27159033                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   12584209028                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    175099992                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  13805070808                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7247611234                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    204139691                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    586587181                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     79358164                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      1355061                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     75203006                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        49096                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     91266400                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2590593                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     83739964                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      1124296                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         3073                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2747928                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      6733876                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       159143                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      3652396                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      7945944                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         3063828                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13784.638052                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          15005563                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         3079680                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            4.872442                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9994842368500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  2928.842366                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    67.432287                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    61.914602                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2764.974382                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  7961.474415                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.178762                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004116                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003779                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.168761                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.485930                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.841348                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9851                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023          102                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5899                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          232                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         4639                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         3547                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1433                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           75                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2951                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2204                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          483                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.601257                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006226                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.360046                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       294450591                       # Number of tag accesses
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-system.cpu1.l2cache.ReadReq_hits::total      12364311                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      2756922                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      2756922                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst        68490                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        68490                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst        32200                       # number of SCUpgradeReq hits
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-system.cpu1.l2cache.overall_hits::total      13141267                       # number of overall hits
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-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       893170                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total       918610                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst       118620                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       118620                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst       151637                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       151637                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst            5                       # number of SCUpgradeFailReq misses
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-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        14150                       # number of overall misses
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-system.cpu1.l2cache.overall_misses::cpu1.inst      1124107                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1149547                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    593312131                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    709102173                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  26528840524                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  27831254828                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst   2374329628                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2374329628                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst   3078262421                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3078262421                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst      2493000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2493000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   9672285471                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   9672285471                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    593312131                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    709102173                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  36201125995                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  37503540299                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    593312131                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    709102173                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  36201125995                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  37503540299                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       491403                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst     12620393                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total     13282921                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      2756922                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      2756922                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst       187110                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       187110                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst       183837                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       183837                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst      1007893                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1007893                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       491403                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.demand_accesses::cpu1.inst     13628286                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       171125                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst     13628286                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     14290814                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.028795                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065975                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.070772                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.069157                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.633959                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.633959                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.824845                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.824845                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.replacements         3964575                       # number of replacements
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+system.cpu1.l2cache.tags.total_refs          17209014                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         3980703                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.323109                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9604482251250                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  4186.861890                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.243250                       # Average occupied blocks per requestor
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2902.209445                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6553.391387                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.255546                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_percent::total     0.840559                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6309                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         3317                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1554                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3097                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          531                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002563                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.385071                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.tags.data_accesses      336896441                       # Number of data accesses
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+system.cpu1.l2cache.ReadReq_hits::total      13741045                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3739269                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3739269                       # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst       314994                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total       314994                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst        88927                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        88927                       # number of UpgradeReq hits
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+system.cpu1.l2cache.overall_hits::total      14685430                       # number of overall hits
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+system.cpu1.l2cache.UpgradeReq_misses::total       132678                       # number of UpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst            6                       # number of SCUpgradeFailReq misses
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+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        14704                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10320                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst      1301238                       # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.inst      1301238                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1326262                       # number of overall misses
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+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  33089400106                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total  34029256940                       # number of ReadReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst   5173608568                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total   5173608568                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst   2603383383                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2603383383                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst   2990869344                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2990869344                       # number of SCUpgradeReq miss cycles
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+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  42613801105                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  42613801105                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  43553657939                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       560431                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       161995                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst     14106151                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total     14828577                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3739269                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3739269                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst       495851                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total       495851                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst       221605                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       221605                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst       188661                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       188661                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst      1183115                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1183115                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       560431                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       161995                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst     15289266                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     16011692                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       560431                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       161995                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst     15289266                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     16011692                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.075322                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.073340                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst     0.364741                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.364741                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.598714                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.598714                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.779186                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.779186                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.229128                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.229128                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.028795                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065975                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.082483                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.080440                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.028795                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065975                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.082483                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.080440                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41930.185936                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62807.986980                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29701.893843                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30297.138969                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20016.267307                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20016.267307                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20300.206552                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20300.206552                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst       498600                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       498600                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41882.788254                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41882.788254                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41930.185936                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62807.986980                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32204.341753                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32624.625439                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41930.185936                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62807.986980                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32204.341753                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32624.625439                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs        62499                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.201781                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.201781                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.085108                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.082831                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.085108                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.082831                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35754.565016                       # average ReadReq miss latency
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31142.730319                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31290.350022                       # average ReadReq miss latency
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+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016                       # average overall miss latency
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+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32748.660203                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32839.407251                       # average overall miss latency
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+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32748.660203                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32839.407251                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs        95890                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs            1018                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs            1623                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    61.393910                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    59.081947                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       843330                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          843330                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        70371                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total        70371                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst         5416                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         5416                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        75787                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        75787                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        75787                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        75787                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        14150                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        11290                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       822799                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total       848239                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2747875                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total      2747875                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst       118620                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       118620                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst       151637                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       151637                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst       225521                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       225521                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        14150                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        11290                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst      1048320                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1073760                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        14150                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        11290                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst      1048320                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      2747875                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      3821635                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    493428269                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    628615807                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  19412995328                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  20535039404                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  69814591572                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  69814591572                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst  25734891864                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25734891864                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst   1991641357                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   1991641357                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst   2078386327                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2078386327                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst      2045000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2045000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   7579512625                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7579512625                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    493428269                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    628615807                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  26992507953                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  28114552029                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    493428269                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    628615807                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  26992507953                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  69814591572                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  97929143601                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3580047284                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3580047284                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst   3492978036                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3492978036                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst   7073025320                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7073025320                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.028795                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.065975                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.065196                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.063859                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks      1340101                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1340101                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            3                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        83863                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total        83867                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst       117019                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total       117019                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst        10752                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        10752                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        94615                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        94619                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        94615                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        94619                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        14703                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10317                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       978645                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total      1003665                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      3652327                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total      3652327                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst        63838                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total        63838                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst       132678                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       132678                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst       147002                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       147002                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst       227978                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       227978                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        14703                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10317                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst      1206623                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1231643                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        14703                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10317                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst      1206623                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      3652327                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      4883970                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  24526546457                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  25289617509                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 110063206845                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   1132471294                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   1132471294                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst   2172031189                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2172031189                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst   2030926339                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2030926339                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst      2024000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2024000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   6846769063                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6846769063                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  31373315520                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  32136386572                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  31373315520                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 142199593417                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3254469267                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3254469267                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst   2984537511                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2984537511                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst   6239006778                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6239006778                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.069377                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.067685                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.633959                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.633959                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.824845                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.824845                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.128744                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.128744                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.598714                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.598714                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.779186                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.779186                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.223755                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223755                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.028795                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.065975                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.076922                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.075136                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.028795                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.065975                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.076922                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.192693                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.192693                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.078920                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.076921                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.078920                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.267419                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23593.848957                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24209.025291                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25406.756702                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16790.097429                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16790.097429                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13706.327130                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst       409000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       409000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26183.273757                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25748.347788                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25624.933726                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.305025                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -2327,327 +1852,904 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements          4834403                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          460.748614                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          144950857                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4834915                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.980022                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8365240216000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   460.748614                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.899900                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.899900                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        306842506                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       306842506                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst     74397461                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       74397461                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst     66754653                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      66754653                       # number of WriteReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst       680221                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       680221                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst      1623333                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1623333                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst      1553141                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1553141                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst    141152114                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       141152114                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst    141152114                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      141152114                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst      3628151                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3628151                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst      2024929                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2024929                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst       114968                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       114968                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst       183901                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       183901                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst      5653080                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5653080                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst      5653080                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5653080                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst  51111445827                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  51111445827                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst  34750982270                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  34750982270                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst   1576484749                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   1576484749                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst   3893749340                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3893749340                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst      2823500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2823500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst  85862428097                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  85862428097                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst  85862428097                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  85862428097                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst     78025612                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     78025612                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst     68779582                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     68779582                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst       680221                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       680221                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst      1738301                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1738301                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst      1737042                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1737042                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst    146805194                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    146805194                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst    146805194                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    146805194                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.046499                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.046499                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.029441                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029441                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.066138                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066138                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.105870                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105870                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.038507                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038507                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.038507                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.038507                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 15188.610120                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15188.610120                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 15188.610120                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15188.610120                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                 680221                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      2756922                       # number of writebacks
-system.cpu1.dcache.writebacks::total          2756922                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst       322268                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       322268                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst       829273                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       829273                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           78                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total           78                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst           59                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           59                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst      1151541                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1151541                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst      1151541                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1151541                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst      3305883                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3305883                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst      1194736                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1194736                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst       114890                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       114890                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst       183842                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       183842                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst      4500619                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4500619                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst      4500619                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4500619                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst  39848912237                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  39848912237                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst  18776610903                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  18776610903                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst  30844406102                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  30844406102                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst   1344930230                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1344930230                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst   3516398127                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3516398127                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst      2557000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2557000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst  58625523140                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  58625523140                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst  58625523140                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  58625523140                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3752867967                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3752867967                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst   3654726713                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3654726713                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst   7407594680                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7407594680                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042369                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042369                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.017371                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017371                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.066093                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066093                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.105836                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105836                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.030657                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030657                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.030657                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.030657                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12053.939065                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11706.242754                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 19127.283901                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 13026.102218                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements               115612                       # number of replacements
-system.iocache.tags.tagsinuse               11.299913                       # Cycle average of tags in use
+system.cpu1.toL2Bus.trans_dist::ReadReq      19283354                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     15081139                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        18583                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        18583                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3739269                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      5170827                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       625737                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       495851                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       477449                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       330499                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       473092                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1314338                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1188302                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     20008489                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16359278                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       359533                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1226091                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         37953391                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    640271616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    615594373                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1295960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4483448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1261645397                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   10423087                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     30921485                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.327379                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.469257                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          20798445     67.26%     67.26% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6          10123040     32.74%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total      30921485                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   14664539498                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176010242                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy  15012316370                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy   8461463125                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy    197959664                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy    666269864                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.iobus.trans_dist::ReadReq                40348                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40348                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136740                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30012                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122926                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231170                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231170                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354176                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338696                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338696                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7496838                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36517000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042881499                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            92917000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           179159841                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115566                       # number of replacements
+system.iocache.tags.tagsinuse               11.298842                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115582                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9121131291000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.419527                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.880386                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463720                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.242524                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706245                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9120788284000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.841658                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.457184                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.240104                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466074                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706178                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1042406                       # Number of tag accesses
-system.iocache.tags.data_accesses             1042406                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106728                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106728                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1040622                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040622                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8889                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8926                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8857                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8894                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide          187                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total          187                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8889                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8929                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8857                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8897                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8889                       # number of overall misses
-system.iocache.overall_misses::total             8929                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5701000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1965059357                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1970760357                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8857                       # number of overall misses
+system.iocache.overall_misses::total             8897                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1971462847                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1977169847                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      6058000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1965059357                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1971117357                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      6058000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1965059357                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1971117357                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28907198811                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28907198811                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1971462847                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1977526847                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1971462847                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1977526847                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8889                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8926                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8857                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8894                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106915                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106915                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8889                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8929                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8857                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8897                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8889                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8929                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8857                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8897                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.001749                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.001749                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 220788.747143                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 222303.783112                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       151450                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 221066.414332                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 220754.547766                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       151450                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 221066.414332                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 220754.547766                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         54362                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 222588.105115                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 222268.949871                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 222588.105115                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 222268.949871                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        228015                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27566                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.902004                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.271603                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106728                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8889                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8926                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8857                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8894                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8889                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8929                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8857                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8897                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8889                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8929                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3777000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1502702365                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1506479365                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8857                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8897                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1510755865                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1514538865                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6627847227                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6627847227                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3978000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1502702365                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1506680365                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3978000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1502702365                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1506680365                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23356679475                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23356679475                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1510755865                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1514739865                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1510755865                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1514739865                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99450                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 168740.101355                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99450                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 168740.101355                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 170252.879060                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 170252.879060                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1797599                       # number of replacements
+system.l2c.tags.tagsinuse                64905.725288                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    8591301                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1860596                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.617499                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               6896032000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    7600.616161                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    16.639535                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     9.409863                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1890.006249                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   324.497512                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   441.216776                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst    10554.786238                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.115976                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000254                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000144                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.028839                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.258806                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004951                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006732                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.161053                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.413626                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.990383                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        43530                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          179                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        19288                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1          252                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1656                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         6242                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        35370                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          173                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          846                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         1730                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        16555                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.664215                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.002731                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.294312                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 89688959                       # Number of tag accesses
+system.l2c.tags.data_accesses                89688959                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         8987                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6604                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             578381                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      2301852                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         8168                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5333                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             630016                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      2353942                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                5893283                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         2942617                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2942617                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.inst         6235                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::cpu1.inst         6750                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::total        12985                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.inst           39044                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.inst           35229                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               74273                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.inst          7514                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.inst          7779                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             15293                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.inst            64131                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.inst            55187                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               119318                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          8987                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6604                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              642512                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher      2301852                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.itb.walker          5333                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              685203                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher      2353942                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 6012601                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         8987                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6604                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             642512                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher      2301852                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         8168                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5333                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             685203                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher      2353942                       # number of overall hits
+system.l2c.overall_hits::total                6012601                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         1978                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         1693                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            95514                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       863521                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker         2685                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker         2512                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst           131326                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       566480                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total              1665709                       # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.inst        16918                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::cpu1.inst         7174                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::total        24092                       # number of WriteInvalidateReq misses
+system.l2c.UpgradeReq_misses::cpu0.inst         36442                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.inst         33251                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             69693                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.inst         9494                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.inst         9010                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           18504                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.inst          45340                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.inst          52041                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              97381                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1978                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1693                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst            140854                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       863521                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2685                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2512                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst            183367                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       566480                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1763090                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1978                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1693                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst           140854                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       863521                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2685                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2512                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst           183367                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       566480                       # number of overall misses
+system.l2c.overall_misses::total              1763090                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    165226748                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker    144557248                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst   7974806913                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    222345248                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker    209364000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst  10644136699                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total   220050587910                       # number of ReadReq miss cycles
+system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst      3639850                       # number of WriteInvalidateReq miss cycles
+system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst      3440357                       # number of WriteInvalidateReq miss cycles
+system.l2c.WriteInvalidateReq_miss_latency::total      7080207                       # number of WriteInvalidateReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.inst    167282107                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.inst    155790979                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    323073086                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.inst     53447323                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.inst     50683879                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    104131202                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.inst   3468272337                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total   7402802919                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    165226748                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    144557248                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst  11443079250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    222345248                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    209364000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst  14578667281                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    227453390829                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    165226748                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    144557248                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst  11443079250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    222345248                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    209364000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst  14578667281                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   227453390829                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        10965                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         8297                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         673895                       # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu1.dtb.walker        10853                       # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu1.inst         761342                       # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::total            7558992                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      2942617                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2942617                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.inst        23153                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.WriteInvalidateReq_accesses::total        37077                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.inst        68480                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          143966                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.inst        17008                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu1.inst         868570                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2920422                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            7775691                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.141734                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.172493                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.220361                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst     0.730704                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst     0.515226                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.649783                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.482765                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.485558                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.484093                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.558208                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.536661                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.547504                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.inst     0.414174                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.inst     0.485330                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.449384                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.179806                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.211114                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.226744                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.179806                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.211114                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.226744                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83493.591651                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81051.251839                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 132106.261004                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst   215.146589                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst   479.559102                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   293.882077                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  4590.365704                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  4685.302066                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4635.660482                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  5629.589530                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  5625.291787                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5627.496866                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 76018.965907                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 129008.383480                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 129008.383480                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             43295                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      946                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     45.766385                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks             1219289                       # number of writebacks
+system.l2c.writebacks::total                  1219289                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst            49                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst            53                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               581                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst             49                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             53                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                581                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst            49                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst            53                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               581                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1978                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1693                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        95465                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2685                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2512                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst       131273                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total         1665128                       # number of ReadReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst        16918                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst         7174                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::total        24092                       # number of WriteInvalidateReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.inst        36442                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.inst        33251                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        69693                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst         9494                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         9010                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        18504                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.inst        45340                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.inst        52041                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         97381                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1978                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1693                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst       140805                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2685                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2512                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst       183314                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1762509                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1978                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1693                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst       140805                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2685                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2512                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst       183314                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1762509                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   6776817493                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   8997883953                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 199639162524                       # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst    385829647                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst    157261640                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total    543091287                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst    371667466                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst    338371346                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    710038812                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst     97958865                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     92039394                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    189998259                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   2897122081                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   3278712382                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   6175834463                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   9673939574                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst  12276596335                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 205814996987                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   9673939574                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst  12276596335                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 205814996987                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5245081248                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   2881233750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8126314998                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   2584862001                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst   2667893000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5252755001                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   7829943249                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   5549126750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13379069999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.141662                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.172423                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.220284                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.730704                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.515226                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.649783                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.482765                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.485558                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.484093                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.558208                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.536661                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.547504                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.414174                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.485330                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.449384                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.179744                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.211053                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.226669                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.179744                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.211053                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.226669                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 116773.870084                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 116773.870084                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq             1764688                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1764688                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38271                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38271                       # Transaction distribution
+system.membus.trans_dist::Writeback           1325983                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       130519                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       130519                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           461811                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         273493                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           92294                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            109929                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            93588                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122926                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24884                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5737506                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5885368                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336109                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       336109                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6221477                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49768                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    195441096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    195648244                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14110976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14110976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               209759220                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           661928                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3975767                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3975767    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             3975767                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109763969                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               34484                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy            20835993                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         15443357238                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        16944581187                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          187180159                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq            8566773                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           8559524                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38271                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38271                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2942617                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       143810                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp        37077                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          531990                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        288786                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         820776                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          117                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           266520                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          266520                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10703555                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10080815                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              20784370                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    361515951                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    330513413                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              692029364                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1718447                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         12650717                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.009140                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.095166                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               12535087     99.09%     99.09% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115630      0.91%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           12650717                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        18290340474                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy          7404000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy       20424320611                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy       19750107809                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 19a412b67..0607c3606 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,138 +1,135 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.727209                       # Number of seconds simulated
-sim_ticks                                51727209160500                       # Number of ticks simulated
-final_tick                               51727209160500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.688410                       # Number of seconds simulated
+sim_ticks                                51688410348500                       # Number of ticks simulated
+final_tick                               51688410348500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180889                       # Simulator instruction rate (inst/s)
-host_op_rate                                   212546                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9849373518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 656984                       # Number of bytes of host memory used
-host_seconds                                  5251.83                       # Real time elapsed on the host
-sim_insts                                   949996153                       # Number of instructions simulated
-sim_ops                                    1116252474                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 152333                       # Simulator instruction rate (inst/s)
+host_op_rate                                   179011                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8275752383                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 662164                       # Number of bytes of host memory used
+host_seconds                                  6245.77                       # Real time elapsed on the host
+sim_insts                                   951433762                       # Number of instructions simulated
+sim_ops                                    1118058358                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        424768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker       725248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker      1005696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          91312008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             93467720                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      9575168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         9575168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     57345920                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.inst      101255460                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         165427876                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6637                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker        11332                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker        15714                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst            1426763                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1460446                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          896030                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.inst           1584368                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2587062                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8212                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker          14021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          19442                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              1765261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1806935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          185109                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             185109                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1108622                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          131971                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst             1957489                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3198082                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1108622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          140183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker         14021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         19442                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3722750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5005018                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1460446                       # Number of read requests accepted
-system.physmem.writeReqs                      2587062                       # Number of write requests accepted
-system.physmem.readBursts                     1460446                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2587062                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 93277376                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    191168                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 160708736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  93467720                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              165427876                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2987                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   75973                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          39020                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               90929                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               88965                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               84770                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               81753                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               95872                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              100020                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               87194                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               85191                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               88300                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              142631                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              90249                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              90988                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              86795                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              81108                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              81197                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              81497                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              153488                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              130402                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              156905                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              130743                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              190154                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              164896                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              144797                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              175639                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              162274                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              194391                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             215398                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             156932                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             147011                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             124629                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             132966                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             130449                       # Per bank write bursts
+system.physmem.bytes_read::cpu.dtb.walker       411264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       350272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          77213320                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        415808                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             78390664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10284736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10284736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     94966144                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.inst          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          94986724                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6426                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5473                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst            1206471                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6497                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1224867                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1483846                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.inst              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1486419                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6777                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1493823                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8045                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1516600                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          198976                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             198976                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1837281                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst                 398                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1837679                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1837281                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6777                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1494221                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8045                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3354280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1224867                       # Number of read requests accepted
+system.physmem.writeReqs                      2137165                       # Number of write requests accepted
+system.physmem.readBursts                     1224867                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2137165                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 78347456                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     44032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 136289472                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  78390664                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              136634468                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      688                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7616                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          39979                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               71039                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               73325                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               71985                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               70214                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               72864                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               82821                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               75004                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               73137                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               67826                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129786                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              72316                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              77203                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              71594                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              74115                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              68849                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              72101                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              128045                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              133141                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              133329                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              132983                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              135529                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              141007                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              130525                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              133720                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              132879                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              138815                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             133616                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             135999                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             129210                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             131804                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             128438                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             130483                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51727207457500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51688408694500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1460431                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1224852                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2584489                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1416507                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     34555                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       762                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       403                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       309                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2134592                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1187733                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     30120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2405                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       606                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       760                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       444                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       307                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                       227                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       153                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      141                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      128                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       70                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       158                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      142                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      131                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       92                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       54                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -158,160 +155,155 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    72795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    99197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   141412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   149421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   158127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   155282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   155338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   158469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   154756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   163262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   150399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   141869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   140112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   143384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   124899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   123820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   121368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   119840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4523                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     3842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     3476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     3047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     2169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       17                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       780499                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      325.414218                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.439490                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     353.699104                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         309228     39.62%     39.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       174811     22.40%     62.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        65731      8.42%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36715      4.70%     75.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        26784      3.43%     78.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        18838      2.41%     80.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14160      1.81%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        15996      2.05%     84.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       118236     15.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         780499                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        115810                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.584803                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      189.442624                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         115806    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::49152-51199            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          115810                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        115810                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.682704                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.755419                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.614982                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           58231     50.28%     50.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23           24453     21.11%     71.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27           18350     15.84%     87.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            9042      7.81%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            1932      1.67%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             855      0.74%     97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             730      0.63%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             458      0.40%     98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             355      0.31%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             216      0.19%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59             209      0.18%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63             191      0.16%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             504      0.44%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              74      0.06%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              53      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              51      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              44      0.04%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               5      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              14      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             5      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             8      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          115810                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    16665773749                       # Total ticks spent queuing
-system.physmem.totMemAccLat               43993129999                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7287295000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11434.81                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    48573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    74403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                   119873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   132680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   128553                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   131972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   134309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   139176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   138776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   138399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   133829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   121319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   116942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   113077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   105310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   103984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   102748                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   101616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     4095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     3285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     2544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     2490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2024                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2001                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1597                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      961                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       728572                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      294.598947                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     169.664587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.125501                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         296144     40.65%     40.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       177091     24.31%     64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        64790      8.89%     73.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35671      4.90%     78.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        25285      3.47%     82.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        17267      2.37%     84.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        13064      1.79%     86.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        11522      1.58%     87.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        87738     12.04%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         728572                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97844                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.511242                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      125.941708                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          97842    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           97844                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97844                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.764472                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.107027                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.533220                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           71394     72.97%     72.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31           19346     19.77%     92.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            3261      3.33%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             806      0.82%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             888      0.91%     97.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             399      0.41%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             342      0.35%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             242      0.25%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             261      0.27%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             243      0.25%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            222      0.23%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            63      0.06%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            71      0.07%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            48      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           149      0.15%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            24      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            24      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             7      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            12      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             6      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            10      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97844                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    16127261998                       # Total ticks spent queuing
+system.physmem.totMemAccLat               39080618248                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6120895000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13173.94                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30184.81                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.81                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.20                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31923.94                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.11                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1137142                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   2050889                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12780013.64                       # Average gap between requests
-system.physmem.pageHitRate                      80.33                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49431156944750                       # Time in different power states
-system.physmem.memoryStateTime::REF      1727285040000                       # Time in different power states
+system.physmem.avgWrQLen                        23.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     946951                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1678178                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.35                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15374157.26                       # Average gap between requests
+system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49562808778250                       # Time in different power states
+system.physmem.memoryStateTime::REF      1725989460000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      568765880250                       # Time in different power states
+system.physmem.memoryStateTime::ACT      399611675250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2969235360                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2931337080                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1620118500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1599439875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               5574566400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               5793535800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              8080715520                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              8191044000                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3378569538240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3378569538240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1383201002250                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1386870926445                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29822988580500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29819769348750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34603003756770                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34603725170190                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.951744                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.965690                       # Core power per rank (mW)
+system.physmem.actEnergy::0                2776243680                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                2731760640                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1514815500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1490544000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               4604987400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               4943562000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              6922447920                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              6876861120                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3376035383760                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3376035383760                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1310091236460                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1307916167760                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29863840623750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29865748578750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34565785738470                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34565742858030                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.733833                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.733004                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst          740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
@@ -324,201 +316,22 @@ system.realview.nvmem.bw_inst_read::cpu.inst           14
 system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              594629                       # Transaction distribution
-system.membus.trans_dist::ReadResp             594629                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33870                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33870                       # Transaction distribution
-system.membus.trans_dist::Writeback            896030                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1688459                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1688459                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            39025                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           39026                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            901834                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           901834                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6924                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      7050430                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      7180576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       228843                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       228843                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7409419                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    251644332                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    251815240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7251264                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7251264                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               259066504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2247                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4033943                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4033943    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4033943                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113743500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5505500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         25619760742                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        15669502469                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186602993                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                40404                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40404                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136687                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           46                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231004                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231004                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354274                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334448                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334448                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492854                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981194482                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179049007                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               259878452                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         182434681                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12106293                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            193171007                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               136122005                       # Number of BTB hits
+system.cpu.branchPred.lookups               261297703                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         183348683                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12210638                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            193789546                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136743179                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.467099                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31463060                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2055318                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.562722                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31690204                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2146162                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -542,25 +355,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183357098                       # DTB read hits
-system.cpu.dtb.read_misses                     476791                       # DTB read misses
-system.cpu.dtb.write_hits                   162738381                       # DTB write hits
-system.cpu.dtb.write_misses                    102414                       # DTB write misses
+system.cpu.dtb.read_hits                    183672011                       # DTB read hits
+system.cpu.dtb.read_misses                     484545                       # DTB read misses
+system.cpu.dtb.write_hits                   163011983                       # DTB write hits
+system.cpu.dtb.write_misses                    101734                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               47228                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    80239                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       828                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  14730                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    80165                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       779                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  14148                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23395                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                183833889                       # DTB read accesses
-system.cpu.dtb.write_accesses               162840795                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23574                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                184156556                       # DTB read accesses
+system.cpu.dtb.write_accesses               163113717                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         346095479                       # DTB hits
-system.cpu.dtb.misses                          579205                       # DTB misses
-system.cpu.dtb.accesses                     346674684                       # DTB accesses
+system.cpu.dtb.hits                         346683994                       # DTB hits
+system.cpu.dtb.misses                          586279                       # DTB misses
+system.cpu.dtb.accesses                     347270273                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -582,93 +395,285 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    453041166                       # ITB inst hits
-system.cpu.itb.inst_misses                     137089                       # ITB inst misses
+system.cpu.itb.inst_hits                    455292001                       # ITB inst hits
+system.cpu.itb.inst_misses                     136900                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               47228                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    57684                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    57667                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    391598                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    366615                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                453178255                       # ITB inst accesses
-system.cpu.itb.hits                         453041166                       # DTB hits
-system.cpu.itb.misses                          137089                       # DTB misses
-system.cpu.itb.accesses                     453178255                       # DTB accesses
-system.cpu.numCycles                       2529291390                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                455428901                       # ITB inst accesses
+system.cpu.itb.hits                         455292001                       # DTB hits
+system.cpu.itb.misses                          136900                       # DTB misses
+system.cpu.itb.accesses                     455428901                       # DTB accesses
+system.cpu.numCycles                       2518825477                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   949996153                       # Number of instructions committed
-system.cpu.committedOps                    1116252474                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      97459423                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7746                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100926289028                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.662423                       # CPI: cycles per instruction
-system.cpu.ipc                               0.375598                       # IPC: instructions per cycle
+system.cpu.committedInsts                   951433762                       # Number of instructions committed
+system.cpu.committedOps                    1118058358                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      97427430                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7769                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100859175256                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.647400                       # CPI: cycles per instruction
+system.cpu.ipc                               0.377729                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16606                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1758931949                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       770359441                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements          24421267                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.933272                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           428216370                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24421779                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.534201                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20287456250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.933272                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999870                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999870                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16629                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1804872231                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       713953246                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          11184340                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.959663                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           330369377                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11184852                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.537215                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4089991250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959663                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1387996074                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1387996074                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    169370817                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       169370817                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    152148495                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      152148495                       # number of WriteReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst       336885                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       336885                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst      4109295                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4109295                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst      4353813                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4353813                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     321519312                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        321519312                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    321519312                       # number of overall hits
+system.cpu.dcache.overall_hits::total       321519312                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      8065146                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       8065146                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      4327048                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4327048                       # number of WriteReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst      1245044                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1245044                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst       246250                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       246250                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.inst     12392194                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       12392194                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst     12392194                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12392194                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128575099737                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 128575099737                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 143976164605                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 143976164605                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst  29659207447                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  29659207447                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst   3578517253                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   3578517253                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       150500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       150500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 272551264342                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 272551264342                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 272551264342                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 272551264342                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    177435963                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177435963                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    156475543                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    156475543                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      4355545                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4355545                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst      4353815                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4353815                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    333911506                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    333911506                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    333911506                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    333911506                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.045454                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.045454                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.027653                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027653                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst     0.787042                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787042                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.056537                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056537                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.037112                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037112                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.037112                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037112                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15942.067228                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15942.067228                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33273.530732                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33273.530732                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23821.814688                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23821.814688                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14532.049758                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14532.049758                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        75250                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75250                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21993.786116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21993.786116                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      8574653                       # number of writebacks
+system.cpu.dcache.writebacks::total           8574653                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       754189                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       754189                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst      1894189                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1894189                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst          150                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          150                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst      2648378                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2648378                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst      2648378                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2648378                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7310957                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7310957                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      2432859                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2432859                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst      1244894                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244894                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst       246248                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       246248                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9743816                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9743816                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9743816                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9743816                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102346476258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 102346476258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  73412590018                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  73412590018                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst   3084334247                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3084334247                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       146500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 175759066276                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 175759066276                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 175759066276                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 175759066276                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5728692998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5728692998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   5585086250                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5585086250                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  11313779248                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11313779248                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.041203                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041203                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015548                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015548                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.056537                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056537                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029181                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029181                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13999.053237                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13999.053237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30175.439686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30175.439686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21821.380618                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21821.380618                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12525.316945                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12525.316945                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        73250                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73250                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          24658250                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.931964                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           430254710                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24658762                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.448350                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       21183887000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.931964                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999867                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999867                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         477059947                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        477059947                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    428216370                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       428216370                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     428216370                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        428216370                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    428216370                       # number of overall hits
-system.cpu.icache.overall_hits::total       428216370                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24421789                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24421789                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24421789                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24421789                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24421789                       # number of overall misses
-system.cpu.icache.overall_misses::total      24421789                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 323902842267                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 323902842267                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 323902842267                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 323902842267                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 323902842267                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 323902842267                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    452638159                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    452638159                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    452638159                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    452638159                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    452638159                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    452638159                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.053954                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.053954                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.053954                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.053954                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.053954                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.053954                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13262.863022                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13262.863022                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13262.863022                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13262.863022                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13262.863022                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13262.863022                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         479572253                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        479572253                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    430254710                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       430254710                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     430254710                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        430254710                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    430254710                       # number of overall hits
+system.cpu.icache.overall_hits::total       430254710                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     24658772                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      24658772                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     24658772                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       24658772                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     24658772                       # number of overall misses
+system.cpu.icache.overall_misses::total      24658772                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 327794821206                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 327794821206                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 327794821206                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 327794821206                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 327794821206                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 327794821206                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    454913482                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    454913482                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    454913482                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    454913482                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    454913482                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    454913482                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054205                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.054205                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.054205                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.054205                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.054205                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.054205                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13293.233791                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13293.233791                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13293.233791                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13293.233791                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -677,229 +682,189 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24421789                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24421789                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24421789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24421789                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24421789                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24421789                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275014410207                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 275014410207                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275014410207                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 275014410207                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275014410207                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 275014410207                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3812415750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3812415750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3812415750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   3812415750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.053954                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.053954                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.053954                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.053954                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.053954                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.053954                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11261.026381                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11261.026381                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11261.026381                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11261.026381                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11261.026381                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11261.026381                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24658772                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24658772                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24658772                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24658772                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24658772                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24658772                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278428644242                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 278428644242                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278428644242                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 278428644242                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278428644242                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 278428644242                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3812277750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   3812277750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054205                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.054205                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.054205                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11291.261554                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       33751616                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33743319                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7503603                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1688467                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1581795                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        49741                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        49742                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2372919                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2372919                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     48947837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30709223                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       697396                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2259044                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          82613500                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1566322176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1215506888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2302360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7713224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2791844648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      568944                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     45280303                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.002552                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.050452                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           45164753     99.74%     99.74% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115550      0.26%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       45280303                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    31745616637                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       870000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36745726780                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15986739626                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     411079115                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1295977131                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements          1126830                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64583.745426                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           39448197                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1188930                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            33.179579                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     13946888021000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 34952.581213                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   365.608431                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   461.071203                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 28804.484579                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.533334                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005579                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007035                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.439522                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.985470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          475                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61625                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          455                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1805                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5403                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54172                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.007248                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.940323                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        361655243                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       361655243                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       952821                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       272081                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     31479251                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       32704153                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7503603                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7503603                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst        11325                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        11325                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst      1470476                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1470476                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       952821                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       272081                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     32949727                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        34174629                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       952821                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       272081                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     32949727                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       34174629                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        11332                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker        15714                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst       472686                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       499732                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst        38413                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        38413                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       902443                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       902443                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker        11332                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker        15714                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst      1375129                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1402175                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker        11332                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker        15714                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst      1375129                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1402175                       # number of overall misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  35148842209                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  37249702459                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst    434827365                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    434827365                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst        23499                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        23499                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::total  65253641861                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker   1212828000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 100402484070                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102503344320                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    888032250                       # number of overall miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.inst 100402484070                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total     33203885                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      7503603                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7503603                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst        49738                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        49738                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::total     35576804                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011753                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.054601                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014794                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015050                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.772307                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.772307                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.replacements          1618781                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65312.211718                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           40301488                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1682083                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.959274                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5745484000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36153.667077                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   338.579375                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   416.289773                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 28403.675493                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.551661                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005166                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006352                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.433406                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996585                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          485                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2429                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5550                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54509                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961670                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        370683226                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       370683226                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       969390                       # number of ReadReq hits
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+system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst       700619                       # number of WriteInvalidateReq hits
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+system.cpu.l2cache.UpgradeReq_miss_latency::total    437669201                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst       144500                       # number of SCUpgradeReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    506602500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst  86732673595                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    435256500                       # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       975816                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::writebacks      8574653                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      8574653                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst      1244894                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::total      1244894                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total     35862775                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018991                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.013728                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.013565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst     0.437206                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.437206                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.782299                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782299                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.380309                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.380309                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011753                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.054601                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.040062                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.039413                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011753                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.054601                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.040062                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.039413                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78365.006177                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77181.366934                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74359.812241                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74539.358014                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11319.797074                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11319.797074                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        23499                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        23499                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72307.771085                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72307.771085                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78365.006177                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77181.366934                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73013.138455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73103.103621                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78365.006177                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77181.366934                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.138455                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73103.103621                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.299305                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.299305                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018991                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.033397                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.032552                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018991                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.033397                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79527.955418                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75684.285080                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 75775.207305                       # average ReadReq miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst     8.247314                       # average WriteInvalidateReq miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     8.247314                       # average WriteInvalidateReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11175.008324                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11175.008324                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        72250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74673.056930                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74673.056930                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75101.813156                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75101.813156                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -908,96 +873,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       896030                       # number of writebacks
-system.cpu.l2cache.writebacks::total           896030                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        11332                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker        15714                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       472664                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       499710                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst        38413                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        38413                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       902443                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       902443                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        11332                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker        15714                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      1375107                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1402153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        11332                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker        15714                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      1375107                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1402153                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    747069250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker   1017596000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  29199771041                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  30964436291                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  31915763266                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  31915763266                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst    384713359                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    384713359                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  53676834083                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53676834083                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    747069250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker   1017596000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  82876605124                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  84641270374                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    747069250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker   1017596000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  82876605124                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  84641270374                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   8007389750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8007389750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   5176574500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176574500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst  13183964250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13183964250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011753                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.054601                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014793                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015050                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.772307                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.772307                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.writebacks::writebacks      1377216                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1377216                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           23                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6426                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5473                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       442221                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       454120                       # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst       544275                       # number of WriteInvalidateReq MSHR misses
+system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       544275                       # number of WriteInvalidateReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst        39165                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        39165                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       713266                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       713266                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6426                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5473                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      1155487                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1167386                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6426                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5473                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      1155487                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1167386                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    366985500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  27899659527                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  28693035027                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst    392011653                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    392011653                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  44103603876                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  44103603876                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    366985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  72003263403                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  72796638903                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    366985500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  72003263403                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  72796638903                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   8007275752                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8007275752                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   5177466000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5177466000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst  13184741752                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13184741752                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.013727                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013564                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.782299                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782299                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.380309                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.380309                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011753                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.054601                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.040062                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.039412                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011753                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.054601                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.040062                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.039412                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64757.286496                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61777.015049                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61964.812173                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.186499                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.186499                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59479.473034                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59479.473034                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64757.286496                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60269.204596                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60365.217187                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64757.286496                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60269.204596                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60365.217187                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.299305                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.299305                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.032551                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.032551                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63089.856716                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63183.817112                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23362.548706                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23362.548706                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.234087                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.234087                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61833.318672                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61833.318672                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1005,246 +974,203 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements          11147587                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.959699                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           329635231                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11148099                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.568739                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4089991250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959699                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1384853655                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1384853655                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    168902945                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       168902945                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    151918527                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      151918527                       # number of WriteReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst      1581795                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total      1581795                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst      4090248                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4090248                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst      4335751                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4335751                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     320821472                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        320821472                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    320821472                       # number of overall hits
-system.cpu.dcache.overall_hits::total       320821472                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      8037897                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       8037897                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      4311983                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4311983                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst       247236                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       247236                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.inst            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.inst     12349880                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       12349880                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst     12349880                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12349880                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 130169188997                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 130169188997                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 162013771213                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 162013771213                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst   3579343752                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   3579343752                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst        26501                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        26501                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 292182960210                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 292182960210                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 292182960210                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 292182960210                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    176940842                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    176940842                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst    156230510                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    156230510                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst      1581795                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1581795                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      4337484                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4337484                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst      4335752                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4335752                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    333171352                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    333171352                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    333171352                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    333171352                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.045427                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.045427                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.027600                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027600                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.057000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.037068                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037068                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.037068                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037068                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16194.433569                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.433569                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 37572.915110                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37572.915110                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14477.437558                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14477.437558                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23658.769171                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23658.769171                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23658.769171                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23658.769171                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                 1581795                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7503603                       # number of writebacks
-system.cpu.dcache.writebacks::total           7503603                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       754441                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       754441                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst      1888429                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1888429                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst      2642870                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2642870                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst      2642870                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2642870                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7283456                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7283456                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      2422384                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2422384                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst       247233                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       247233                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9705840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9705840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9705840                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9705840                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 104220169248                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 104220169248                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  83386178898                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83386178898                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  50958353731                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  50958353731                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst   3083220248                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3083220248                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst        24499                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        24499                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 187606348146                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 187606348146                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 187606348146                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187606348146                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5728567000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5728567000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   5584485000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5584485000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  11313052000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11313052000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.041163                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041163                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015505                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015505                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.056999                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056999                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.029132                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029132                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.029132                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029132                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14309.164392                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14309.164392                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 34423.187611                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34423.187611                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12470.909013                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.909013                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 19329.223246                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19329.223246                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 19329.223246                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19329.223246                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements               115484                       # number of replacements
-system.iocache.tags.tagsinuse               10.452726                       # Cycle average of tags in use
+system.cpu.toL2Bus.trans_dist::ReadReq       34021842                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      34013749                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33869                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33869                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8574653                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351558                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244894                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        50067                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        50069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2383072                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2383072                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49422067                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31180667                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       697225                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2277994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          83577953                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1581505984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1264852800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2305528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7806528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2856470840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      563561                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     46295151                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.002496                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.049898                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           46179597     99.75%     99.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115554      0.25%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       46295151                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    32987192886                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1194000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy   37103090732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   15825165926                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy     409755911                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy    1302956232                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.iobus.trans_dist::ReadReq                40416                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40416                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231028                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231028                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354298                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334544                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334544                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492950                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042369212                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           179072505                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115495                       # number of replacements
+system.iocache.tags.tagsinuse               10.448328                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115511                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13140359698000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.516791                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.935936                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219799                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433496                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653295                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13141221301000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.519405                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928922                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219963                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433058                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653020                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040243                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040243                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039983                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039983                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8838                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8875                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8887                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           46                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           46                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8838                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8878                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8850                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8890                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8838                       # number of overall misses
-system.iocache.overall_misses::total             8878                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8850                       # number of overall misses
+system.iocache.overall_misses::total             8890                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1936499108                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1941984108                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1921500610                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1926985610                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28836803097                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28836803097                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1936499108                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1942323108                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1921500610                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1927324610                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1936499108                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1942323108                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1921500610                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1927324610                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8838                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8875                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8887                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106710                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106710                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8838                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8878                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8850                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8890                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8838                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8878                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8850                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8890                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000431                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000431                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -1252,53 +1178,61 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 219110.557592                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 218815.110761                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 216831.957916                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 219110.557592                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 218779.354359                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 216796.919010                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 219110.557592                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 218779.354359                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         53642                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 216796.919010                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        224459                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27520                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.770856                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.156214                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106630                       # number of writebacks
+system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8838                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8875                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8850                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8887                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8838                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8878                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8850                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8890                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8838                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8878                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8850                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8890                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1476815114                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1480376114                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1461199612                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1464760612                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6530998375                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6530998375                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1476815114                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1480559114                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1461199612                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1464943612                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1476815114                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1480559114                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1461199612                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1464943612                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
@@ -1306,18 +1240,112 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167098.338312                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 166802.942423                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 167098.338312                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166767.190133                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 167098.338312                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166767.190133                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              549050                       # Transaction distribution
+system.membus.trans_dist::ReadResp             549050                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33869                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33869                       # Transaction distribution
+system.membus.trans_dist::Writeback           1483846                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       650746                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       650746                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            39985                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           39987                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            712642                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           712642                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6920                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4987889                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5118031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335345                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335345                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5453376                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    200958508                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201129408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14066624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14066624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               215196032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3058                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3350229                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3350229    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             3350229                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           113834500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5697498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         21359860992                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        12431404244                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186704495                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 173ad2168..4496ee012 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,142 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.557115                       # Number of seconds simulated
-sim_ticks                                51557114994500                       # Number of ticks simulated
-final_tick                               51557114994500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.320621                       # Number of seconds simulated
+sim_ticks                                51320620981500                       # Number of ticks simulated
+final_tick                               51320620981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81227                       # Simulator instruction rate (inst/s)
-host_op_rate                                    95475                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3758004040                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 668380                       # Number of bytes of host memory used
-host_seconds                                 13719.28                       # Real time elapsed on the host
-sim_insts                                  1114380469                       # Number of instructions simulated
-sim_ops                                    1309844804                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  75246                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88415                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4505389037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 667676                       # Number of bytes of host memory used
+host_seconds                                 11390.94                       # Real time elapsed on the host
+sim_insts                                   857117694                       # Number of instructions simulated
+sim_ops                                    1007133124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        437568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker      1002304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker      1237760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           6145632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         128560840                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            137384104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      6145632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6145632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    102180288                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data      102783780                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         211790564                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6837                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker        15661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker        19340                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             111978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2008776                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2162592                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1596567                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data           1608248                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              3311479                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8487                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker          19441                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          24008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               119200                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2493562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2664697                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          119200                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             119200                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1981885                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          132406                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1993591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4107882                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1981885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          140894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker         19441                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         24008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              119200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4487152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6772580                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2162592                       # Number of read requests accepted
-system.physmem.writeReqs                      3311479                       # Number of write requests accepted
-system.physmem.readBursts                     2162592                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    3311479                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                138204608                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    201280                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 207618304                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 137384104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              211790564                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     3145                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   67428                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48470                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              140382                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              139333                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              140658                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              133921                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              130324                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              134612                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              126217                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              133097                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              129592                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              157619                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             133394                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133867                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             132326                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             132284                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             133117                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             128704                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              201659                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              203665                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              231223                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              188549                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              224931                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              188791                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              176287                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              226882                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              203233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              233524                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             253232                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             198347                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             181957                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             175879                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             180282                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             175595                       # Per bank write bursts
+system.physmem.bytes_read::cpu.dtb.walker       227264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       206272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5756576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          43073416                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        400256                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49663784                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5756576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5756576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69780544                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          69801124                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3551                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             673035                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6254                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                791962                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1090321                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1092894                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4019                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               112169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               839300                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  967716                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          112169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             112169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1359698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1360099                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1359698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              112169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              839701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2327815                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        791962                       # Number of read requests accepted
+system.physmem.writeReqs                      1696531                       # Number of write requests accepted
+system.physmem.readBursts                      791962                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1696531                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 50649920                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     35648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 108090368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  49663784                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              108433892                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      557                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7601                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          35291                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               50546                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               51810                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               46789                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               46242                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               46096                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               52242                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               46925                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               49452                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               44750                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               73148                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              48402                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              51457                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              45806                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              48601                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              42635                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46504                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              106325                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              106592                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              106293                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              105191                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              106687                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              109171                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              103226                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              105745                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              103090                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              109771                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             107182                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             108709                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102154                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             106063                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             100653                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102060                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         190                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51557113761500                       # Total gap between requests
+system.physmem.numWrRetry                          63                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51320619748500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2141307                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  770677                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                3308906                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1296550                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    764534                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     68768                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     25837                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       916                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       532                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1693958                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    524690                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    218670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     33629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11094                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       783                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8                       222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      143                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      115                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::19                       56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -162,162 +159,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16                    88539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   132669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   172060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   179259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   199827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   201826                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   215089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   217686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   234764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   216813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   209096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   190795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   202440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   157954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   153989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   157951                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   145311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     9323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     7805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     6801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     6277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     6099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     5695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     5430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     5062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     4998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     4548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     4335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     4121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     3461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     2987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     1591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     1247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      474                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1034839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      334.179783                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.532509                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     356.014667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         392208     37.90%     37.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       234584     22.67%     60.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        87901      8.49%     69.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        49413      4.77%     73.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        38348      3.71%     77.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        26689      2.58%     80.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        21988      2.12%     82.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        25501      2.46%     84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       158207     15.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1034839                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        135592                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.925969                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      128.724301                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         135587    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-43007            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          135592                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        135592                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.924981                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.930688                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.164557                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23          101303     74.71%     74.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            7599      5.60%     80.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39           12845      9.47%     89.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            3908      2.88%     92.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            2324      1.71%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             925      0.68%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71            2932      2.16%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79            1250      0.92%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             889      0.66%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             249      0.18%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            327      0.24%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           193      0.14%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           473      0.35%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            16      0.01%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            22      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            28      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            17      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            31      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            89      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            56      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            42      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             7      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            15      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            15      0.01%     99.97% # Writes before turning the bus around for reads
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+system.physmem.wrQLenPdf::51                     1971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      990                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       519847                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.358892                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.693203                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.458813                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         210597     40.51%     40.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       125304     24.10%     64.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44434      8.55%     73.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23828      4.58%     77.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        16026      3.08%     80.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10297      1.98%     82.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8038      1.55%     84.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7736      1.49%     85.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        73587     14.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         519847                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         65806                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.026092                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       69.420005                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           65801     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           65806                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         65806                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.665015                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       22.295407                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       18.784846                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           44130     67.06%     67.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            6726     10.22%     77.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            8110     12.32%     89.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47            2086      3.17%     92.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55            1158      1.76%     94.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             536      0.81%     95.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             588      0.89%     96.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             530      0.81%     97.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             479      0.73%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             220      0.33%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            383      0.58%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111           149      0.23%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119           276      0.42%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            79      0.12%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           128      0.19%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            41      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            35      0.05%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            20      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            44      0.07%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            20      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            23      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            10      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215            10      0.02%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             6      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             5      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             5      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          135592                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    43990891280                       # Total ticks spent queuing
-system.physmem.totMemAccLat               84480522530                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10797235000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20371.37                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           65806                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15790981009                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30629824759                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3957025000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19953.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39121.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.68                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.03                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.66                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.11                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38703.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.29                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1747291                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   2621349                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9418422.55                       # Average gap between requests
-system.physmem.pageHitRate                      80.85                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49290195125250                       # Time in different power states
-system.physmem.memoryStateTime::REF      1721605340000                       # Time in different power states
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     603831                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1356638                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20623172.24                       # Average gap between requests
+system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49368372569000                       # Time in different power states
+system.physmem.memoryStateTime::REF      1713708100000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      545313634750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      238539960500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3951453240                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3871929600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2156050875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                2112660000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               8412588600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               8431020000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0             10640075760                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1             10381277520                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3367460045040                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3367460045040                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1383947967870                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1368871606665                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29720278968750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29733503847000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34496847150135                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34494632385825                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.099654                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.056696                       # Core power per rank (mW)
+system.physmem.actEnergy::0                1984348800                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                1945694520                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1082730000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1061638875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               3042748800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               3130163400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              5503010400                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              5441139360                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3352013043600                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3352013043600                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1228384903950                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1226638074825                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29714838054000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29716370360250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34306848839550                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34306600114830                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.480867                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.476020                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
@@ -334,201 +328,22 @@ system.realview.nvmem.bw_inst_read::total            8                       # I
 system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              657217                       # Transaction distribution
-system.membus.trans_dist::ReadResp             657217                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33865                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33865                       # Transaction distribution
-system.membus.trans_dist::Writeback           1596567                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1712339                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1712339                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            48473                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           48476                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1541174                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1541174                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      9221519                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      9351669                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229018                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       229018                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                9580687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    341910604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    342081160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7264064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               349345224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2022                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5500895                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5500895    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             5500895                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109641999                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5450500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         32462148974                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        21571101815                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186532342                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136716                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           17                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354224                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492654                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981079506                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179002658                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               291488483                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         200150149                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          13608043                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            209143322                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               138326751                       # Number of BTB hits
+system.cpu.branchPred.lookups               226428976                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         151471445                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12246087                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159886473                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104578062                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.139693                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                37688944                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             403819                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.407698                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31061917                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             345275                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -552,25 +367,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            206311750                       # DTB read hits
-system.cpu.checker.dtb.read_misses             258027                       # DTB read misses
-system.cpu.checker.dtb.write_hits           190103200                       # DTB write hits
-system.cpu.checker.dtb.write_misses             94684                       # DTB write misses
-system.cpu.checker.dtb.flush_tlb                   22                       # Number of times complete TLB was flushed
+system.cpu.checker.dtb.read_hits            161215407                       # DTB read hits
+system.cpu.checker.dtb.read_misses             149229                       # DTB read misses
+system.cpu.checker.dtb.write_hits           146260364                       # DTB write hits
+system.cpu.checker.dtb.write_misses             51460                       # DTB write misses
+system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid       127936                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid            2418                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            89489                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries            72721                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults          10233                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           7177                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             24751                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        206569777                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       190197884                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             19208                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        161364636                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       146311824                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 396414950                       # DTB hits
-system.cpu.checker.dtb.misses                  352711                       # DTB misses
-system.cpu.checker.dtb.accesses             396767661                       # DTB accesses
+system.cpu.checker.dtb.hits                 307475771                       # DTB hits
+system.cpu.checker.dtb.misses                  200689                       # DTB misses
+system.cpu.checker.dtb.accesses             307676460                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -592,28 +407,28 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits           1114925280                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             131008                       # ITB inst misses
+system.cpu.checker.itb.inst_hits            857529218                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             120798                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
-system.cpu.checker.itb.flush_tlb                   22                       # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid       127936                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid            2418                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            61860                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries            52233                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses       1115056288                       # ITB inst accesses
-system.cpu.checker.itb.hits                1114925280                       # DTB hits
-system.cpu.checker.itb.misses                  131008                       # DTB misses
-system.cpu.checker.itb.accesses            1115056288                       # DTB accesses
-system.cpu.checker.numCycles               1310563748                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        857650016                       # ITB inst accesses
+system.cpu.checker.itb.hits                 857529218                       # DTB hits
+system.cpu.checker.itb.misses                  120798                       # DTB misses
+system.cpu.checker.itb.accesses             857650016                       # DTB accesses
+system.cpu.checker.numCycles               1007708571                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -639,25 +454,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    220000246                       # DTB read hits
-system.cpu.dtb.read_misses                    1007031                       # DTB read misses
-system.cpu.dtb.write_hits                   193886106                       # DTB write hits
-system.cpu.dtb.write_misses                    416122                       # DTB write misses
-system.cpu.dtb.flush_tlb                           22                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    171196432                       # DTB read hits
+system.cpu.dtb.read_misses                     671544                       # DTB read misses
+system.cpu.dtb.write_hits                   149025904                       # DTB write hits
+system.cpu.dtb.write_misses                    258759                       # DTB write misses
+system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid              127936                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    2418                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    89690                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       112                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15179                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72979                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       104                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10362                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     87251                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                221007277                       # DTB read accesses
-system.cpu.dtb.write_accesses               194302228                       # DTB write accesses
+system.cpu.dtb.perms_faults                     68614                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171867976                       # DTB read accesses
+system.cpu.dtb.write_accesses               149284663                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         413886352                       # DTB hits
-system.cpu.dtb.misses                         1423153                       # DTB misses
-system.cpu.dtb.accesses                     415309505                       # DTB accesses
+system.cpu.dtb.hits                         320222336                       # DTB hits
+system.cpu.dtb.misses                          930303                       # DTB misses
+system.cpu.dtb.accesses                     321152639                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -679,639 +494,803 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    465588468                       # ITB inst hits
-system.cpu.itb.inst_misses                     176797                       # ITB inst misses
+system.cpu.itb.inst_hits                    360051885                       # ITB inst hits
+system.cpu.itb.inst_misses                     161655                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           22                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid              127936                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    2418                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    63536                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53701                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    462381                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372863                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                465765265                       # ITB inst accesses
-system.cpu.itb.hits                         465588468                       # DTB hits
-system.cpu.itb.misses                          176797                       # DTB misses
-system.cpu.itb.accesses                     465765265                       # DTB accesses
-system.cpu.numCycles                       2146849645                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                360213540                       # ITB inst accesses
+system.cpu.itb.hits                         360051885                       # DTB hits
+system.cpu.itb.misses                          161655                       # DTB misses
+system.cpu.itb.accesses                     360213540                       # DTB accesses
+system.cpu.numCycles                       1576874693                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          791511347                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1301628389                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   291488483                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          176015695                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1268750537                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29307286                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    4254748                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27926                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles      12217982                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1219824                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          381                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 465107423                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6746831                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   53918                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         2092636388                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.729302                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.142136                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          648679854                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1010290403                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   226428976                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135639979                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     852655064                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26160452                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3389644                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                26807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9240220                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1021673                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 359662567                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6136086                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47510                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1528093850                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.774691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.161324                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1367675983     65.36%     65.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                280886167     13.42%     78.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 86945610      4.15%     82.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                357128628     17.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                965958627     63.21%     63.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215893777     14.13%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70817340      4.63%     81.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                275424106     18.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           2092636388                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.135775                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.606297                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                614820490                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             852644163                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 531180111                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              83391963                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10599661                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             41490545                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               4112846                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1415541998                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              32718079                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               10599661                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                678805488                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                83662136                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      556428904                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 549849830                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             213290369                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1391734034                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               7977079                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               7435136                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 893230                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1023922                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents              127479585                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            25199                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1342075875                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2217645602                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1652184740                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1639045                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1263873564                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 78202308                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           44203192                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       39719264                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 172796539                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            223511224                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           198396121                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12647992                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11061331                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1338396177                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            44508712                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1370133902                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4153047                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        65240654                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41320787                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         373617                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    2092636388                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.654741                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.915536                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1528093850                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.143594                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.640692                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                527180052                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             504302107                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 436284853                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              51059674                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9267164                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33905862                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3872221                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1095429909                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29099398                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9267164                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                572442291                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46180186                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363186865                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 441948285                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              95069059                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1075584704                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6788495                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               4945824                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 318864                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 589123                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               42956715                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            21763                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1023437611                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1659121727                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1272319582                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1685396                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             957674620                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65762988                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27435128                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23745394                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 104747763                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            175168030                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           152601618                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9963388                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9061948                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1040022976                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27737741                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1056135120                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3300763                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53598061                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33623556                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         314928                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1528093850                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.691145                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.927830                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0          1237717942     59.15%     59.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           455529583     21.77%     80.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           292996726     14.00%     94.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96986296      4.63%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9377226      0.45%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               28615      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           873977548     57.19%     57.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           338098484     22.13%     79.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           236626258     15.49%     94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72801252      4.76%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6571176      0.43%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19132      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      2092636388                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1528093850                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                74528454     34.28%     34.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  90672      0.04%     34.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26772      0.01%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              287      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               58830485     27.06%     61.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              83911289     38.60%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58371154     35.14%     35.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100885      0.06%     35.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26756      0.02%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              767      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44544414     26.81%     62.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63075062     37.97%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             945793660     69.03%     69.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2946266      0.22%     69.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                129775      0.01%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         114397      0.01%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            224851656     16.41%     85.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           196298100     14.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                 2      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             727332382     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2546997      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                123061      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         120668      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            175096796     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150915164     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1370133902                       # Type of FU issued
-system.cpu.iq.rate                           0.638207                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   217387959                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.158662                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5052021388                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1447405501                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1347303683                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2423809                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             923681                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       885699                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1585997449                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1524411                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5766333                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1056135120                       # Type of FU issued
+system.cpu.iq.rate                           0.669765                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   166119038                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157290                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3807304115                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1120557954                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1038099529                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2479775                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             941816                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       907592                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1220693938                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1560218                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4348848                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     16996131                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        24128                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       185382                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8259714                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13855252                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14404                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       142361                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6337064                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      3623609                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       3385962                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2552747                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1859122                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10599661                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11961718                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7304667                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1383179145                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9267164                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6379535                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3965873                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1067985048                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             223511224                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            198396121                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           39177517                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 185228                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6936317                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         185382                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4274350                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5730421                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10004771                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1356817685                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             220004444                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          11924579                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             175168030                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            152601618                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23314125                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  62024                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3832996                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         142361                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3691152                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5135953                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8827105                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1044930592                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             171186057                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10287379                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        274256                       # number of nop insts executed
-system.cpu.iew.exec_refs                    413901554                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                257473473                       # Number of branches executed
-system.cpu.iew.exec_stores                  193897110                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.632004                       # Inst execution rate
-system.cpu.iew.wb_sent                     1349182874                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1348189382                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 579023420                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 949767765                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        224331                       # number of nop insts executed
+system.cpu.iew.exec_refs                    320208959                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                198322451                       # Number of branches executed
+system.cpu.iew.exec_stores                  149022902                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.662659                       # Inst execution rate
+system.cpu.iew.wb_sent                     1039793819                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1039007121                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 442154878                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 715627882                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.627985                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.609647                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.658903                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.617856                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        62443917                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        44135095                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9554061                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   2078483160                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.630193                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.269789                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51471265                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27422813                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8433025                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1516084212                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.664299                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.291990                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1396354428     67.18%     67.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    397736022     19.14%     86.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    152396085      7.33%     93.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     44287772      2.13%     95.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     35996912      1.73%     97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18656723      0.90%     98.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10905184      0.52%     98.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5449343      0.26%     99.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     16700691      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    998537580     65.86%     65.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    291350566     19.22%     85.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121957393      8.04%     93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36696853      2.42%     95.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28610485      1.89%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14255849      0.94%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8557612      0.56%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4232636      0.28%     99.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11885238      0.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   2078483160                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1114380469                       # Number of instructions committed
-system.cpu.commit.committedOps             1309844804                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1516084212                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            857117694                       # Number of instructions committed
+system.cpu.commit.committedOps             1007133124                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      396651499                       # Number of memory references committed
-system.cpu.commit.loads                     206515092                       # Number of loads committed
-system.cpu.commit.membars                     9189565                       # Number of memory barriers committed
-system.cpu.commit.branches                  249089949                       # Number of branches committed
-system.cpu.commit.fp_insts                     873640                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1196978104                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             31078874                       # Number of function calls committed.
+system.cpu.commit.refs                      307577331                       # Number of memory references committed
+system.cpu.commit.loads                     161312777                       # Number of loads committed
+system.cpu.commit.membars                     7014752                       # Number of memory barriers committed
+system.cpu.commit.branches                  191334741                       # Number of branches committed
+system.cpu.commit.fp_insts                     896026                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 925144388                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25493443                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        910428363     69.51%     69.51% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2554988      0.20%     69.70% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           104143      0.01%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       105769      0.01%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       206515092     15.77%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      190136407     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        697181314     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2164633      0.21%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98281      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       161312777     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      146264554     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1309844804                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              16700691                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total        1007133124                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11885238                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3424556806                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2758622493                       # The number of ROB writes
-system.cpu.timesIdled                         9031521                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        54213257                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 100967380384                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                  1114380469                       # Number of Instructions Simulated
-system.cpu.committedOps                    1309844804                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.926496                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.926496                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.519077                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.519077                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1611998606                       # number of integer regfile reads
-system.cpu.int_regfile_writes               948639329                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1420015                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   765124                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 315259155                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                316098925                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              6952427793                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               45059384                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq       28539920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      28531649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33865                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33865                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      9369509                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1712344                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1605675                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        61529                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        61535                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      3074731                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      3074731                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     33703094                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     37825776                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       810571                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3115869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          75455310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1077469744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1502191576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2724416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10868120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2593253856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      644632                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     42703026                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        9.002705                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.051942                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9           42587504     99.73%     99.73% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::10            115522      0.27%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       42703026                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32333793873                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       871500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   25296093441                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   19876823538                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     472614279                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1760067316                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements          16829629                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.959617                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           447510611                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          16830141                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             26.589831                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       12236526000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.959617                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
+system.cpu.rob.rob_reads                   2555181565                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2129123637                       # The number of ROB writes
+system.cpu.timesIdled                         8137810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        48780843                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101064367400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   857117694                       # Number of Instructions Simulated
+system.cpu.committedOps                    1007133124                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.839741                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.839741                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.543555                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.543555                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237020079                       # number of integer regfile reads
+system.cpu.int_regfile_writes               738429838                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1457787                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 228125574                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                228731881                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              5247037954                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27486572                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9822538                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.985265                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           286045243                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9823050                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.119799                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.985265                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1249214859                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1249214859                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    148712432                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       148712432                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    129479125                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      129479125                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       381594                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        381594                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324870                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       324870                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352883                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3352883                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3750315                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3750315                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     278191557                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        278191557                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    278573151                       # number of overall hits
+system.cpu.dcache.overall_hits::total       278573151                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9502058                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9502058                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11465174                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11465174                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1197022                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1197022                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233022                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1233022                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20967232                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20967232                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22164254                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22164254                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 140935225401                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 322991667568                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38675981880                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38675981880                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 463926892969                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 463926892969                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 463926892969                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 463926892969                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    158214490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    158214490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    140944299                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    140944299                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578616                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1578616                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3802331                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3802331                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3750320                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3750320                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    299158789                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    299158789                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    300737405                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    300737405                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060058                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060058                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081345                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081345                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758273                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.758273                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791468                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791468                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070087                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070087                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073700                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073700                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22126.282237                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20931.310973                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     21466802                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1401851                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.313184                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      7593763                       # number of writebacks
+system.cpu.dcache.writebacks::total           7593763                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4321399                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4321399                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9425025                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9425025                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7055                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7055                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219414                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219414                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13746424                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13746424                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13746424                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13746424                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5180659                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5180659                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2040149                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2040149                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190231                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1190231                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1225967                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1225967                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7220808                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7220808                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8411039                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8411039                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70208074682                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  70208074682                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53752252884                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53752252884                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18853760746                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18853760746                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2809792248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2809792248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 123960327566                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 142814088312                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729213249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729213249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587099983                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587099983                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316313232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316313232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032745                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032745                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753971                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753971                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024137                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024137                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027968                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027968                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          15082585                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.954216                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           343840613                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15083097                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.796420                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       14175734000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.954216                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          291                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           92                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         481916487                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        481916487                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    447510611                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       447510611                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     447510611                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        447510611                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    447510611                       # number of overall hits
-system.cpu.icache.overall_hits::total       447510611                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     17575514                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      17575514                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     17575514                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       17575514                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     17575514                       # number of overall misses
-system.cpu.icache.overall_misses::total      17575514                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 231527181766                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 231527181766                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 231527181766                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 231527181766                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 231527181766                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465086125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465086125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465086125                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465086125                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465086125                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465086125                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.037790                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.037790                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.037790                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.037790                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.037790                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.037790                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13173.280836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13173.280836                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        11084                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         374724467                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        374724467                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    343840613                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       343840613                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     343840613                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        343840613                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    343840613                       # number of overall hits
+system.cpu.icache.overall_hits::total       343840613                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15800655                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15800655                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15800655                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15800655                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15800655                       # number of overall misses
+system.cpu.icache.overall_misses::total      15800655                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208208668907                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208208668907                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208208668907                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208208668907                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208208668907                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    359641268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    359641268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    359641268                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    359641268                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    359641268                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    359641268                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043934                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043934                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043934                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043934                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043934                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043934                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13177.217584                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13177.217584                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        10839                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               920                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               972                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.047826                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    11.151235                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       745151                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       745151                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       745151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       745151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       745151                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       745151                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16830363                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     16830363                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     16830363                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     16830363                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     16830363                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     16830363                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 191394786019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 191394786019                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717456                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       717456                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       717456                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       717456                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       717456                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       717456                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15083199                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     15083199                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     15083199                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     15083199                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     15083199                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     15083199                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 171815580989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 171815580989                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.036188                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.036188                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.041940                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.041940                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1866229                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64521.528187                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           35312731                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1928499                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.310993                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     13813873928000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   307.320059                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.834309                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7078.453286                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.523738                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004689                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006864                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.108009                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.341220                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          496                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61774                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2102                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5030                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.007568                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.942596                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        341864435                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       341864435                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1342854                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       321211                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     16739434                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      8950656                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       27354155                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      9369509                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      9369509                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        13684                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        13684                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.replacements          1167362                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65297.852107                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           29065274                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1230222                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.626040                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       2430272000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   320.853018                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   490.286692                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7518.567341                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.569512                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004896                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007481                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.299753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996366                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          285                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62575                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          285                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          565                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2655                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5044                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54243                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004349                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954819                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        273181992                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       273181992                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       797530                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297299                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst     14998467                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      6339712                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total       22433008                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      7593763                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      7593763                       # number of Writeback hits
+system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       728839                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.WriteInvalidateReq_hits::total       728839                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9472                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9472                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1532929                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1532929                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker      1342854                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       321211                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     16739434                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     10483585                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        28887084                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker      1342854                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       321211                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     16739434                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     10483585                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       28887084                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        15661                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker        19341                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        90708                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       467610                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       593320                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        47842                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        47842                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data      1541802                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total      1541802                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker        15661                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker        19341                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        90708                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2009412                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2135122                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker        15661                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker        19341                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        90708                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2009412                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2135122                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker   1242745748                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker   1521537709                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6968907733                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  38087084418                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  47820275608                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    470429308                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    470429308                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        46998                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        46998                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128470228063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 128470228063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker   1242745748                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker   1521537709                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   6968907733                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 166557312481                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 176290503671                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker   1242745748                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker   1521537709                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   6968907733                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 166557312481                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 176290503671                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1358515                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       340552                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst     16830142                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      9418266                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     27947475                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      9369509                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      9369509                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        61526                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        61526                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      3074731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      3074731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1358515                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       340552                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     16830142                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     12492997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     31022206                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1358515                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       340552                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     16830142                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     12492997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     31022206                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.056793                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005390                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049649                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021230                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.777590                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.777590                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.501443                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.501443                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for demand accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005390                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.056793                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005390                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.160843                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068826                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78669.029988                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76827.928441                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81450.534458                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80597.781312                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  9832.977467                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  9832.977467                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        15666                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        15666                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83324.725265                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83324.725265                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78669.029988                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.928441                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82888.582571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82566.946372                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78669.029988                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.928441                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82888.582571                       # average overall miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1320,113 +1299,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18259324004                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24194010014                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345545498                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345545498                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29577738885                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29577738885                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    220243499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5475082762                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47837062889                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  53771748899                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    220243499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5475082762                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47837062889                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  53771748899                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289773250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393755500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176184000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176184000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289733251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393715501                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176071500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176071500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465957250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569939500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049647                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021229                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.777590                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.777590                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.501443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.501443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068825                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068825                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69004.344071                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68136.808705                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.580745                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.580745                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71012.621808                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465804751                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569787001                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.039032                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208413                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208413                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030898                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030898                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1436,336 +1416,384 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements          13756884                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.985330                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           363427258                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          13757396                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             26.416864                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.985330                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          382                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1609448196                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1609448196                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    188132338                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       188132338                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    164232223                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      164232223                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       465761                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        465761                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data      1605675                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total      1605675                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4847947                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4847947                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      5335203                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      5335203                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     352364561                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        352364561                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    352830322                       # number of overall hits
-system.cpu.dcache.overall_hits::total       352830322                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12712279                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12712279                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     18968725                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     18968725                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      2072118                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      2072118                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       550419                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       550419                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     31681004                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       31681004                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     33753122                       # number of overall misses
-system.cpu.dcache.overall_misses::total      33753122                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 203403538452                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1021678237791                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8626183252                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   8626183252                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       117003                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       117003                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1225081776243                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1225081776243                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    200844617                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    200844617                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    183200948                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    183200948                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2537879                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2537879                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5398366                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      5398366                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      5335209                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      5335209                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    384045565                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    384045565                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    386583444                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    386583444                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063294                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.063294                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.103541                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.103541                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.816476                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.816476                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.101960                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.101960                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.082493                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.082493                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.087311                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087311                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38669.285110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36295.361841                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     38319499                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           2284719                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    16.772084                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                 1605675                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      9369509                       # number of writebacks
-system.cpu.dcache.writebacks::total           9369509                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5628309                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5628309                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15829986                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total     15829986                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265840                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       265840                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     21458295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     21458295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     21458295                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     21458295                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7083970                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7083970                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3120649                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      3120649                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2065320                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      2065320                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       284579                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       284579                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     10204619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     10204619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     12269939                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     12269939                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  31611668497                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  31611668497                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3751055249                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3751055249                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       104997                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       104997                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 250741484767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 282353153264                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729434750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729434750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587276983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587276983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316711733                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316711733                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035271                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035271                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.017034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.017034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.813798                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.813798                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.052716                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.052716                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026571                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026571                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031739                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031739                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements               115458                       # number of replacements
-system.iocache.tags.tagsinuse               10.450727                       # Cycle average of tags in use
+system.cpu.toL2Bus.trans_dist::ReadReq       23341232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23333163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      7593763                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332631                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1225967                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43982                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1999866                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1999866                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30208899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27463876                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       731462                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1967033                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          60371270                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965659760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1114918084                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2404176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6408648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2089390668                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      611685                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     34508223                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        9.003348                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.057762                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9           34392703     99.67%     99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10            115520      0.33%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       34508223                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    26206492236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1177500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy   22671590732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   13674088224                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy     431886005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy    1166711358                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.iobus.trans_dist::ReadReq                40382                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40382                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492678                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042360658                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           179004169                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115462                       # number of replacements
+system.iocache.tags.tagsinuse               10.424613                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13090278324000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.528058                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.922669                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.220504                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.432667                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653170                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13092189065000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544618                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879995                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039786                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039786                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039677                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           17                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           17                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5547000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1929395843                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1934942843                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
+system.iocache.overall_misses::total             8856                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1927411613                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1932938613                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5886000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1929395843                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1935281843                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5886000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1929395843                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1935281843                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1927411613                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1933277613                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1927411613                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1933277613                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106681                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106681                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000159                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000159                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 218637.609379                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 218337.130125                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 218601.812154                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 218601.812154                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         53350                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        226675                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27646                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.717668                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.199197                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3623000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1470987863                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1474610863                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1468863623                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1472466623                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3806000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1470987863                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1474793863                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3806000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1470987863                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1474793863                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1468863623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1472649623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1468863623                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1472649623                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              412825                       # Transaction distribution
+system.membus.trans_dist::ReadResp             412825                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
+system.membus.trans_dist::Writeback           1090321                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       603637                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       603637                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35296                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35298                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            416163                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           416163                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3625442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3755550                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4090619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    144046540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144217012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14051136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14051136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               158268148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3264                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2503253                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2503253    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2503253                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109702500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5437999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         16337638979                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         7836649146                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186565831                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    17164                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16179                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 6eaff03eb..e64b12ad0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,181 +1,178 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.379675                       # Number of seconds simulated
-sim_ticks                                47379674621500                       # Number of ticks simulated
-final_tick                               47379674621500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.422278                       # Number of seconds simulated
+sim_ticks                                47422277747000                       # Number of ticks simulated
+final_tick                               47422277747000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105231                       # Simulator instruction rate (inst/s)
-host_op_rate                                   123773                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5339286706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 910192                       # Number of bytes of host memory used
-host_seconds                                  8873.78                       # Real time elapsed on the host
-sim_insts                                   933798389                       # Number of instructions simulated
-sim_ops                                    1098335322                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  91986                       # Simulator instruction rate (inst/s)
+host_op_rate                                   108182                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4717167353                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 870208                       # Number of bytes of host memory used
+host_seconds                                 10053.13                       # Real time elapsed on the host
+sim_insts                                   924745220                       # Number of instructions simulated
+sim_ops                                    1087564829                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       353088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       523648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1152800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         18354072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     38298624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       338240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       462784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           532064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12967328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     29162240                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        472128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            102617016                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1152800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       532064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1684864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     56488832                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      66623564                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      34275268                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6830592                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         164218256                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         5517                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         8182                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             33965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            286804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       598416                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         5285                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         7231                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              8357                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            202629                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       455660                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7377                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1619423                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          882638                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          1043270                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           535552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106728                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2568188                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          7452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         11052                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               24331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              387383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       808334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          7139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          9768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               11230                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              273690                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       615501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9965                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2165845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          24331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          11230                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              35561                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1192259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            1406163                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             723417                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          144167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3466006                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1192259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         7452                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        11052                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              24331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1793546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       808334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         7139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         9768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              11230                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             997107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       615501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          154132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5631851                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1619423                       # Number of read requests accepted
-system.physmem.writeReqs                      2568188                       # Number of write requests accepted
-system.physmem.readBursts                     1619423                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2568188                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                103371328                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    271744                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 158872640                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 102617016                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              164218256                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     4246                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   85771                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         103144                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              111705                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              107185                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               95216                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               93593                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               97040                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              109538                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              103640                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              104459                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               87345                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              119689                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              87550                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             102455                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              98167                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              96293                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              97699                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             103603                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              151797                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              157102                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              173467                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              129226                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              217724                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              151423                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              153455                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              181552                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              127836                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              166575                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             140595                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             139064                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             135611                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             129688                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             173219                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             154051                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker       123008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        83392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1145824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         12461528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     54523392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       250240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       244864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           679904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         13804768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     35481280                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        451200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            119249400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1145824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       679904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1825728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     92428416                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          92449232                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1922                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1303                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             33856                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            194733                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       851928                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3826                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            215714                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       554395                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           7050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1879304                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1444194                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1446797                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               24162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              262778                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      1149742                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          5277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          5163                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               14337                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              291103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       748199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2514628                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          24162                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          14337                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              38499                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1949051                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1949489                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1949051                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2594                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              24162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             263217                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      1149742                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         5277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         5163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              14337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             291103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       748199                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4464118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1879304                       # Number of read requests accepted
+system.physmem.writeReqs                      1600997                       # Number of write requests accepted
+system.physmem.readBursts                     1879304                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1600997                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                120227392                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 101998144                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 119249400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              102318032                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      751                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7249                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          97584                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              111371                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              133364                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              107237                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              129396                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              116369                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              129089                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              116664                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              120571                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              118226                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              133705                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              98234                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             110272                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             110364                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124983                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             111960                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             106748                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               99185                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              109011                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               97054                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              108172                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               98286                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              106076                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              100140                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              103851                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               98795                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               98239                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              89198                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              97505                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              95822                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102116                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              95043                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              95228                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         280                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47379673169000                       # Total gap between requests
+system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47422276363500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1598053                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1857934                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2565585                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    575288                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    378276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    198870                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    124070                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     84552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     66107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     57559                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     49842                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     42131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     14414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     7965                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     5242                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     3374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     2598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1882                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      199                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1598394                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    506038                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    360780                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    256406                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    156907                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    129304                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     95738                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     81613                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     74114                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     66527                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     41507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    30519                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    26998                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    23594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    21466                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     2821                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     2006                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      877                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      672                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      365                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        1                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -191,159 +188,184 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    50077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    80336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    91349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   103691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   113552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   135687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   144994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   161556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   168861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   188844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   173768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   166459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   153274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   157126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   123678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   118188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   114281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   106686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    15195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                    11268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     9055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     7628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     7057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     6378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     5840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     5400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     5192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     4660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     4389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     4093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     3546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     3036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1911                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     1704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     1382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     1113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      674                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       968355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.813741                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     146.322670                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.242545                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         500729     51.71%     51.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       182951     18.89%     70.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        62910      6.50%     77.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        30320      3.13%     80.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        27676      2.86%     83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        15651      1.62%     84.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        12433      1.28%     85.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        15606      1.61%     87.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       120079     12.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         968355                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         90300                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.886467                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      201.343157                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          90297    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-59391            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           90300                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         90300                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.490421                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       23.640759                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       19.748039                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           56859     62.97%     62.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            8057      8.92%     71.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39           12273     13.59%     85.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            3990      4.42%     89.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            1898      2.10%     92.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             944      1.05%     93.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71            2681      2.97%     96.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79            1258      1.39%     97.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             729      0.81%     98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             233      0.26%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            328      0.36%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           174      0.19%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           473      0.52%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            16      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            44      0.05%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            33      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            16      0.02%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            34      0.04%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            77      0.09%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            57      0.06%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            40      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             6      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            21      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            22      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             4      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             7      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           90300                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    65880977516                       # Total ticks spent queuing
-system.physmem.totMemAccLat               96165546266                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8075885000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       40788.70                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    23051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    29130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    37353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    44982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    51054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    59346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    67111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    76742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    83422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    92810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    99100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   107174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   114191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   124207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   117512                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   121939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   125600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   118087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    27656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                    21524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                    15466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                    10008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     6220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     4458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     3377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     2458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      599                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       975956                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      227.699905                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.562466                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     280.517231                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         518192     53.10%     53.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       197775     20.26%     73.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        73464      7.53%     80.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        39205      4.02%     84.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        32875      3.37%     88.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        20645      2.12%     90.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14690      1.51%     91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        16974      1.74%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        62136      6.37%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         975956                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         85700                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.919883                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       65.914571                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           85693     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           85700                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         85700                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.596511                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.559355                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.221946                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           76419     89.17%     89.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            4825      5.63%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             861      1.00%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             776      0.91%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             493      0.58%     97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             137      0.16%     97.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             117      0.14%     97.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             137      0.16%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             585      0.68%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              72      0.08%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              76      0.09%     98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              72      0.08%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             110      0.13%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              48      0.06%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              42      0.05%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              81      0.09%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             124      0.14%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              28      0.03%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              35      0.04%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              50      0.06%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             194      0.23%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            14      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            23      0.03%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            14      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            54      0.06%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            16      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            21      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            26      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131           106      0.12%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            28      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             8      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             9      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            15      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            15      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            11      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             4      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             6      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           85700                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   131185455773                       # Total ticks spent queuing
+system.physmem.totMemAccLat              166408324523                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9392765000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       69833.25                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  59538.70                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.18                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.35                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.47                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  88583.25                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         3.63                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.06                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1266207                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1862998                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.05                       # Row buffer hit rate for writes
-system.physmem.avgGap                     11314248.90                       # Average gap between requests
-system.physmem.pageHitRate                      76.37                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     45458713155000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1582111440000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.75                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1529879                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    966437                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  60.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13625912.35                       # Average gap between requests
+system.physmem.pageHitRate                      71.89                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     45568926392500                       # Time in different power states
+system.physmem.memoryStateTime::REF      1583533900000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      338849669500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      269814192000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3771472320                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3549283920                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2057847000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1936613250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               6414501600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               6183847800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              8526034080                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              7559820720                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3094609976640                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3094609976640                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1215510046335                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1201972779180                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          27361567580250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          27373442376000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            31692457458225                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            31689254697510                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.904083                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.836485                       # Core power per rank (mW)
+system.physmem.actEnergy::0                3837713040                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                3540506760                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                2093990250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1931824125                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               7519675800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               7132967400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              5325102000                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              5002210080                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3097392308400                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3097392308400                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1175879799405                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1172220553305                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          27421890099000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          27425099964000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            31713938687895                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            31712320334070                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.756196                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.722070                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
@@ -376,15 +398,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              146587108                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         96932064                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7164901                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           103453764                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               67642054                       # Number of BTB hits
+system.cpu0.branchPred.lookups              136692903                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         91051024                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6675955                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            96641264                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               62499971                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.383850                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20270932                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            203679                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            64.672137                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               18343531                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            188881                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -409,25 +431,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   106134781                       # DTB read hits
-system.cpu0.dtb.read_misses                    438400                       # DTB read misses
-system.cpu0.dtb.write_hits                   87107060                       # DTB write hits
-system.cpu0.dtb.write_misses                   166320                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    98285730                       # DTB read hits
+system.cpu0.dtb.read_misses                    371363                       # DTB read misses
+system.cpu0.dtb.write_hits                   82429878                       # DTB write hits
+system.cpu0.dtb.write_misses                   160428                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              46078                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   41289                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      449                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7213                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34259                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      107                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  6211                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    39737                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               106573181                       # DTB read accesses
-system.cpu0.dtb.write_accesses               87273380                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    37781                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                98657093                       # DTB read accesses
+system.cpu0.dtb.write_accesses               82590306                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        193241841                       # DTB hits
-system.cpu0.dtb.misses                         604720                       # DTB misses
-system.cpu0.dtb.accesses                    193846561                       # DTB accesses
+system.cpu0.dtb.hits                        180715608                       # DTB hits
+system.cpu0.dtb.misses                         531791                       # DTB misses
+system.cpu0.dtb.accesses                    181247399                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -449,519 +471,533 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   230537480                       # ITB inst hits
-system.cpu0.itb.inst_misses                     86000                       # ITB inst misses
+system.cpu0.itb.inst_hits                   214588445                       # ITB inst hits
+system.cpu0.itb.inst_misses                     81035                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              46078                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   29668                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24176                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   226388                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   217359                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               230623480                       # ITB inst accesses
-system.cpu0.itb.hits                        230537480                       # DTB hits
-system.cpu0.itb.misses                          86000                       # DTB misses
-system.cpu0.itb.accesses                    230623480                       # DTB accesses
-system.cpu0.numCycles                       786965482                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               214669480                       # ITB inst accesses
+system.cpu0.itb.hits                        214588445                       # DTB hits
+system.cpu0.itb.misses                          81035                       # DTB misses
+system.cpu0.itb.accesses                    214669480                       # DTB accesses
+system.cpu0.numCycles                       723605959                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          90387711                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     647691070                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  146587108                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          87912986                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    665690431                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15471710                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1846295                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              143165                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6476529                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       786234                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       320116                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                230311190                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1742140                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  28723                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         773386336                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.980975                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.219702                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          84128505                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     603958712                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  136692903                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          80843502                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    610845531                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               14389096                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1590613                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              145998                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6064926                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       691327                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       308415                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                214371554                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1629958                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  26989                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         710969863                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.995603                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.223531                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               409957196     53.01%     53.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               140998975     18.23%     71.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                49617031      6.42%     77.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               172813134     22.34%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               371943625     52.31%     52.31% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               132005479     18.57%     70.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                45223870      6.36%     77.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               161796889     22.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           773386336                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.186269                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.823023                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               108593313                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            378356513                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                240969730                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             39977542                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5489238                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            21224089                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2292433                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             668689408                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             25030555                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5489238                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               146312922                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               57383456                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     250430469                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                242520551                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             71249700                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             650266707                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6336504                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              9477139                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                381865                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                840506                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              33815177                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           14484                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          619540415                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1001273329                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       768127423                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           806411                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            558016180                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                61524234                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16309942                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14158531                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 81487680                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           106551444                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           90697387                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9851628                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8566406                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 626998472                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16435650                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                631073777                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2910747                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       54340762                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     37568320                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        303534                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    773386336                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.815988                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.066561                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           710969863                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.188905                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.834651                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               100859820                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            341670501                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                226894689                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             36450722                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5094131                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19684552                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2143149                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             625299942                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             23465263                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5094131                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               135677386                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               49836875                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     228336608                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                227963533                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             64061330                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             608231586                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              5949574                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              8548374                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                231810                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                263882                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              30185355                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           12581                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          579905224                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            937754781                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       718843517                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups          1013139                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            522903039                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                57002179                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15055979                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13152707                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 73956769                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            99026206                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           85770687                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          8763922                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         7686093                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 586686508                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15156086                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                590156830                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2681738                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       50409396                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     34542071                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        266225                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    710969863                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.830073                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.072195                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          429333552     55.51%     55.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          143479671     18.55%     74.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          122471651     15.84%     89.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           69760577      9.02%     98.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8335355      1.08%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5527      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                  3      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          390297771     54.90%     54.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          132320625     18.61%     73.51% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          115120103     16.19%     89.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           65333726      9.19%     98.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7893369      1.11%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4269      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      773386336                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      710969863                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               65856729     45.73%     45.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 73447      0.05%     45.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  22232      0.02%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              47      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              37876967     26.30%     72.09% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             40192311     27.91%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               61459839     45.63%     45.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 50531      0.04%     45.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  24866      0.02%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              22      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              34471783     25.59%     71.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             38693635     28.73%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            431505224     68.38%     68.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1606072      0.25%     68.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                80666      0.01%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 12      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                1      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         46680      0.01%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           109370672     17.33%     85.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           88464450     14.02%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            403696370     68.40%     68.40% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1373917      0.23%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                72713      0.01%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  2      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         82685      0.01%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           101222055     17.15%     85.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           83709039     14.18%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             631073777                       # Type of FU issued
-system.cpu0.iq.rate                          0.801908                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  144021733                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228217                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2181305203                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        697468177                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    613392938                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1161167                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            463347                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       426941                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             774373560                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 721950                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2923759                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             590156830                       # Type of FU issued
+system.cpu0.iq.rate                          0.815578                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  134700676                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228246                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2027250728                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        651818194                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    574107974                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1415207                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            570288                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       525567                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             723981962                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 875543                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2649036                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13150556                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        17424                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       157648                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6172607                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     12005066                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        15997                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       137574                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5832630                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2931375                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4759724                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2633268                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      3783846                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5489238                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8266633                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              4717216                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          643560247                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5094131                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                6289107                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              4809356                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          601961701                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            106551444                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            90697387                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13867290                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 61805                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              4582618                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        157648                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2155844                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3101202                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5257046                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            622852330                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            106129153                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7624905                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             99026206                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            85770687                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          12881584                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 63147                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              4682481                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        137574                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1984191                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2898838                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4883029                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            582493668                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             98279194                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7144205                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       126125                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   193235409                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               117777762                       # Number of branches executed
-system.cpu0.iew.exec_stores                  87106256                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.791461                       # Inst execution rate
-system.cpu0.iew.wb_sent                     614619625                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    613819879                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                298670143                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                489758313                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       119107                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   180711366                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               110157991                       # Number of branches executed
+system.cpu0.iew.exec_stores                  82432172                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.804987                       # Inst execution rate
+system.cpu0.iew.wb_sent                     575359382                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    574633541                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                278757047                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                457962623                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.779983                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609832                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.794125                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.608690                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       50622338                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       16132116                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4918284                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    763797135                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.766621                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.569865                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       46943290                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14889861                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4575538                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    702085405                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.780670                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.579297                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    508551807     66.58%     66.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    131505056     17.22%     83.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     56862924      7.44%     91.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     18814885      2.46%     93.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13980697      1.83%     95.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9342143      1.22%     96.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6309382      0.83%     97.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      4063980      0.53%     98.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14366261      1.88%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    463334360     65.99%     65.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    122538358     17.45%     83.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     53278812      7.59%     91.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     18006181      2.56%     93.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     13261797      1.89%     95.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8597155      1.22%     96.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5895517      0.84%     97.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3809437      0.54%     98.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     13363788      1.90%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    763797135                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           498729441                       # Number of instructions committed
-system.cpu0.commit.committedOps             585543302                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    702085405                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           466411686                       # Number of instructions committed
+system.cpu0.commit.committedOps             548096953                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     177925668                       # Number of memory references committed
-system.cpu0.commit.loads                     93400888                       # Number of loads committed
-system.cpu0.commit.membars                    4075726                       # Number of memory barriers committed
-system.cpu0.commit.branches                 111746625                       # Number of branches committed
-system.cpu0.commit.fp_insts                    417930                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                537600399                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            15117239                       # Number of function calls committed.
+system.cpu0.commit.refs                     166959196                       # Number of memory references committed
+system.cpu0.commit.loads                     87021139                       # Number of loads committed
+system.cpu0.commit.membars                    3711025                       # Number of memory barriers committed
+system.cpu0.commit.branches                 104496556                       # Number of branches committed
+system.cpu0.commit.fp_insts                    513447                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                502627891                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13679873                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       406177320     69.37%     69.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1336444      0.23%     69.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           63141      0.01%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        40729      0.01%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       93400888     15.95%     85.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      84524780     14.44%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       379865208     69.31%     69.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1141082      0.21%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           57492      0.01%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        73933      0.01%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       87021139     15.88%     85.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      79938057     14.58%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        585543302                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14366261                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total        548096953                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             13363788                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                  1380974813                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1281884282                       # The number of ROB writes
-system.cpu0.timesIdled                         846185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       13579146                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93972383800                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  498729441                       # Number of Instructions Simulated
-system.cpu0.committedOps                    585543302                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.577941                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.577941                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.633737                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.633737                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               735405419                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              437369435                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   697220                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  340900                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                134840784                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               135500502                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             3071586051                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16203449                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6421778                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          503.783649                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          165065902                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6422290                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.702032                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                  1279505618                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1198929363                       # The number of ROB writes
+system.cpu0.timesIdled                         780048                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       12636096                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 94120949562                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  466411686                       # Number of Instructions Simulated
+system.cpu0.committedOps                    548096953                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.551432                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.551432                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.644566                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.644566                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               688144011                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              408577767                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   842658                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  455584                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                127446024                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               128164594                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             2855519856                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15107964                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          5838402                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          504.465464                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          155155227                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5838912                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            26.572626                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1750084500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.783649                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983952                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.983952                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        369226254                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       369226254                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     86280065                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       86280065                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     73574281                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      73574281                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       230862                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       230862                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data      1040668                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1040668                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1948592                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1948592                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1987329                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1987329                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    159854346                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       159854346                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    160085208                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      160085208                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7331765                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7331765                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7708797                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7708797                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       740087                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       740087                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       294779                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       294779                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       214098                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       214098                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     15040562                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      15040562                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     15780649                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     15780649                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 115068880578                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 135208359707                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4223400082                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4223400082                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4534810216                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4534810216                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4219500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4219500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 250277240285                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 250277240285                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     93611830                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     93611830                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     81283078                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     81283078                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       970949                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       970949                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1040668                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1040668                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2243371                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2243371                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2201427                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2201427                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    174894908                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    174894908                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    175865857                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    175865857                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.078321                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.078321                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.094839                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.094839                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.762231                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.762231                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.131400                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.131400                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097254                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097254                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.085998                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.085998                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.089731                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.089731                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   504.465464                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.985284                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.985284                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        346167633                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       346167633                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     80535549                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       80535549                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69641264                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69641264                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       207056                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       207056                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       203093                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       203093                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1877400                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1877400                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1900232                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1900232                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    150176813                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       150176813                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    150383869                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      150383869                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6642832                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6642832                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7191098                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7191098                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       692118                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       692118                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       798159                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       798159                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       243998                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       243998                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       184133                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       184133                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13833930                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13833930                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     14526048                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     14526048                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  99514286008                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  99514286008                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 115098035706                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  53560236062                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  53560236062                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3359260407                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3359260407                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3823760481                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3823760481                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2172500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2172500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 214612321714                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 214612321714                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     87178381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     87178381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     76832362                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     76832362                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       899174                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       899174                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1001252                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1001252                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2121398                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2121398                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2084365                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2084365                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    164010743                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    164010743                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    164909917                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    164909917                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076198                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.076198                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.093595                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.093595                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.769726                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.769726                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.797161                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.797161                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.115018                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.115018                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088340                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088340                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084348                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.084348                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088085                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.088085                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     17082084                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     19003690                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           950552                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         748671                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.970699                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    25.383232                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1040668                       # number of fast writes performed
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     16118603                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     16176348                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           692801                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         696412                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.265848                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    23.228129                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3548346                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3548346                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3808172                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3808172                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6155071                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6155071                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       150940                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       150940                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9963243                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9963243                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9963243                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9963243                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3523593                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3523593                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1532184                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1532184                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       733570                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       733570                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       143839                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       143839                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       214091                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       214091                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5055777                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5055777                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5789347                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5789347                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48006705459                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  48006705459                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27570008615                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27570008615                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18661725527                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18661725527                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  57519686561                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  57519686561                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1764532424                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1764532424                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4095364784                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4095364784                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4027500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4027500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  75576714074                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  75576714074                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94238439601                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  94238439601                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5807383412                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5807383412                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5600359921                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5600359921                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11407743333                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11407743333                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037640                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037640                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018850                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018850                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.755519                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.755519                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064117                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064117                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097251                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097251                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028908                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028908                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032919                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032919                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3975125                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3975125                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3497983                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3497983                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5763188                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      5763188                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         4492                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         4492                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       123982                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       123982                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9261171                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9261171                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9261171                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9261171                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3144849                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3144849                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1427910                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1427910                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       685927                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       685927                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       793667                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       793667                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       120016                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       120016                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       184129                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       184129                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4572759                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4572759                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5258686                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5258686                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40981205496                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40981205496                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  22755476630                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22755476630                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17996613568                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17996613568                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  51855736982                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  51855736982                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1434297417                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1434297417                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3446370519                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3446370519                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2070500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2070500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  63736682126                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  63736682126                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  81733295694                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  81733295694                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5581760391                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5581760391                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5277895398                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5277895398                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10859655789                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10859655789                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036074                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036074                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018585                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018585                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.762841                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.762841                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.792675                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.792675                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056574                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056574                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088338                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088338                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027881                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027881                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031888                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031888                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -969,447 +1005,463 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6503720                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.971418                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          223511778                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6504232                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.364054                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8400074750                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.971418                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999944                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          6042830                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.967320                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          208050611                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6043342                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.426417                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11201042000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.967320                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999936                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999936                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          266                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          184                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        467078613                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       467078613                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    223511778                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      223511778                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    223511778                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       223511778                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    223511778                       # number of overall hits
-system.cpu0.icache.overall_hits::total      223511778                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6775226                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6775226                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6775226                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6775226                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6775226                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6775226                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  58809305620                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  58809305620                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  58809305620                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  58809305620                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  58809305620                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  58809305620                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    230287004                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    230287004                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    230287004                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    230287004                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    230287004                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    230287004                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029421                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029421                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029421                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029421                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029421                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029421                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8680.050764                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8680.050764                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8680.050764                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8680.050764                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8680.050764                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8680.050764                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      4711788                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          167                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           607280                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        434737408                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       434737408                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    208050611                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      208050611                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    208050611                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       208050611                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    208050611                       # number of overall hits
+system.cpu0.icache.overall_hits::total      208050611                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6296413                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6296413                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6296413                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6296413                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6296413                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6296413                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  55127710497                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  55127710497                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  55127710497                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  55127710497                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  55127710497                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  55127710497                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    214347024                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    214347024                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    214347024                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    214347024                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    214347024                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    214347024                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029375                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029375                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029375                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029375                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029375                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029375                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8755.415265                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8755.415265                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8755.415265                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8755.415265                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8755.415265                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8755.415265                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      4477144                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets           62                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           570538                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.758839                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          167                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.847232                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           62                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       270621                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       270621                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       270621                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       270621                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       270621                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       270621                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6504605                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6504605                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6504605                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6504605                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6504605                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6504605                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  47647231055                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  47647231055                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  47647231055                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  47647231055                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  47647231055                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  47647231055                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       253053                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       253053                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       253053                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       253053                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       253053                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       253053                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6043360                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6043360                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6043360                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6043360                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6043360                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6043360                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  44707631164                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  44707631164                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  44707631164                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  44707631164                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  44707631164                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  44707631164                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1699559498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1699559498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1699559498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1699559498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028246                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028246                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028246                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028246                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028246                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028246                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7325.153650                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7325.153650                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7325.153650                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7325.153650                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7325.153650                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7325.153650                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028194                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028194                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028194                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7397.810351                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  7397.810351                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  7397.810351                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     59245032                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2351166                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     52469358                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      1249562                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     60184765                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      4393414                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     48808124                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      3087530                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       200789                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2974157                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4925432                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       452633                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      3443064                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      5114963                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         3747306                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16276.136731                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          13593053                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3763332                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.611973                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      6997709500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4266.822439                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    59.073583                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    61.998615                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   875.814301                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3003.067946                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8009.359846                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.260426                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003606                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003784                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.053455                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.183293                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.488853                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.993417                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8909                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           95                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7022                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0          203                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          252                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3635                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         3246                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1573                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           72                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          759                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2892                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2491                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          768                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.543762                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005798                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.428589                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       294843936                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      294843936                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       600493                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       179726                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      6257574                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data      3196043                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total      10233836                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3548335                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3548335                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       119384                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       119384                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        38955                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        38955                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       985595                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       985595                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       600493                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       179726                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      6257574                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4181638                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       11219431                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       600493                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       179726                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      6257574                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4181638                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      11219431                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        16370                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        12947                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       246684                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data      1202213                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total      1478214                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            9                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            9                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       131869                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       131869                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       175118                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       175118                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           18                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total           18                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       304338                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       304338                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        16370                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        12947                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       246684                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1506551                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1782552                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        16370                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        12947                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       246684                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1506551                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1782552                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    782711292                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    885174343                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   6713721698                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  44470699734                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  52852307067                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2670586208                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2670586208                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3556484886                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3556484886                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3931499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3931499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15577643529                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  15577643529                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    782711292                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    885174343                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   6713721698                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  60048343263                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  68429950596                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    782711292                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    885174343                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   6713721698                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  60048343263                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  68429950596                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       616863                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       192673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      6504258                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data      4398256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total     11712050                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3548344                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3548344                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       251253                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       251253                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       214073                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       214073                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           18                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           18                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1289933                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1289933                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       616863                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       192673                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      6504258                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5688189                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     13001983                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       616863                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       192673                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      6504258                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5688189                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     13001983                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.026537                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.067197                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.037927                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.273339                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.126213                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000003                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000003                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.524845                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.524845                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.818029                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.818029                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.replacements         4158550                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16214.275256                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          12594287                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         4174696                       # Sample count of references to valid blocks.
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+system.cpu0.l2cache.tags.warmup_cycle      9944532000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  3315.303513                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    38.862270                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.140550                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   967.067959                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2910.372119                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8960.528846                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.202350                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002372                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001351                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.059025                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.177635                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.546907                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7728                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          951                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1001                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3816                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2122                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          566                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004761                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.471680                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       280330704                       # Number of tag accesses
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+system.cpu0.l2cache.Writeback_hits::writebacks      3975115                       # number of Writeback hits
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+system.cpu0.l2cache.UpgradeReq_hits::total       121282                       # number of UpgradeReq hits
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040778                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.285062                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.130355                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.719507                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.719507                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.503091                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.503091                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.790514                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.790514                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.235933                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.235933                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.026537                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.067197                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.037927                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.264856                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.137098                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.026537                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.067197                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.037927                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.264856                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.137098                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47813.762492                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 68369.069514                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 27215.878200                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36990.699430                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35754.164869                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20251.812086                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20251.812086                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20309.076657                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.076657                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 218416.611111                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218416.611111                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51185.338436                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51185.338436                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47813.762492                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 68369.069514                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 27215.878200                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39858.154993                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38388.754211                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47813.762492                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68369.069514                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 27215.878200                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39858.154993                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38388.754211                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs       218783                       # number of cycles access was blocked
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+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.268305                       # miss rate for demand accesses
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+system.cpu0.l2cache.overall_miss_rate::total     0.138650                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34658.489359                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34139.010283                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 27432.805640                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34790.290338                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33484.804522                       # average ReadReq miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 79701.265997                       # average WriteInvalidateReq miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 79701.265997                       # average WriteInvalidateReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20226.492471                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20226.492471                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20262.343701                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20262.343701                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       288500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       288500                       # average SCUpgradeFailReq miss latency
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+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44702.657471                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34658.489359                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34139.010283                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 27432.805640                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36618.495379                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 35214.995476                       # average overall miss latency
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+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36618.495379                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 35214.995476                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs       289229                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            9480                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs            8029                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    23.078376                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    36.023041                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1237814                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1237814                       # number of writebacks
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-system.cpu0.l2cache.Writeback_mshr_misses::total            9                       # number of Writeback MSHR misses
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-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       131869                       # number of UpgradeReq MSHR misses
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-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  49106078519                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  49106078519                       # number of WriteInvalidateReq MSHR miss cycles
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-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2297414257                       # number of UpgradeReq MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1519173000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5544879586                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7064052586                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5346512529                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5346512529                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1519173000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10891392115                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12410565115                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.026536                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066288                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.028093                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.266067                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.118006                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000003                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000003                       # mshr miss rate for Writeback accesses
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+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11883264160                       # number of overall MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.278529                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.122077                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.524845                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.524845                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.818029                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.818029                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.129074                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.129074                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.503091                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.503091                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.790514                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.790514                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.200020                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.200020                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.026536                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.066288                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.028093                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.251089                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.126143                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.026536                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.066288                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.028093                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.251089                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.185504                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.185504                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.025853                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256912                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.128447                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.025853                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256912                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.354862                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13837.367604                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 181083.277778                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 181083.277778                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40961.276755                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40961.276755                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23582.064847                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32082.226080                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31451.797521                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.417806                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       237500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       237500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1419,69 +1471,69 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      15637085                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     12009481                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        33046                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        33046                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3548344                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      4365503                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1683195                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp      1040668                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       461767                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       386684                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       535373                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq          113                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          191                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1436156                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1297014                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     13051451                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18246800                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       419537                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1341455                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         33059243                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    416613216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    664873226                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1541384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4934904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1087962730                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    9586812                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     27467610                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.337349                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.472805                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      15173335                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11005084                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31316                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        31316                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      3975122                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      5222365                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp           14                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       963549                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       792291                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       491639                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       333223                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       494297                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1332515                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1202467                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     12129286                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16997895                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       390025                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1185916                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         30703122                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    387114336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    641181457                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1414144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4287888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1033997825                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   10518238                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     27441081                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.371527                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.483213                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          18201451     66.27%     66.27% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6           9266159     33.73%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          17245975     62.85%     62.85% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6          10195106     37.15%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      27467610                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   13754094390                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      27441081                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   13452656135                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    197445482                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    192867736                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9792438220                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9099601288                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9396795912                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8421572630                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    228193109                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    213967447                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    726243001                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    651243914                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              126883394                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         85166335                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6223569                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            90014178                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               58475937                       # Number of BTB hits
+system.cpu1.branchPred.lookups              133961841                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89061347                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6618163                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            94585757                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               62217505                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            64.963029                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16774062                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            171946                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            65.778936                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               18340774                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            186545                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1505,25 +1557,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    93423769                       # DTB read hits
-system.cpu1.dtb.read_misses                    385141                       # DTB read misses
-system.cpu1.dtb.write_hits                   77506370                       # DTB write hits
-system.cpu1.dtb.write_misses                   166753                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    98830623                       # DTB read hits
+system.cpu1.dtb.read_misses                    443426                       # DTB read misses
+system.cpu1.dtb.write_hits                   80619639                       # DTB write hits
+system.cpu1.dtb.write_misses                   165440                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              46078                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   38053                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      411                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6413                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   44150                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      612                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6848                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    42956                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                93808910                       # DTB read accesses
-system.cpu1.dtb.write_accesses               77673123                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    42554                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                99274049                       # DTB read accesses
+system.cpu1.dtb.write_accesses               80785079                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        170930139                       # DTB hits
-system.cpu1.dtb.misses                         551894                       # DTB misses
-system.cpu1.dtb.accesses                    171482033                       # DTB accesses
+system.cpu1.dtb.hits                        179450262                       # DTB hits
+system.cpu1.dtb.misses                         608866                       # DTB misses
+system.cpu1.dtb.accesses                    180059128                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1545,519 +1597,533 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   200532583                       # ITB inst hits
-system.cpu1.itb.inst_misses                     85074                       # ITB inst misses
+system.cpu1.itb.inst_hits                   211899162                       # ITB inst hits
+system.cpu1.itb.inst_misses                     88988                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              46078                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   26827                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   32114                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   221691                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   230833                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               200617657                       # ITB inst accesses
-system.cpu1.itb.hits                        200532583                       # DTB hits
-system.cpu1.itb.misses                          85074                       # DTB misses
-system.cpu1.itb.accesses                    200617657                       # DTB accesses
-system.cpu1.numCycles                       671498045                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               211988150                       # ITB inst accesses
+system.cpu1.itb.hits                        211899162                       # DTB hits
+system.cpu1.itb.misses                          88988                       # DTB misses
+system.cpu1.itb.accesses                    211988150                       # DTB accesses
+system.cpu1.numCycles                       705261968                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          76057268                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     563958948                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  126883394                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          75249999                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    570112426                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13401984                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1796129                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              140886                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6366912                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       711415                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       284551                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                200289545                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1511940                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  28568                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         662170579                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.001134                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.225253                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          81258744                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     595261780                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  133961841                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          80558279                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    597026773                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14270848                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1888771                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              137791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6543938                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       793820                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       311963                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                211646234                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1619349                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  28847                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         695097224                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.005850                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.225976                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               344731960     52.06%     52.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               123888404     18.71%     70.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                41617512      6.29%     77.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               151932703     22.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               360486788     51.86%     51.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               129920524     18.69%     70.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                44826389      6.45%     77.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               159863523     23.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           662170579                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.188956                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.839852                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                93652150                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            319101856                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                208055943                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             36600277                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4760353                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            17735520                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1981049                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             585316730                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             21686226                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4760353                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               127273008                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               44978505                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     215016897                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                210494675                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             59647141                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             569572737                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5483527                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              8310630                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                236317                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                296206                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              25698514                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           13591                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          543172602                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            884661173                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       673765883                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           933137                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            489609146                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                53563450                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15680851                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13859127                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 73666324                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            93680638                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           80687792                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8658535                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7660349                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 547737456                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15869030                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                553093233                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2542275                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       47705580                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     32628806                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        263861                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    662170579                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.835273                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.067651                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           695097224                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.189946                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.844029                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                99752260                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            332349824                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                219841712                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             38085588                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5067840                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            18995502                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2109796                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             616514692                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             22877728                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5067840                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               135033848                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               48639647                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     225189127                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                222148294                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             59018468                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             599774214                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5804898                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              8803158                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                361913                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                923044                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              23085631                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           14113                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          571116000                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            927515458                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       708750961                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           721490                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            514023695                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                57092304                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          16265387                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      14239236                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 76589893                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            99537313                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           83963206                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          9607701                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         8257946                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 576970515                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           16478044                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                581773999                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2685793                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       50643585                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     34938077                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        295595                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    695097224                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.836968                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.068825                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          358036858     54.07%     54.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          130663379     19.73%     73.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          105371554     15.91%     89.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           60712008      9.17%     98.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7383178      1.11%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               3602      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          375720628     54.05%     54.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          136500819     19.64%     73.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          111041420     15.97%     89.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           64151608      9.23%     98.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7678235      1.10%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               4508      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                  6      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      662170579                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      695097224                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               55137578     43.73%     43.73% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 43337      0.03%     43.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  11462      0.01%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              21      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              33948572     26.92%     70.70% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             36949037     29.30%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               58467261     44.14%     44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 65736      0.05%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   8975      0.01%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              28      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              36077917     27.24%     71.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             37847209     28.57%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            376818141     68.13%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1181294      0.21%     68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                70304      0.01%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.36% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         78003      0.01%     68.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            96248927     17.40%     85.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           78696516     14.23%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            396486231     68.15%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1392625      0.24%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                78812      0.01%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         42928      0.01%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           101899765     17.52%     85.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           81873638     14.07%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             553093233                       # Type of FU issued
-system.cpu1.iq.rate                          0.823671                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  126090007                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.227972                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1895671563                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        610922154                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    537423673                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1317762                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            530370                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       489519                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             678367586                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 815653                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2464833                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             581773999                       # Type of FU issued
+system.cpu1.iq.rate                          0.824905                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  132467126                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.227695                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1992741902                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        643831652                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    565540483                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1056239                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            418449                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       388115                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             713583395                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 657730                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2682619                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11666973                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        15967                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       141534                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5620813                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12570649                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16823                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       158978                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5834378                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2485085                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4066782                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2724944                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      3729174                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4760353                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                6088373                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2643428                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          563729528                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5067840                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                8144414                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2028582                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          593577386                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             93680638                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            80687792                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13644540                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 61293                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2520664                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        141534                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1916152                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2651693                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4567845                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            545961284                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             93419699                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6590982                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             99537313                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            83963206                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          14010879                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 57965                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1901764                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        158978                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2040667                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2820650                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4861317                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            574179310                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             98827451                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6993764                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       123042                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   170926883                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               102016204                       # Number of branches executed
-system.cpu1.iew.exec_stores                  77507184                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.813050                       # Inst execution rate
-system.cpu1.iew.wb_sent                     538581721                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    537913192                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                259879872                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                425846883                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       128827                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   179445358                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               107524158                       # Number of branches executed
+system.cpu1.iew.exec_stores                  80617907                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.814136                       # Inst execution rate
+system.cpu1.iew.wb_sent                     566651750                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    565928598                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                274900610                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                450009146                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.801064                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610266                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.802437                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610878                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       44555907                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15605169                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4282930                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    653744993                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.784392                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.576833                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       47337627                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       16182449                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4550579                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    686146419                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.786229                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.582193                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    427404365     65.38%     65.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    119117281     18.22%     83.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     49133324      7.52%     91.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     16524443      2.53%     93.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11998035      1.84%     95.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8093886      1.24%     96.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5471403      0.84%     97.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3473274      0.53%     98.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12528982      1.92%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    448874592     65.42%     65.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    124520992     18.15%     83.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     51724584      7.54%     91.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     17115210      2.49%     93.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12441515      1.81%     95.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8692682      1.27%     96.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5812900      0.85%     97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3666336      0.53%     98.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     13297608      1.94%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    653744993                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           435068948                       # Number of instructions committed
-system.cpu1.commit.committedOps             512792020                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    686146419                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           458333534                       # Number of instructions committed
+system.cpu1.commit.committedOps             539467876                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     157080643                       # Number of memory references committed
-system.cpu1.commit.loads                     82013664                       # Number of loads committed
-system.cpu1.commit.membars                    3580423                       # Number of memory barriers committed
-system.cpu1.commit.branches                  96770677                       # Number of branches committed
-system.cpu1.commit.fp_insts                    477739                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                470356347                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12430117                       # Number of function calls committed.
+system.cpu1.commit.refs                     165095491                       # Number of memory references committed
+system.cpu1.commit.loads                     86966664                       # Number of loads committed
+system.cpu1.commit.membars                    3858042                       # Number of memory barriers committed
+system.cpu1.commit.branches                 101991370                       # Number of branches committed
+system.cpu1.commit.fp_insts                    379596                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                495494093                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13607824                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       354618766     69.15%     69.15% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         966577      0.19%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           56200      0.01%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        69792      0.01%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       82013664     15.99%     85.36% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75066979     14.64%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       373132612     69.17%     69.17% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1140635      0.21%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           62088      0.01%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        37050      0.01%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       86966664     16.12%     85.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      78128827     14.48%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        512792020                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12528982                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total        539467876                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             13297608                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                  1194813735                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1123082959                       # The number of ROB writes
-system.cpu1.timesIdled                         724798                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        9327466                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94087851225                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  435068948                       # Number of Instructions Simulated
-system.cpu1.committedOps                    512792020                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.543429                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.543429                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.647908                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.647908                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               645605353                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              381721004                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   775313                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  445860                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                118711593                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               119446570                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             2680324661                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15740060                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5270583                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          418.735038                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          145844611                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5271093                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.668761                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8472891797000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   418.735038                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.817842                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.817842                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        326008687                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       326008687                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     76031229                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       76031229                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     65289331                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      65289331                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       171825                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       171825                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       535551                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       535551                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1744878                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1744878                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1734724                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1734724                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    141320560                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       141320560                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    141492385                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      141492385                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6360074                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6360074                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7315323                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7315323                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       690767                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       690767                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       239985                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       239985                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       206300                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       206300                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13675397                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13675397                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     14366164                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     14366164                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  96502365280                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  96502365280                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 122289774326                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3384586861                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3384586861                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4391846948                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4391846948                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4067000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4067000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 218792139606                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 218792139606                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     82391303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     82391303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     72604654                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     72604654                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       862592                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       862592                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       535551                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       535551                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1984863                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1984863                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1941024                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1941024                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    154995957                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    154995957                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    155858549                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    155858549                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.077194                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.077194                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.100756                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.100756                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.800804                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.800804                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120908                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120908                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106284                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106284                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.088231                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.088231                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.092174                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.092174                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501                       # average StoreCondReq miss latency
+system.cpu1.rob.rob_reads                  1255653176                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1182522736                       # The number of ROB writes
+system.cpu1.timesIdled                         784634                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       10164744                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94139293558                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  458333534                       # Number of Instructions Simulated
+system.cpu1.committedOps                    539467876                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.538753                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.538753                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.649877                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.649877                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               678371688                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              402814905                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   627803                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  323588                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                123299886                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               123979632                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             2817640596                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              16155257                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5719154                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          428.720007                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          153241322                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5719665                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            26.792010                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8515430590500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   428.720007                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.837344                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.837344                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        342874086                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       342874086                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     80584085                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       80584085                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     68058878                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      68058878                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187635                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       187635                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       112453                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total       112453                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1764554                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1764554                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1816897                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1816897                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    148642963                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       148642963                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    148830598                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      148830598                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6869643                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6869643                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7494314                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7494314                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       706318                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       706318                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       458418                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       458418                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       288948                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       288948                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       190861                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       190861                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     14363957                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      14363957                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     15070275                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     15070275                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 105402463849                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 121649241613                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  17403154350                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  17403154350                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4078869410                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   4078869410                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3937390159                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3937390159                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1956500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1956500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 227051705462                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 227051705462                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     87453728                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     87453728                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     75553192                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     75553192                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       893953                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       893953                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       570871                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       570871                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2053502                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2053502                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2007758                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2007758                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    163006920                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    163006920                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    163900873                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    163900873                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.078552                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.078552                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.099193                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.099193                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.790106                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.790106                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.803015                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.803015                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.140710                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.140710                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095062                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095062                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.088119                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.088119                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.091947                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.091947                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      8615413                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     17976416                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           462301                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         741969                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    18.635938                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    24.227988                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                 535551                       # number of fast writes performed
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      4622048                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     18188306                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           368036                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         754235                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    12.558684                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    24.114906                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3043634                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3043634                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3366977                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3366977                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5934775                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5934775                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       123858                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       123858                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9301752                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9301752                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9301752                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9301752                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2993097                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2993097                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1369794                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1369794                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       690691                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       690691                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116127                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116127                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       206288                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       206288                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4362891                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4362891                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5053582                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5053582                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38940153004                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38940153004                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23265516814                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23265516814                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16955467787                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16955467787                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  29882890933                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  29882890933                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1431846930                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1431846930                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3970245052                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3970245052                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3877000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3877000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  62205669818                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  62205669818                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  79161137605                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  79161137605                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    568928684                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    568928684                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    634602446                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    634602446                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1203531130                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1203531130                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036328                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036328                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018866                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018866                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.800716                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.800716                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058506                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058506                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106278                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106278                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028148                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028148                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032424                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032424                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3658567                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3658567                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3579229                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3579229                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6058526                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      6058526                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3270                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total         3270                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       146042                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       146042                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9637755                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9637755                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9637755                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9637755                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3290414                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3290414                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1435788                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1435788                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       706224                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       706224                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       455148                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       455148                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       142906                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       142906                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       190858                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       190858                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4726202                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4726202                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5432426                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5432426                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  44800014998                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  44800014998                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23381887855                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23381887855                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16359112476                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16359112476                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  16414544257                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  16414544257                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1722097666                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1722097666                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3546227841                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3546227841                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1864500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1864500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  68181902853                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  68181902853                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  84541015329                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  84541015329                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    790979694                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    790979694                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    944680456                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    944680456                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1735660150                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1735660150                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037625                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037625                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019004                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019004                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.790001                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.790001                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.797287                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.797287                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069591                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069591                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095060                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095060                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028994                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.028994                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033145                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033145                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2065,446 +2131,464 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5515063                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.927395                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          194540892                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5515575                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            35.271190                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8512592975000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.927395                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980327                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980327                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5881686                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.904324                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          205507195                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5882198                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            34.937143                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8555135625500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.904324                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980282                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.980282                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           87                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          371                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        406089111                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       406089111                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    194540892                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      194540892                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    194540892                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       194540892                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    194540892                       # number of overall hits
-system.cpu1.icache.overall_hits::total      194540892                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5745874                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5745874                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5745874                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5745874                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5745874                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5745874                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  49972720911                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  49972720911                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  49972720911                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  49972720911                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  49972720911                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  49972720911                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    200286766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    200286766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    200286766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    200286766                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    200286766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    200286766                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028688                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028688                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028688                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028688                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028688                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028688                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8697.148756                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8697.148756                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8697.148756                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8697.148756                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8697.148756                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8697.148756                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      4058036                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses        429168724                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       429168724                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    205507195                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      205507195                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    205507195                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       205507195                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    205507195                       # number of overall hits
+system.cpu1.icache.overall_hits::total      205507195                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6136058                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6136058                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6136058                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6136058                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6136058                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6136058                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53889413624                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  53889413624                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  53889413624                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  53889413624                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  53889413624                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  53889413624                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    211643253                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    211643253                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    211643253                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    211643253                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    211643253                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    211643253                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028992                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.028992                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028992                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.028992                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028992                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.028992                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8782.415946                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8782.415946                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8782.415946                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8782.415946                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8782.415946                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8782.415946                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      4496430                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           525950                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           574651                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.715631                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.824627                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       230295                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       230295                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       230295                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       230295                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       230295                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       230295                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5515579                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5515579                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5515579                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5515579                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5515579                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5515579                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  40507461081                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  40507461081                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  40507461081                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  40507461081                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  40507461081                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  40507461081                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6176248                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6176248                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6176248                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6176248                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027538                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027538                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027538                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027538                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027538                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027538                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7344.190171                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7344.190171                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7344.190171                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  7344.190171                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7344.190171                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  7344.190171                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       253840                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       253840                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       253840                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       253840                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       253840                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       253840                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5882218                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5882218                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5882218                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5882218                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5882218                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5882218                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  43727434357                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  43727434357                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  43727434357                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  43727434357                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  43727434357                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  43727434357                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6637997                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6637997                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6637997                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      6637997                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027793                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.027793                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.027793                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7433.834373                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  7433.834373                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  7433.834373                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     50505684                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2064047                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     44628493                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       907161                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     56932742                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2823095                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     47812216                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      2677811                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       133845                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2772138                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4283124                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       382726                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      3236886                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4916498                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         3436745                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13730.844001                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          11600969                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         3452900                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            3.359776                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9794240275500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4681.996556                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    70.505551                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    81.585621                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   599.676687                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2582.188700                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  5714.890886                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.285766                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004303                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004980                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036601                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.157604                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.348809                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.838064                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9001                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         7069                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0          110                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          838                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         3805                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         2947                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1301                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           61                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          786                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3475                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2116                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          647                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.549377                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.431458                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       248779915                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      248779915                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       532626                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       172045                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5284751                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2703668                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       8693090                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3043623                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3043623                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        90999                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        90999                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        33582                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        33582                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       896481                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       896481                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       532626                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       172045                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5284751                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3600149                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9589571                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       532626                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       172045                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5284751                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3600149                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9589571                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        15803                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        12743                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       230826                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data      1092537                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1351909                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks           10                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total           10                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       129352                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       129352                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       172689                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       172689                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           17                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total           17                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       259572                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       259572                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        15803                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker        12743                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       230826                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1352109                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1611481                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        15803                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker        12743                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       230826                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1352109                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1611481                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    757783063                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    830879579                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   5925678894                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  36970844217                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  44485185753                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2628732175                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2628732175                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3477493272                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3477493272                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3782000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3782000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12238175338                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  12238175338                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    757783063                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    830879579                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   5925678894                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  49209019555                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  56723361091                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    757783063                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    830879579                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   5925678894                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  49209019555                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  56723361091                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       548429                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       184788                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5515577                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3796205                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total     10044999                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3043633                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3043633                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       220351                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       220351                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       206271                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       206271                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           17                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           17                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1156053                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1156053                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       548429                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       184788                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5515577                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4952258                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     11201052                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       548429                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       184788                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5515577                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4952258                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     11201052                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.028815                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.068960                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.041850                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.287797                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.134585                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000003                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000003                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.587027                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.587027                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.837195                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.837195                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.replacements         4092617                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13780.930785                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          12621619                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         4108487                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            3.072084                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9637211064000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  3757.362843                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    62.809020                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    56.863279                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   599.057552                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3491.075179                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  5813.762913                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.229331                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003834                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003471                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036564                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.213078                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.354844                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.841121                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8933                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6853                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           68                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          777                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         3625                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         2921                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1542                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           64                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3137                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2007                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          750                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.545227                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005127                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.418274                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       271640392                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      271640392                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       596119                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       184681                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5616426                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data      2971260                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total       9368486                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3658557                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3658557                       # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       182266                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total       182266                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        95807                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        95807                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        41710                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        41710                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       960995                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       960995                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       596119                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       184681                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5616426                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3932255                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       10329481                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       596119                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       184681                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      5616426                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3932255                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      10329481                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        16104                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        12169                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst       265788                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data      1166045                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total      1460106                       # number of ReadReq misses
+system.cpu1.l2cache.Writeback_misses::writebacks            9                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total            9                       # number of Writeback misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       271820                       # number of WriteInvalidateReq misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::total       271820                       # number of WriteInvalidateReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       129531                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       129531                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       149141                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       149141                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       255657                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       255657                       # number of ReadExReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        16104                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker        12169                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       265788                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1421702                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1715763                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        16104                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker        12169                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       265788                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1421702                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1715763                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    666484538                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    571688851                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   6944017926                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  40559833009                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total  48742024324                       # number of ReadReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data  11677447356                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total  11677447356                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2603211060                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2603211060                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3027794367                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3027794367                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1818500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1818500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11891425269                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  11891425269                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    666484538                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    571688851                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   6944017926                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  52451258278                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  60633449593                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    666484538                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    571688851                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   6944017926                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  52451258278                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  60633449593                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       612223                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       196850                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5882214                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.data      4137305                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total     10828592                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3658566                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3658566                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       454086                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total       454086                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       225338                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       225338                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       190851                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       190851                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1216652                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1216652                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       612223                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       196850                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5882214                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      5353957                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     12045244                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       612223                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       196850                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5882214                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      5353957                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     12045244                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026304                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.061819                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.045185                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.281837                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.134838                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.598609                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.598609                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.574830                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.574830                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.781453                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.781453                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.224533                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.224533                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.028815                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.068960                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.041850                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.273029                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.143869                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.028815                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.068960                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.041850                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.273029                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.143869                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47951.848573                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65202.823432                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 25671.626654                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 33839.443623                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32905.458691                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20322.315658                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20322.315658                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20137.317791                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20137.317791                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 222470.588235                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 222470.588235                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47147.517213                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47147.517213                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47951.848573                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 65202.823432                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 25671.626654                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36394.269659                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35199.522111                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47951.848573                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 65202.823432                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 25671.626654                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36394.269659                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35199.522111                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs       100701                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210132                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210132                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026304                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.061819                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.045185                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.265542                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.142443                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026304                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.061819                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.045185                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.265542                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.142443                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26126.152896                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34784.106110                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33382.524504                       # average ReadReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 42960.221308                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 42960.221308                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20097.204993                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20097.204993                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20301.556024                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20301.556024                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259785.714286                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259785.714286                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46513.200378                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46513.200378                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26126.152896                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36893.285849                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 35339.058829                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26126.152896                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36893.285849                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 35339.058829                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs       176494                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs            5340                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs            8388                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    18.857865                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    21.041249                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1046487                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1046487                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            8                       # number of ReadReq MSHR hits
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-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            8                       # number of overall MSHR hits
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-system.cpu1.l2cache.overall_mshr_hits::total        99339                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        15795                       # number of ReadReq MSHR misses
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-system.cpu1.l2cache.ReadReq_mshr_misses::total      1284880                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks           10                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total           10                       # number of Writeback MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2771770                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total      2771770                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       129352                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       129352                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172689                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172689                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           17                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           17                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       227262                       # number of ReadExReq MSHR misses
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-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        15795                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1313167                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total      4283912                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    645813787                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  88845492183                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  88845492183                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  25545271269                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25545271269                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2271880441                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2271880441                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2355036377                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3117000                       # number of SCUpgradeFailReq MSHR miss cycles
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-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8386609809                       # number of ReadExReq MSHR miss cycles
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-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5617250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    522273803                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    527891053                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    592984543                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    592984543                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1115258346                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1120875596                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.028800                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.068143                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.030928                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.286050                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.127912                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000003                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000003                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.writebacks::writebacks      1389640                       # number of writebacks
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    478828801                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   4373003012                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39351297895                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 163956146412                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6077501                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    736923302                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    743000803                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    890555024                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    890555024                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6077501                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1627478326                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1633555827                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.279663                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.127597                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.587027                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.587027                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.837195                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.837195                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.198134                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.198134                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.574830                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.574830                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.781453                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.781453                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.196584                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.196584                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.028800                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.068143                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.030928                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.265165                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.135000                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.028800                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.068143                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.030928                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.265165                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.180399                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.180399                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.257106                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132931                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.257106                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.382456                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.401623                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2514,66 +2598,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      14195138                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10319504                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         5540                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         5540                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3043633                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      4072942                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            7                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1683351                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       535551                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       440112                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       381311                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       495883                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq          113                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          191                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1326326                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1162072                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11031290                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15072798                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       408972                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1223990                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         27737050                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    352998000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    552975725                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1478304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4387432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         911839461                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   10107713                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     25138246                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.388398                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.487386                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq      15325840                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     11081361                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         7210                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         7210                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3658566                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      4807205                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           18                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       637593                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       454086                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       471082                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       336358                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       477965                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1352070                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1222067                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11764566                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16293479                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       431287                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1341589                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         29830921                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    376462768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    612089908                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1574800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4897784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         995025260                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   10166385                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     26584709                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.370632                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.482974                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          15374612     61.16%     61.16% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6           9763634     38.84%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          16731578     62.94%     62.94% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6           9853131     37.06%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      25138246                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   11278575992                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      26584709                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   12493291014                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    196968741                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    175961487                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8281966249                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8832336643                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7967439656                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8528127192                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    225433169                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    235484276                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    677266087                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    730977975                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40417                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40417                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136643                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136782                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq          139                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48150                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40396                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40396                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136775                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30047                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2588,13 +2672,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123084                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231234                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231234                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123062                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231200                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231200                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354398                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48170                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354342                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48148                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2609,13 +2693,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156191                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338952                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156169                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338816                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338816                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7497229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36599000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7497071                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36581000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2643,678 +2727,710 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           982013630                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1043032876                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93033000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            93018000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179230570                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179190812                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115615                       # number of replacements
-system.iocache.tags.tagsinuse               11.386738                       # Cycle average of tags in use
+system.iocache.tags.replacements               115581                       # number of replacements
+system.iocache.tags.tagsinuse               11.295325                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115597                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9111214571000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.838966                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.547771                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239935                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.471736                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.711671                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9153631711000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.835501                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.459825                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.239719                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466239                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705958                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1042022                       # Number of tag accesses
-system.iocache.tags.data_accesses             1042022                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106728                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106728                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1040757                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040757                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8889                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8926                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8872                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8909                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide          139                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total          139                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8889                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8929                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8872                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8912                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8889                       # number of overall misses
-system.iocache.overall_misses::total             8929                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5695000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1981823591                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1987518591                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8872                       # number of overall misses
+system.iocache.overall_misses::total             8912                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1960529318                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1966236318                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       365000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       365000                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      6060000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1981823591                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1987883591                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      6060000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1981823591                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1987883591                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28841569746                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28841569746                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      6072000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1960529318                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1966601318                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      6072000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1960529318                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1966601318                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8889                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8926                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8872                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8909                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106867                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106867                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8889                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8929                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8872                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8912                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8889                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8929                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8872                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8912                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.001301                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.001301                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 153918.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 222952.367083                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 222666.210060                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 220702.246941                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total 121666.666667                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       151500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 222952.367083                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 222632.275843                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       151500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 222952.367083                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 222632.275843                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         55347                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       151800                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 220979.409152                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 220668.909111                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       151800                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 220979.409152                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 220668.909111                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        224453                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27297                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.081421                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.222625                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106728                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8889                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8926                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8872                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8909                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8889                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8929                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8872                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8912                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8889                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8929                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3771000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1519438621                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1523209621                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8872                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8912                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1499010380                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1502793380                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       209000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       209000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6630698579                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6630698579                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3980000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1519438621                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1523418621                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3980000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1519438621                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1523418621                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23291152308                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23291152308                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3992000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1499010380                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1503002380                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3992000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1499010380                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1503002380                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 170614.696047                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 170614.696047                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99800                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 168649.279623                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99800                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 168649.279623                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1387044                       # number of replacements
-system.l2c.tags.tagsinuse                64427.808632                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    7620997                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1449367                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     5.258155                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   10003.170740                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   188.441651                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   243.424548                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      921.507825                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8419.959281                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   189.151688                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   259.454485                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      442.813505                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     5057.928398                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.152636                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002875                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003714                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.014061                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.128478                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.370744                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002886                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003959                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.006757                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.077178                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.219801                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983090                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        33631                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          302                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        28390                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           18                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1           86                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         2393                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1787                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        29347                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1           16                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           34                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          216                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2265                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4264                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        21604                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.513168                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004608                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.433197                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 91165244                       # Number of tag accesses
-system.l2c.tags.data_accesses                91165244                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         7553                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             170694                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             696092                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1825935                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         8223                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5157                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             162945                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             691200                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1816536                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                5388636                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2284318                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2284318                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           28567                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           31425                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               59992                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          8944                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          7440                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             16384                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            53362                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53750                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107112                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          7553                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              170694                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              749454                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher      1825935                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          8223                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5157                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              162945                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              744950                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher      1816536                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 5495748                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         7553                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4301                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             170694                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             749454                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher      1825935                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         8223                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5157                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             162945                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             744950                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher      1816536                       # number of overall hits
-system.l2c.overall_hits::total                5495748                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         5517                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         8182                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            12718                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           197063                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       598730                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         5285                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         7231                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             8328                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           136549                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       456002                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total              1435605                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         38751                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         39177                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             77928                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        11922                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         9604                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           21526                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          91592                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          67962                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             159554                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         5517                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         8182                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             12718                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            288655                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       598730                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         5285                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         7231                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              8328                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            204511                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       456002                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1595159                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         5517                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         8182                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            12718                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           288655                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       598730                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         5285                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         7231                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             8328                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           204511                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       456002                       # number of overall misses
-system.l2c.overall_misses::total              1595159                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    458859494                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    660185236                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   1228334988                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  18297393453                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  72887603477                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    440607992                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    598540979                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    788794491                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  12800911061                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  55801999034                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total   163963230205                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    163981726                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    172729371                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    336711097                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     59985022                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     52908784                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    112893806                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7434747873                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5448950117                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12883697990                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    458859494                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    660185236                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1228334988                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  25732141326                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  72887603477                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    440607992                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    598540979                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    788794491                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  18249861178                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  55801999034                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    176846928195                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    458859494                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    660185236                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1228334988                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  25732141326                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  72887603477                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    440607992                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    598540979                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    788794491                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  18249861178                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  55801999034                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   176846928195                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        13070                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        12483                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         183412                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         893155                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2424665                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        13508                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        12388                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         171273                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         827749                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2272538                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            6824241                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2284318                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2284318                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        67318                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        70602                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          137920                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        20866                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        17044                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         37910                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       144954                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       121712                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           266666                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        13070                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        12483                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          183412                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1038109                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2424665                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        13508                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        12388                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          171273                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          949461                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2272538                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             7090907                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        13070                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        12483                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         183412                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1038109                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2424665                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        13508                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        12388                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         171273                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         949461                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2272538                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            7090907                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.422112                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.655451                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.069341                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.220637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.246933                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.391250                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.583710                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.048624                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.164964                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.200658                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.210368                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.575641                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.554899                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.565023                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.571360                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.563483                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.567819                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.631869                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.558384                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.598329                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.422112                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.655451                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.069341                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.278058                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.246933                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.391250                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.583710                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.048624                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.215397                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.200658                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.224958                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.422112                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.655451                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.069341                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.278058                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.246933                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.391250                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.583710                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.048624                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.215397                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.200658                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.224958                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83171.922059                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80687.513566                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 96582.401950                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 92850.476513                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83369.534910                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82774.302171                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 94715.957133                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 93745.915832                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 114211.938663                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4231.677273                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4408.948388                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4320.797364                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5031.456299                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5509.036235                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5244.532472                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81172.459090                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80176.423840                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 80748.198040                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83171.922059                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80687.513566                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 96582.401950                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 89144.970037                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83369.534910                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82774.302171                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 94715.957133                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 89236.574942                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 110864.765327                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83171.922059                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80687.513566                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 96582.401950                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 89144.970037                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83369.534910                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82774.302171                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 94715.957133                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 89236.574942                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 110864.765327                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             23951                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1916125                       # number of replacements
+system.l2c.tags.tagsinuse                64884.880884                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    8755676                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1978999                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.424295                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               3437261500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    8337.656958                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    17.346754                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    14.129416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      627.039592                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3445.654069                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   351.392171                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   435.207962                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      621.389971                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11403.863316                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.127223                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000265                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000216                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.009568                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.052577                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.235173                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005362                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006641                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.009482                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.174009                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.369551                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.990065                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        38428                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          201                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        24245                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1          143                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         2926                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         6291                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        29058                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2           14                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          187                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1447                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2670                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        19923                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.586365                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003067                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.369949                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 93004482                       # Number of tag accesses
+system.l2c.tags.data_accesses                93004482                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         9030                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6306                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             171973                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             713080                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1991967                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         8819                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5864                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             186687                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             740221                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      2136612                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                5970559                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         3063024                       # number of Writeback hits
+system.l2c.Writeback_hits::total              3063024                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data        47241                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::cpu1.data        45742                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::total        92983                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.data           33885                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           29324                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               63209                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          7714                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          7828                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             15542                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            60878                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            59021                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               119899                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          9030                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6306                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              171973                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              773958                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher      1991967                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          8819                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5864                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              186687                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              799242                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher      2136612                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 6090458                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         9030                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6306                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             171973                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             773958                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher      1991967                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         8819                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5864                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             186687                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             799242                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher      2136612                       # number of overall hits
+system.l2c.overall_hits::total                6090458                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         1923                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         1303                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            12603                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           144091                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       852232                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker         3910                       # number of ReadReq misses
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+system.l2c.WriteInvalidateReq_misses::total        48318                       # number of WriteInvalidateReq misses
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+system.l2c.UpgradeReq_misses::cpu1.data         36221                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             73559                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         9578                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           19480                       # number of SCUpgradeReq misses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data    165935687                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    341290592                       # number of UpgradeReq miss cycles
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+system.l2c.ReadReq_accesses::total            7720095                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      3063024                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          3063024                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data        76778                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        65545                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          136768                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        17292                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        17730                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         35022                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       113779                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu0.dtb.walker        10953                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            7946439                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu0.inst      0.068281                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.168101                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.inst      0.053882                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.226621                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.384707                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.291075                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.341951                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.524241                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.552613                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.537838                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.553898                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.558488                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.556222                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.464945                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.475672                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.470280                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.171245                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.068281                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.202886                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.394840                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.053882                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.214033                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.206170                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.233561                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.171245                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.068281                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.202886                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.394840                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.053882                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.214033                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.206170                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.233561                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 98271.303579                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 96013.027038                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 95234.409236                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 90710.394841                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 151108.769214                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   340.069404                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   556.818966                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   424.319032                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4696.419332                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4581.201154                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4639.685042                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5084.462518                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5571.975964                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5332.273511                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83642.321676                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81746.910167                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 82688.891136                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 98271.303579                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 92690.949572                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 95234.409236                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 88505.270864                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 147184.723697                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 98271.303579                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 92690.949572                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 95234.409236                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 88505.270864                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 147184.723697                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             89319                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      978                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     3582                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     24.489775                       # average number of cycles each access was blocked
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 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
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+system.l2c.demand_mshr_miss_latency::cpu0.data  15810969380                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    283035747                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    279220250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    879069489                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  16556979239                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  72582930119                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 250500278615                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    153132498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    103417998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1081620491                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  15810969380                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 142769903404                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    283035747                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    279220250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    879069489                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  16556979239                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  72582930119                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 250500278615                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1103207000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4952355997                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4307750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    415818753                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6475689500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4782466503                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    497465997                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5279932500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4751952495                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4753250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    613999250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6473911995                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4501573998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    766793502                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5268367500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1103207000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9734822500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4307750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    913284750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11755622000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.422112                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.655451                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.069216                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.220588                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.246804                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.391250                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.583710                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.048455                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.164922                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.200507                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.210253                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.575641                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.554899                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.565023                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.571360                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.563483                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.567819                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.631869                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.558384                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.598329                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.422112                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.655451                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.069216                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.278016                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.246804                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.391250                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.583710                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.048455                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.215360                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.200507                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.224847                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.422112                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.655451                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.069216                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.278016                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.246804                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.391250                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.583710                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.048455                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.215360                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.200507                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.224847                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 98604.649565                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 98604.649565                       # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9253526493                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4753250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1380792752                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11742279495                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.168066                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.181431                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.226536                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.384707                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.291075                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.341951                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.524241                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.552613                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.537838                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.553898                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.558488                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.556222                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.464945                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.475672                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.470280                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.202855                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.299552                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.214002                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.233479                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.202855                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.299552                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.214002                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.233479                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71179.305627                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 85938.383204                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82860.730418                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135016.780662                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82860.730418                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135016.780662                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -3329,57 +3445,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             1503713                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1503713                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38586                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38586                       # Transaction distribution
-system.membus.trans_dist::Writeback            882638                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1682947                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1682947                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           373970                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         331267                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          103150                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            170539                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           155861                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123084                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq             1817706                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1817706                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38526                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38526                       # Transaction distribution
+system.membus.trans_dist::Writeback           1444194                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       154200                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       154200                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           434662                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         279066                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           97607                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            117028                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102726                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123062                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26002                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      8087433                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      8236597                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       229762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                8466359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156191                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25796                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6008493                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6157429                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       336112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6493541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156169                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52004                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    259532552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    259741319                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7302720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7302720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               267044039                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           618323                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4885385                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    207457224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    207665557                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14110208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14110208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               221775765                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           633029                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4186947                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4885385    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4186947    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4885385                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98770920                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4186947                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98514469                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               45500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21644945                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21244987                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         25191464236                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        16556458898                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         16738053981                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        17312327015                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          187451430                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          187280188                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3423,49 +3539,49 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            7757807                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7750243                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38586                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38586                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2284318                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1682954                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1576219                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          430271                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        347651                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         777922                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          191                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          191                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           316482                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          316482                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     11788342                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9897130                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              21685472                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    381410986                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    320139805                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              701550791                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1633796                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         12761522                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.009063                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.094770                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            8653355                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           8646086                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38526                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38526                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3063024                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       248029                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp       141301                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          493306                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        294608                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         787914                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           97                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           273153                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          273153                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10956928                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10351144                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              21308072                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    369780529                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    344544100                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              714324629                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1644746                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         12968411                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.008917                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.094008                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               12645858     99.09%     99.09% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115664      0.91%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               12852771     99.11%     99.11% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115640      0.89%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           12761522                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        21862906503                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           12968411                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        19352517195                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          6130500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          7381500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       19509958221                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       20456793572                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       17925237290                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       20083133002                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   14096                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   13518                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    4921                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    5604                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index d5d5bafb9..5bc8e2e71 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,158 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.557115                       # Number of seconds simulated
-sim_ticks                                51557114994500                       # Number of ticks simulated
-final_tick                               51557114994500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.320621                       # Number of seconds simulated
+sim_ticks                                51320620981500                       # Number of ticks simulated
+final_tick                               51320620981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111994                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131638                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5181426993                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 668412                       # Number of bytes of host memory used
-host_seconds                                  9950.37                       # Real time elapsed on the host
-sim_insts                                  1114380469                       # Number of instructions simulated
-sim_ops                                    1309844804                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 107709                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6449160479                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 667684                       # Number of bytes of host memory used
+host_seconds                                  7957.72                       # Real time elapsed on the host
+sim_insts                                   857117694                       # Number of instructions simulated
+sim_ops                                    1007133124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide        437568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker      1002304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker      1237760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           6145632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         128560840                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            137384104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      6145632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6145632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    102180288                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data      102783780                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         211790564                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6837                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker        15661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker        19340                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             111978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2008776                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2162592                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1596567                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data           1608248                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              3311479                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8487                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker          19441                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          24008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               119200                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2493562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2664697                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          119200                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             119200                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1981885                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          132406                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1993591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4107882                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1981885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          140894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker         19441                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         24008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              119200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4487152                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6772580                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2162592                       # Number of read requests accepted
-system.physmem.writeReqs                      3311479                       # Number of write requests accepted
-system.physmem.readBursts                     2162592                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    3311479                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                138204608                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    201280                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 207618304                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 137384104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              211790564                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     3145                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   67428                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48470                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              140382                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              139333                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              140658                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              133921                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              130324                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              134612                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              126217                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              133097                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              129592                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              157619                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             133394                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133867                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             132326                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             132284                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             133117                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             128704                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              201659                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              203665                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              231223                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              188549                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              224931                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              188791                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              176287                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              226882                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              203233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              233524                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             253232                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             198347                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             181957                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             175879                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             180282                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             175595                       # Per bank write bursts
+system.physmem.bytes_read::cpu.dtb.walker       227264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       206272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5756576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          43073416                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        400256                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49663784                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5756576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5756576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69780544                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          69801124                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3551                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             673035                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6254                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                791962                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1090321                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1092894                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4019                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               112169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               839300                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  967716                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          112169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             112169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1359698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1360099                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1359698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              112169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              839701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2327815                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        791962                       # Number of read requests accepted
+system.physmem.writeReqs                      1696531                       # Number of write requests accepted
+system.physmem.readBursts                      791962                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1696531                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 50649920                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     35648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 108090368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  49663784                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              108433892                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      557                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7601                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          35291                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               50546                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               51810                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               46789                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               46242                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               46096                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               52242                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               46925                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               49452                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               44750                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               73148                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              48402                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              51457                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              45806                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              48601                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              42635                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46504                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              106325                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              106592                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              106293                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              105191                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              106687                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              109171                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              103226                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              105745                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              103090                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              109771                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             107182                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             108709                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102154                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             106063                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             100653                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102060                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         190                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51557113761500                       # Total gap between requests
+system.physmem.numWrRetry                          63                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51320619748500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2141307                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  770677                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                3308906                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1296550                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    764534                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     68768                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     25837                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       916                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       532                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1693958                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    524690                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    218670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     33629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11094                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       783                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       426                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      143                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      115                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -178,357 +159,191 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    55343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    88539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   132669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   172060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   179259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   199827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   201826                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   215089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   217686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   234764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   216813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   209096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   190795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   202440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   157954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   153989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   157951                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   145311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     9323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     7805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     6801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     6277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     6099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     5695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     5430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     5062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     4998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     4548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     4335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     4121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     4055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     3461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     3051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     2987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     1591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     1247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      474                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1034839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      334.179783                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.532509                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     356.014667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         392208     37.90%     37.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       234584     22.67%     60.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        87901      8.49%     69.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        49413      4.77%     73.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        38348      3.71%     77.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        26689      2.58%     80.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        21988      2.12%     82.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        25501      2.46%     84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       158207     15.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1034839                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        135592                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.925969                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      128.724301                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         135587    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-43007            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          135592                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        135592                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.924981                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.930688                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.164557                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23          101303     74.71%     74.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            7599      5.60%     80.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39           12845      9.47%     89.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            3908      2.88%     92.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            2324      1.71%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             925      0.68%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71            2932      2.16%     97.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79            1250      0.92%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             889      0.66%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             249      0.18%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            327      0.24%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           193      0.14%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           473      0.35%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            16      0.01%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            22      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            28      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            17      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            31      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            89      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            56      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            42      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             7      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            15      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            15      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::15                    35109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    66510                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    80685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    95220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    95674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   107871                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   105650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   115186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   109604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   123316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   110089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    98131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    89808                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    90193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    76388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    75197                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    74826                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    71320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     5232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     4640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     4117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     3862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     3608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     3366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     3244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     3200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     3037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     2623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     2429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     2386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     2289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     2041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      990                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       519847                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.358892                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.693203                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.458813                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         210597     40.51%     40.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       125304     24.10%     64.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44434      8.55%     73.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23828      4.58%     77.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        16026      3.08%     80.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10297      1.98%     82.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8038      1.55%     84.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7736      1.49%     85.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        73587     14.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         519847                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         65806                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.026092                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       69.420005                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           65801     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           65806                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         65806                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.665015                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       22.295407                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       18.784846                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           44130     67.06%     67.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            6726     10.22%     77.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            8110     12.32%     89.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47            2086      3.17%     92.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55            1158      1.76%     94.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             536      0.81%     95.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             588      0.89%     96.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             530      0.81%     97.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             479      0.73%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             220      0.33%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            383      0.58%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111           149      0.23%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119           276      0.42%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            79      0.12%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           128      0.19%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            41      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            35      0.05%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            20      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            44      0.07%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            20      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            23      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            10      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215            10      0.02%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             6      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             5      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             5      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          135592                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    43990891280                       # Total ticks spent queuing
-system.physmem.totMemAccLat               84480522530                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10797235000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20371.37                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           65806                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15790981009                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30629824759                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3957025000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19953.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39121.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.68                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.03                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.66                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.11                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  38703.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.29                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1747291                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   2621349                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9418422.55                       # Average gap between requests
-system.physmem.pageHitRate                      80.85                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49290195125250                       # Time in different power states
-system.physmem.memoryStateTime::REF      1721605340000                       # Time in different power states
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     603831                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1356638                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20623172.24                       # Average gap between requests
+system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49368372569000                       # Time in different power states
+system.physmem.memoryStateTime::REF      1713708100000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      545313634750                       # Time in different power states
+system.physmem.memoryStateTime::ACT      238539960500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3951453240                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3871929600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2156050875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                2112660000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               8412588600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               8431020000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0             10640075760                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1             10381277520                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3367460045040                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3367460045040                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1383947967870                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1368871606665                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29720278968750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29733503847000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34496847150135                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34494632385825                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.099654                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.056696                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              657217                       # Transaction distribution
-system.membus.trans_dist::ReadResp             657217                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33865                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33865                       # Transaction distribution
-system.membus.trans_dist::Writeback           1596567                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1712339                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1712339                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            48473                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           48476                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1541174                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1541174                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      9221519                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      9351669                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229018                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       229018                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                9580687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    341910604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    342081160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7264064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               349345224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2022                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5500895                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5500895    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             5500895                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109641999                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5450500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         32462148974                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        21571101815                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186532342                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.physmem.actEnergy::0                1984348800                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                1945694520                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1082730000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1061638875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               3042748800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               3130163400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              5503010400                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              5441139360                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3352013043600                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3352013043600                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1228384903950                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1226638074825                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29714838054000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29716370360250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34306848839550                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34306600114830                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.480867                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.476020                       # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136716                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           17                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354224                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492654                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981079506                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179002658                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               291488483                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         200150149                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          13608043                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            209143322                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               138326751                       # Number of BTB hits
+system.cpu.branchPred.lookups               226428976                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         151471445                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12246087                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159886473                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104578062                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.139693                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                37688944                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             403819                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.407698                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31061917                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             345275                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -552,25 +367,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    220000246                       # DTB read hits
-system.cpu.dtb.read_misses                    1007031                       # DTB read misses
-system.cpu.dtb.write_hits                   193886106                       # DTB write hits
-system.cpu.dtb.write_misses                    416122                       # DTB write misses
-system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    171196432                       # DTB read hits
+system.cpu.dtb.read_misses                     671544                       # DTB read misses
+system.cpu.dtb.write_hits                   149025904                       # DTB write hits
+system.cpu.dtb.write_misses                    258759                       # DTB write misses
+system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               63968                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1209                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    89690                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       112                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15179                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               40008                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1029                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72979                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       104                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10362                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     87251                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                221007277                       # DTB read accesses
-system.cpu.dtb.write_accesses               194302228                       # DTB write accesses
+system.cpu.dtb.perms_faults                     68614                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171867976                       # DTB read accesses
+system.cpu.dtb.write_accesses               149284663                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         413886352                       # DTB hits
-system.cpu.dtb.misses                         1423153                       # DTB misses
-system.cpu.dtb.accesses                     415309505                       # DTB accesses
+system.cpu.dtb.hits                         320222336                       # DTB hits
+system.cpu.dtb.misses                          930303                       # DTB misses
+system.cpu.dtb.accesses                     321152639                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -592,635 +407,803 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    465588468                       # ITB inst hits
-system.cpu.itb.inst_misses                     176797                       # ITB inst misses
+system.cpu.itb.inst_hits                    360051885                       # ITB inst hits
+system.cpu.itb.inst_misses                     161655                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               63968                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1209                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    63536                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               40008                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1029                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53701                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    462381                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372863                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                465765265                       # ITB inst accesses
-system.cpu.itb.hits                         465588468                       # DTB hits
-system.cpu.itb.misses                          176797                       # DTB misses
-system.cpu.itb.accesses                     465765265                       # DTB accesses
-system.cpu.numCycles                       2146849645                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                360213540                       # ITB inst accesses
+system.cpu.itb.hits                         360051885                       # DTB hits
+system.cpu.itb.misses                          161655                       # DTB misses
+system.cpu.itb.accesses                     360213540                       # DTB accesses
+system.cpu.numCycles                       1576874693                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          791511347                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1301628389                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   291488483                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          176015695                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1268750537                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29307286                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    4254748                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27926                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles      12217982                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1219824                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          381                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 465107423                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6746831                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   53918                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         2092636388                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.729302                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.142136                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          648679854                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1010290403                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   226428976                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135639979                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     852655064                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26160452                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3389644                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                26807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9240220                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1021673                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 359662567                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6136086                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47510                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1528093850                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.774691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.161324                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1367675983     65.36%     65.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                280886167     13.42%     78.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 86945610      4.15%     82.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                357128628     17.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                965958627     63.21%     63.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215893777     14.13%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70817340      4.63%     81.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                275424106     18.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           2092636388                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.135775                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.606297                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                614820490                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             852644163                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 531180111                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              83391963                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10599661                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             41490545                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               4112846                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1415541998                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              32718079                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               10599661                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                678805488                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                83662136                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      556428904                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 549849830                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             213290369                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1391734034                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               7977079                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               7435136                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 893230                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1023922                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents              127479585                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            25199                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1342075875                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2217645602                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1652184740                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1639045                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1263873564                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 78202308                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           44203192                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       39719264                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 172796539                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            223511224                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           198396121                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12647992                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11061331                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1338396177                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            44508712                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1370133902                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4153047                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        65240654                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41320787                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         373617                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    2092636388                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.654741                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.915536                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1528093850                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.143594                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.640692                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                527180052                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             504302107                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 436284853                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              51059674                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9267164                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33905862                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3872221                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1095429909                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29099398                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9267164                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                572442291                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46180186                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363186865                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 441948285                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              95069059                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1075584704                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6788495                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               4945824                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 318864                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 589123                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               42956715                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            21763                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1023437611                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1659121727                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1272319582                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1685396                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             957674620                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65762988                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27435128                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23745394                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 104747763                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            175168030                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           152601618                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9963388                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9061948                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1040022976                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27737741                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1056135120                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3300763                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53598061                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33623556                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         314928                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1528093850                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.691145                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.927830                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0          1237717942     59.15%     59.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           455529583     21.77%     80.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           292996726     14.00%     94.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96986296      4.63%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9377226      0.45%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               28615      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           873977548     57.19%     57.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           338098484     22.13%     79.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           236626258     15.49%     94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72801252      4.76%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6571176      0.43%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19132      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      2092636388                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1528093850                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                74528454     34.28%     34.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  90672      0.04%     34.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26772      0.01%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              287      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               58830485     27.06%     61.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              83911289     38.60%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58371154     35.14%     35.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100885      0.06%     35.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26756      0.02%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              767      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44544414     26.81%     62.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63075062     37.97%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             945793660     69.03%     69.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2946266      0.22%     69.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                129775      0.01%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         114397      0.01%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            224851656     16.41%     85.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           196298100     14.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                 2      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             727332382     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2546997      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                123061      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         120668      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            175096796     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150915164     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1370133902                       # Type of FU issued
-system.cpu.iq.rate                           0.638207                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   217387959                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.158662                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5052021388                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1447405501                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1347303683                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2423809                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             923681                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       885699                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1585997449                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1524411                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5766333                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1056135120                       # Type of FU issued
+system.cpu.iq.rate                           0.669765                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   166119038                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157290                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3807304115                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1120557954                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1038099529                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2479775                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             941816                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       907592                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1220693938                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1560218                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4348848                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     16996131                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        24128                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       185382                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8259714                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13855252                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14404                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       142361                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6337064                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      3623609                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       3385962                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2552747                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1859122                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10599661                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11961718                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7304667                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1383179145                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9267164                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6379535                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3965873                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1067985048                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             223511224                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            198396121                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           39177517                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 185228                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6936317                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         185382                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4274350                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5730421                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10004771                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1356817685                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             220004444                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          11924579                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             175168030                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            152601618                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23314125                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  62024                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3832996                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         142361                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3691152                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5135953                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8827105                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1044930592                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             171186057                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10287379                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        274256                       # number of nop insts executed
-system.cpu.iew.exec_refs                    413901554                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                257473473                       # Number of branches executed
-system.cpu.iew.exec_stores                  193897110                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.632004                       # Inst execution rate
-system.cpu.iew.wb_sent                     1349182874                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1348189382                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 579023420                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 949767765                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        224331                       # number of nop insts executed
+system.cpu.iew.exec_refs                    320208959                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                198322451                       # Number of branches executed
+system.cpu.iew.exec_stores                  149022902                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.662659                       # Inst execution rate
+system.cpu.iew.wb_sent                     1039793819                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1039007121                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 442154878                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 715627882                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.627985                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.609647                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.658903                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.617856                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        62443917                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        44135095                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9554061                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   2078483160                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.630193                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.269789                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51471265                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27422813                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8433025                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1516084212                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.664299                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.291990                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1396354428     67.18%     67.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    397736022     19.14%     86.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    152396085      7.33%     93.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     44287772      2.13%     95.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     35996912      1.73%     97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18656723      0.90%     98.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10905184      0.52%     98.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5449343      0.26%     99.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     16700691      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    998537580     65.86%     65.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    291350566     19.22%     85.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121957393      8.04%     93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36696853      2.42%     95.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28610485      1.89%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14255849      0.94%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8557612      0.56%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4232636      0.28%     99.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11885238      0.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   2078483160                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1114380469                       # Number of instructions committed
-system.cpu.commit.committedOps             1309844804                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1516084212                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            857117694                       # Number of instructions committed
+system.cpu.commit.committedOps             1007133124                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      396651499                       # Number of memory references committed
-system.cpu.commit.loads                     206515092                       # Number of loads committed
-system.cpu.commit.membars                     9189565                       # Number of memory barriers committed
-system.cpu.commit.branches                  249089949                       # Number of branches committed
-system.cpu.commit.fp_insts                     873640                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1196978104                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             31078874                       # Number of function calls committed.
+system.cpu.commit.refs                      307577331                       # Number of memory references committed
+system.cpu.commit.loads                     161312777                       # Number of loads committed
+system.cpu.commit.membars                     7014752                       # Number of memory barriers committed
+system.cpu.commit.branches                  191334741                       # Number of branches committed
+system.cpu.commit.fp_insts                     896026                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 925144388                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25493443                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        910428363     69.51%     69.51% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2554988      0.20%     69.70% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           104143      0.01%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.71% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       105769      0.01%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.72% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       206515092     15.77%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      190136407     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        697181314     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2164633      0.21%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98281      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       161312777     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      146264554     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1309844804                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              16700691                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total        1007133124                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11885238                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3424556806                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2758622493                       # The number of ROB writes
-system.cpu.timesIdled                         9031521                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        54213257                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 100967380384                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                  1114380469                       # Number of Instructions Simulated
-system.cpu.committedOps                    1309844804                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.926496                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.926496                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.519077                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.519077                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1611998606                       # number of integer regfile reads
-system.cpu.int_regfile_writes               948639021                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1420015                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   765124                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 315259155                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                316098925                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              6952427793                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               45059384                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq       28539920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      28531649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33865                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33865                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      9369509                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1712344                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1605675                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        61529                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        61535                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      3074731                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      3074731                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     33703094                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     37825776                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       810571                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3115869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          75455310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1077469744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1502191576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2724416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10868120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2593253856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      644632                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     42703026                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.002705                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.051942                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           42587504     99.73%     99.73% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115522      0.27%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       42703026                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32333793873                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       871500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   25296093441                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   19876823538                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     472614279                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1760067316                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements          16829629                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.959617                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           447510611                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          16830141                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             26.589831                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       12236526000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.959617                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
+system.cpu.rob.rob_reads                   2555181565                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2129123637                       # The number of ROB writes
+system.cpu.timesIdled                         8137810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        48780843                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101064367400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   857117694                       # Number of Instructions Simulated
+system.cpu.committedOps                    1007133124                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.839741                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.839741                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.543555                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.543555                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237020079                       # number of integer regfile reads
+system.cpu.int_regfile_writes               738429626                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1457787                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 228125574                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                228731881                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              5247037954                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27486572                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9822538                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.985265                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           286045243                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9823050                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.119799                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.985265                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1249214859                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1249214859                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    148712432                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       148712432                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    129479125                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      129479125                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       381594                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        381594                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324870                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       324870                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352883                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3352883                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3750315                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3750315                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     278191557                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        278191557                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    278573151                       # number of overall hits
+system.cpu.dcache.overall_hits::total       278573151                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9502058                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9502058                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11465174                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11465174                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1197022                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1197022                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233022                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1233022                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20967232                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20967232                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22164254                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22164254                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 140935225401                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 322991667568                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38675981880                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38675981880                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 463926892969                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 463926892969                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 463926892969                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 463926892969                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    158214490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    158214490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    140944299                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    140944299                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578616                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1578616                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3802331                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3802331                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3750320                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3750320                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    299158789                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    299158789                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    300737405                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    300737405                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060058                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060058                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081345                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081345                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758273                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.758273                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791468                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791468                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070087                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070087                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073700                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073700                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22126.282237                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20931.310973                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     21466802                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1401851                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.313184                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      7593763                       # number of writebacks
+system.cpu.dcache.writebacks::total           7593763                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4321399                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4321399                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9425025                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9425025                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7055                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7055                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219414                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219414                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13746424                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13746424                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13746424                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13746424                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5180659                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5180659                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2040149                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2040149                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190231                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1190231                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1225967                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1225967                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7220808                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7220808                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8411039                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8411039                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70208074682                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  70208074682                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53752252884                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53752252884                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18853760746                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18853760746                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2809792248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2809792248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 123960327566                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 142814088312                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729213249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729213249                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587099983                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587099983                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316313232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316313232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032745                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032745                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753971                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753971                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024137                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024137                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027968                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027968                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          15082585                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.954216                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           343840613                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15083097                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.796420                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       14175734000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.954216                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          291                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           92                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         481916487                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        481916487                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    447510611                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       447510611                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     447510611                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        447510611                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    447510611                       # number of overall hits
-system.cpu.icache.overall_hits::total       447510611                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     17575514                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      17575514                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     17575514                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       17575514                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     17575514                       # number of overall misses
-system.cpu.icache.overall_misses::total      17575514                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 231527181766                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 231527181766                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 231527181766                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 231527181766                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 231527181766                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465086125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465086125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465086125                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465086125                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465086125                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465086125                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.037790                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.037790                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.037790                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.037790                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.037790                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.037790                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13173.280836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13173.280836                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        11084                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         374724467                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        374724467                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    343840613                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       343840613                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     343840613                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        343840613                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    343840613                       # number of overall hits
+system.cpu.icache.overall_hits::total       343840613                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15800655                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15800655                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15800655                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15800655                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15800655                       # number of overall misses
+system.cpu.icache.overall_misses::total      15800655                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208208668907                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208208668907                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208208668907                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208208668907                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208208668907                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    359641268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    359641268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    359641268                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    359641268                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    359641268                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    359641268                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043934                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043934                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043934                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043934                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043934                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043934                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13177.217584                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13177.217584                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        10839                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               920                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               972                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.047826                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    11.151235                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       745151                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       745151                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       745151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       745151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       745151                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       745151                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16830363                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     16830363                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     16830363                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     16830363                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     16830363                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     16830363                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 191394786019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 191394786019                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717456                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       717456                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       717456                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       717456                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       717456                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       717456                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15083199                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     15083199                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     15083199                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     15083199                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     15083199                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     15083199                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 171815580989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 171815580989                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.036188                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036188                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.036188                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.041940                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.041940                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1866229                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64521.528187                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           35312731                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1928499                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.310993                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     13813873928000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   307.320059                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.834309                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7078.453286                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.523738                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004689                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006864                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.108009                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.341220                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          496                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61774                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2102                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5030                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.007568                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.942596                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        341864435                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       341864435                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1342854                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       321211                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     16739434                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      8950656                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       27354155                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      9369509                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      9369509                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        13684                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        13684                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.replacements          1167362                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65297.852107                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           29065274                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1230222                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.626040                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       2430272000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   320.853018                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   490.286692                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7518.567341                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.569512                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004896                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007481                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.299753                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996366                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          285                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62575                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          285                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          565                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2655                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5044                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54243                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004349                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954819                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        273181992                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       273181992                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       797530                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297299                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst     14998467                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      6339712                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total       22433008                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      7593763                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      7593763                       # number of Writeback hits
+system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       728839                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.WriteInvalidateReq_hits::total       728839                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9472                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9472                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1532929                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1532929                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker      1342854                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       321211                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     16739434                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     10483585                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        28887084                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker      1342854                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       321211                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     16739434                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     10483585                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       28887084                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        15661                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker        19341                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        90708                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       467610                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       593320                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        47842                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        47842                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data      1541802                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total      1541802                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker        15661                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker        19341                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        90708                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2009412                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2135122                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker        15661                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker        19341                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        90708                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2009412                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2135122                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker   1242745748                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker   1521537709                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   6968907733                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  38087084418                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  47820275608                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    470429308                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    470429308                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        46998                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        46998                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128470228063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 128470228063                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker   1242745748                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker   1521537709                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   6968907733                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 166557312481                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 176290503671                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker   1242745748                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker   1521537709                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   6968907733                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 166557312481                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 176290503671                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1358515                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       340552                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst     16830142                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      9418266                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     27947475                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      9369509                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      9369509                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        61526                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        61526                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      3074731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      3074731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1358515                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       340552                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     16830142                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     12492997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     31022206                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1358515                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       340552                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     16830142                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     12492997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     31022206                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.056793                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005390                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.049649                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021230                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.777590                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.777590                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.501443                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.501443                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.056793                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005390                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.160843                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068826                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.011528                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.056793                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005390                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.160843                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068826                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79352.898793                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78669.029988                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76827.928441                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81450.534458                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80597.781312                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  9832.977467                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  9832.977467                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        15666                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        15666                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83324.725265                       # average ReadExReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1229,113 +1212,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
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+system.cpu.l2cache.demand_mshr_misses::cpu.data       674300                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       765717                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3551                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3223                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        84643                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       674300                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       765717                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    220243499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5475082762                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18259324004                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24194010014                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19601424690                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345545498                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345545498                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29577738885                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29577738885                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    220243499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5475082762                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47837062889                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  53771748899                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    220243499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5475082762                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47837062889                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  53771748899                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289773250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393755500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176184000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176184000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289733251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393715501                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176071500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176071500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465957250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569939500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.049647                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021229                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.777590                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.777590                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.501443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.501443                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068825                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011528                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.056790                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005390                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.160841                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068825                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69004.344071                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68136.808705                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.580745                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.580745                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71012.621808                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66907.205670                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465804751                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569787001                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.039032                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208413                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208413                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030898                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030898                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1345,336 +1329,380 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements          13756884                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.985330                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           363427258                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          13757396                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             26.416864                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.985330                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          382                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1609448196                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1609448196                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    188132338                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       188132338                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    164232223                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      164232223                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       465761                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        465761                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data      1605675                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total      1605675                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4847947                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4847947                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      5335203                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      5335203                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     352364561                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        352364561                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    352830322                       # number of overall hits
-system.cpu.dcache.overall_hits::total       352830322                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12712279                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12712279                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     18968725                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     18968725                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      2072118                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      2072118                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       550419                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       550419                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     31681004                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       31681004                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     33753122                       # number of overall misses
-system.cpu.dcache.overall_misses::total      33753122                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 203403538452                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1021678237791                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8626183252                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   8626183252                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       117003                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       117003                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1225081776243                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1225081776243                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    200844617                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    200844617                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    183200948                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    183200948                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2537879                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2537879                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1605675                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5398366                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      5398366                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      5335209                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      5335209                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    384045565                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    384045565                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    386583444                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    386583444                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063294                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.063294                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.103541                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.103541                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.816476                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.816476                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.101960                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.101960                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.082493                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.082493                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.087311                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087311                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38669.285110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36295.361841                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     38319499                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           2284719                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    16.772084                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                 1605675                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      9369509                       # number of writebacks
-system.cpu.dcache.writebacks::total           9369509                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5628309                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5628309                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15829986                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total     15829986                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265840                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       265840                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     21458295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     21458295                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     21458295                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     21458295                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7083970                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7083970                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3120649                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      3120649                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2065320                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      2065320                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       284579                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       284579                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     10204619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     10204619                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     12269939                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     12269939                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  31611668497                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  31611668497                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  59007365277                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3751055249                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3751055249                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       104997                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       104997                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 250741484767                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 282353153264                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729434750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729434750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587276983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587276983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316711733                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316711733                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035271                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035271                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.017034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.017034                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.813798                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.813798                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.052716                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.052716                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026571                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026571                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031739                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031739                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements               115458                       # number of replacements
-system.iocache.tags.tagsinuse               10.450727                       # Cycle average of tags in use
+system.cpu.toL2Bus.trans_dist::ReadReq       23341232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23333163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      7593763                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332631                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1225967                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43982                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1999866                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1999866                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30208899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27463876                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       731462                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1967033                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          60371270                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965659760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1114918084                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2404176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6408648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2089390668                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      611685                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     34508223                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.003348                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.057762                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           34392703     99.67%     99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115520      0.33%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       34508223                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    26206492236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1177500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy   22671590732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   13674088224                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy     431886005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy    1166711358                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.iobus.trans_dist::ReadReq                40382                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40382                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492678                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042360658                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           179004169                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115462                       # number of replacements
+system.iocache.tags.tagsinuse               10.424613                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13090278324000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.528058                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.922669                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.220504                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.432667                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653170                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13092189065000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544618                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879995                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039786                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039786                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039677                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           17                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           17                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5547000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1929395843                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1934942843                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
+system.iocache.overall_misses::total             8856                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1927411613                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1932938613                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5886000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1929395843                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1935281843                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5886000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1929395843                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1935281843                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1927411613                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1933277613                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1927411613                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1933277613                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106681                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106681                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000159                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000159                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 218637.609379                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 218337.130125                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 218601.812154                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       147150                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 218926.114036                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 218601.812154                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         53350                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        226675                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27646                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.717668                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.199197                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3623000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1470987863                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1474610863                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1468863623                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1472466623                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6546677301                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3806000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1470987863                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1474793863                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3806000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1470987863                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1474793863                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1468863623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1472649623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1468863623                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1472649623                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        95150                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166586.904213                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              412825                       # Transaction distribution
+system.membus.trans_dist::ReadResp             412825                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
+system.membus.trans_dist::Writeback           1090321                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       603637                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       603637                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35296                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35298                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            416163                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           416163                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3625442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3755550                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4090619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    144046540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144217012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14051136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14051136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               158268148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3264                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2503253                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2503253    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2503253                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109702500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5437999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         16337638979                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         7836649146                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186565831                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    17164                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16179                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index dc447388d..a91165258 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,185 +1,176 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.274675                       # Number of seconds simulated
-sim_ticks                                51274674635500                       # Number of ticks simulated
-final_tick                               51274674635500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.234988                       # Number of seconds simulated
+sim_ticks                                51234988037500                       # Number of ticks simulated
+final_tick                               51234988037500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 308954                       # Simulator instruction rate (inst/s)
-host_op_rate                                   363040                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18009090527                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 661116                       # Number of bytes of host memory used
-host_seconds                                  2847.16                       # Real time elapsed on the host
-sim_insts                                   879639951                       # Number of instructions simulated
-sim_ops                                    1033631621                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 253332                       # Simulator instruction rate (inst/s)
+host_op_rate                                   297695                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            14683650995                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 666424                       # Number of bytes of host memory used
+host_seconds                                  3489.25                       # Real time elapsed on the host
+sim_insts                                   883939374                       # Number of instructions simulated
+sim_ops                                    1038732312                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        391104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       245504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       412480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2683060                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         32648008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        82560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       137216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           615744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          8957184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker       211392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker       332480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          2079744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data         22931008                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             71727484                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2683060                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       615744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      2079744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5378548                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     40940416                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      59033572                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      12553152                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data      28525952                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         147879588                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6111                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         3836                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         6445                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             82330                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            510138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1290                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2144                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9621                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            139956                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker         3303                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker         5195                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             32496                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            358297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1161162                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          639694                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           924651                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           196143                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data           445718                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2312870                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             7628                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          4788                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          8045                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               52327                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              636728                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2676                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               12009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              174690                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          4123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker          6484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               40561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              447219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1398887                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          52327                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          12009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          40561                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             104897                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            798453                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          133136                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            1151320                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             244822                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data             556336                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2884067                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            798453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          140763                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4788                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         8045                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              52327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1788048                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2676                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              12009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             419512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         4123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker         6484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              40561                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1003555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4282954                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        556099                       # Number of read requests accepted
-system.physmem.writeReqs                       996967                       # Number of write requests accepted
-system.physmem.readBursts                      556099                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     996967                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 35500160                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     90176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  61170112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  35590336                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               63805888                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1409                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   41184                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          18778                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               32891                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               34922                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               33947                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               34663                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               34185                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               37826                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               34767                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               37084                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               34802                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               37662                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              34607                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              34013                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              33947                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              34396                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              33124                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              31854                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               51538                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               50883                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               55756                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               53410                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               72819                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               60009                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               50793                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               81282                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               66815                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               79578                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              79171                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              57649                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              53518                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              50714                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              46719                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              45129                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker       127040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       124736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3010420                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         25072712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        36992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        30656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           716608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          7359168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        93568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        90944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          2126784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data         17729152                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        417856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             56936636                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3010420                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       716608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      2126784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5853812                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     77081408                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          77101988                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1985                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1949                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             87445                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            391774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          578                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          479                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             11197                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            114987                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker         1462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker         1421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             33231                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            277018                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6529                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                930055                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1204397                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1206970                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2435                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               58757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              489367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           598                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               13987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              143636                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker          1826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker          1775                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               41510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              346036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1111284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          58757                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          13987                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          41510                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             114254                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1504468                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1504870                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1504468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              58757                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             489769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              13987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             143636                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker         1826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker         1775                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              41510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             346036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2616154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        440433                       # Number of read requests accepted
+system.physmem.writeReqs                       603232                       # Number of write requests accepted
+system.physmem.readBursts                      440433                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     603232                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28170752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     16960                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  38511488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28187712                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               38606848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      265                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1490                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          18504                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25157                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28496                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28335                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               27633                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27808                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               30320                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               26148                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               26657                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               26790                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29797                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              28841                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              30668                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26625                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26518                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25131                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25244                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               36236                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               36759                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               37480                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               39199                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               39135                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               41156                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               37007                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               36943                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               37618                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               39787                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              38447                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              38818                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              34864                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              36482                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              35714                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              36097                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          45                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51273477930500                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51233791781500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  556099                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  440433                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 996967                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    389698                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    112133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     36470                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     14160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       527                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       309                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       212                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       78                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       79                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 603232                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    309302                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     89084                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12395                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -189,927 +180,227 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       479                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    37928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    42662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    45878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    50737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    55571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    55063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    62119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    67007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    62568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    56729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    57939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    47309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    45594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    44878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    43071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      961                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      542                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      114                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       313965                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      307.901429                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     171.041097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.087880                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         132720     42.27%     42.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        70601     22.49%     64.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        25843      8.23%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        12745      4.06%     77.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         9334      2.97%     80.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6247      1.99%     82.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5388      1.72%     83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6641      2.12%     85.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        44446     14.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         313965                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         40272                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        13.773590                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      142.393884                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          40271    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           40272                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         40272                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.733189                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       21.769670                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.088668                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 6      0.01%      0.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.00%      0.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                4      0.01%      0.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              68      0.17%      0.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           21743     53.99%     54.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            7529     18.70%     72.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             844      2.10%     74.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            2202      5.47%     80.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            3572      8.87%     89.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             961      2.39%     91.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             568      1.41%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             548      1.36%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             664      1.65%     96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             107      0.27%     96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              86      0.21%     96.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63             131      0.33%     96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             645      1.60%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71             191      0.47%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75             148      0.37%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             110      0.27%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              71      0.18%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              17      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               8      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               9      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             4      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             5      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             6      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           40272                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10784853014                       # Total ticks spent queuing
-system.physmem.totMemAccLat               21185290514                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2773450000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19443.03                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::2                       478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       473                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      462                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      455                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    12525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    16592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    24225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    27652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    32938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    35820                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    36604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    38132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    38614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    39680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    39064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    37806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    36835                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    37288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    32953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    32715                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    32497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    31145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      605                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      516                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      259                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       270943                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.111691                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     146.841271                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     289.814348                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         123351     45.53%     45.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        67798     25.02%     70.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        24089      8.89%     79.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        12477      4.61%     84.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8623      3.18%     87.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         5501      2.03%     89.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4269      1.58%     90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3914      1.44%     92.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20921      7.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         270943                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         29531                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.905286                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       10.293446                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-15            12117     41.03%     41.03% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16-31           16080     54.45%     95.48% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-47            1080      3.66%     99.14% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::48-63             183      0.62%     99.76% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-79              43      0.15%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::80-95              13      0.04%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-111              6      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::112-127             3      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-143             3      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::176-191             2      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::320-335             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           29531                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         29531                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.376621                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.754514                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.014003                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 5      0.02%      0.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                10      0.03%      0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               10      0.03%      0.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              38      0.13%      0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           24052     81.45%     81.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2161      7.32%     88.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             399      1.35%     90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             574      1.94%     92.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             563      1.91%     94.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             287      0.97%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             195      0.66%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             150      0.51%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             203      0.69%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              86      0.29%     97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              51      0.17%     97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              59      0.20%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             110      0.37%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              84      0.28%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              56      0.19%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              59      0.20%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              85      0.29%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              34      0.12%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              26      0.09%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              18      0.06%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              70      0.24%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            10      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             9      0.03%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             9      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            14      0.05%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             8      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             6      0.02%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             7      0.02%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            32      0.11%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             9      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             8      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             3      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             2      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           29531                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10316676500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               18569826500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2200840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       23438.04                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38193.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.69                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.19                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.69                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.24                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  42188.04                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.75                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.55                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.75                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.80                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     423817                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    772691                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.41                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                     33014358.65                       # Average gap between requests
-system.physmem.pageHitRate                      79.21                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49344562776500                       # Time in different power states
-system.physmem.memoryStateTime::REF      1712173840000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     332271                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    438696                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.49                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.90                       # Row buffer hit rate for writes
+system.physmem.avgGap                     49090265.35                       # Average gap between requests
+system.physmem.pageHitRate                      74.00                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49384314860250                       # Time in different power states
+system.physmem.memoryStateTime::REF      1710848620000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      217931188500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      139817808500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                1214869320                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                1158706080                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 662875125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 632230500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               2186223000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               2140359000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              3087655200                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              3105818640                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3349012031040                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3349012031040                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1215657712530                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1211135236200                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29698434260250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29702401344750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34270255626465                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34269585726210                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.366215                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.353150                       # Core power per rank (mW)
+system.physmem.actEnergy::0                1046447640                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                1001881440                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 570978375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 546661500                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1720321200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1712989200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              1969369200                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              1929918960                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3346419900720                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3346419900720                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1177540520625                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1174853241090                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29708058483750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29710415746500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34237326021510                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34236880339410                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.241213                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.232514                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              512200                       # Transaction distribution
-system.membus.trans_dist::ReadResp             512200                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33772                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33772                       # Transaction distribution
-system.membus.trans_dist::Writeback            639694                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1670603                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1670603                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36363                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36366                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            685391                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           685391                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122952                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6155552                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6285312                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229159                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       229159                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6514471                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156082                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212389664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    212559378                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7272512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7272512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               219831890                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1887                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3467502                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3467502    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3467502                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            48925999                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1640000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9861261476                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6001066379                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           87450398                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   829792                       # number of replacements
-system.l2c.tags.tagsinuse                64538.969055                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   28099922                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   891020                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    31.536803                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             13806560382000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35856.169681                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   191.429036                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   290.837170                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3857.675402                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9456.283942                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    48.759094                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    73.219747                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      709.055197                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2692.383155                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker   111.816270                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker   164.499208                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2725.095268                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     8361.745885                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.547122                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002921                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004438                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.058863                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.144291                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000744                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001117                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.010819                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.041083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001706                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.002510                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.041582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.127590                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.984787                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          502                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        60726                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          489                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2207                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4867                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53302                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.007660                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.926605                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                265686556                       # Number of tag accesses
-system.l2c.tags.data_accesses               265686556                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       200882                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       128104                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            6599762                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3104423                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        71894                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        47918                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            2040254                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             973662                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       383209                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker       140169                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst            5756088                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data            2406989                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               21853354                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         6807908                       # number of Writeback hits
-system.l2c.Writeback_hits::total              6807908                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            5076                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1634                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            4357                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               11067                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           707211                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           212100                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           483663                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1402974                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        200882                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        128104                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6599762                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3811634                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         71894                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         47918                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             2040254                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             1185762                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        383209                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker        140169                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             5756088                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             2890652                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                23256328                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       200882                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       128104                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6599762                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3811634                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        71894                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        47918                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            2040254                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            1185762                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       383209                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker       140169                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            5756088                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            2890652                       # number of overall hits
-system.l2c.overall_hits::total               23256328                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         3836                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         6445                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            39229                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           153846                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         1290                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2144                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             9621                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data            42836                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker         3311                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker         5220                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst            32496                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data           126310                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               426584                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         17268                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          5409                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data         13103                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             35780                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu2.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         356597                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          97202                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data         232172                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             685971                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3836                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         6445                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             39229                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            510443                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1290                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2144                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              9621                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            140038                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker         3311                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker         5220                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst             32496                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data            358482                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1112555                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3836                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         6445                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            39229                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           510443                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1290                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2144                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             9621                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           140038                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker         3311                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker         5220                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst            32496                       # number of overall misses
-system.l2c.overall_misses::cpu2.data           358482                       # number of overall misses
-system.l2c.overall_misses::total              1112555                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     98176250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    165694000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    710409250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data   3173067500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker    260580226                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker    407293488                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst   2545464971                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data  10430324641                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    17791010326                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     64697721                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data    151206011                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    215903732                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        23499                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu2.data        22999                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        46498                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   6960631918                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data  20491301758                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  27451933676                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker     98176250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    165694000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    710409250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  10133699418                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker    260580226                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker    407293488                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst   2545464971                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data  30921626399                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     45242944002                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker     98176250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    165694000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    710409250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  10133699418                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker    260580226                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker    407293488                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst   2545464971                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data  30921626399                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    45242944002                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       204718                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       134549                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst        6638991                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        3258269                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        73184                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        50062                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst        2049875                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data        1016498                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker       386520                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu2.inst        5788584                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data        2533299                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total           22279938                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      6807908                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          6807908                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        22344                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         7043                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data        17460                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46847                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             6                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1063808                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       309302                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       715835                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2088945                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       204718                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       134549                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         6638991                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.dtb.walker        73184                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.inst         2049875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1325800                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       386520                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.data         3249134                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            24368883                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       204718                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       134549                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        6638991                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4322077                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        73184                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.inst        2049875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1325800                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu2.itb.walker       145389                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        5788584                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        3249134                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           24368883                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.005909                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.047217                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004693                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.042141                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.005614                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.049860                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.019147                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.772825                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.767997                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.750458                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.763763                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.400000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.335208                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.314262                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.324337                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.328382                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.118101                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.105625                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu2.data       0.110332                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.045655                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.118101                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004693                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.105625                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005614                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.110332                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.045655                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73839.439767                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 74074.785227                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78331.639925                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 82577.188196                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 41705.760943                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11539.800885                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6034.201565                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        23499                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 11499.500000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15499.333333                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71609.966030                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88259.143041                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 40019.087798                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 73839.439767                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72363.925634                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 78331.639925                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 86257.124204                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 40665.804389                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 73839.439767                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72363.925634                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 78331.639925                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 86257.124204                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 40665.804389                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              639694                       # number of writebacks
-system.l2c.writebacks::total                   639694                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker            8                       # number of ReadReq MSHR hits
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-system.l2c.ReadReq_mshr_hits::cpu2.data             4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                37                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.dtb.walker            8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.itb.walker           25                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 37                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.dtb.walker            8                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total                37                       # number of overall MSHR hits
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-system.l2c.UpgradeReq_mshr_misses::cpu2.data        13103                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        18512                       # number of UpgradeReq MSHR misses
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-system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::total        329374                       # number of ReadExReq MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.data       140038                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu2.data       358478                       # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1290                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.inst         9621                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       140038                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu2.data       358478                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          552565                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    588487750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data   2634900000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst   2138403529                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data   8858602217                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15001935210                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   3923029000                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data  10580910001                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total  14503939001                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     54095409                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    131333088                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    185428497                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5718766582                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  17592121130                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  23310887712                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    139178500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    588487750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   8353666582                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst   2138403529                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data  26450723347                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  38312822922                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    139178500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    588487750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   8353666582                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst   2138403529                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data  26450723347                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  38312822922                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    884253000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1618942500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2503195500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    835101000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1639869500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2474970500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1719354000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   3258812000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4978166000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.042141                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.049858                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.010018                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767997                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.750458                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.395159                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.314262                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.324337                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.157675                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.105625                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.110330                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.022675                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.105625                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.110330                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.022675                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61511.345597                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70136.036427                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 67215.681681                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10023.131191                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.664704                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58833.836567                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75771.932576                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 70773.308494                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59652.855525                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73786.183105                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69336.318663                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59652.855525                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73786.183105                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69336.318663                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq           22792948                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          22787515                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33772                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33772                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          6807908                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1600102                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1563939                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46847                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             6                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46853                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2088945                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2088945                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29041280                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27958653                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       843900                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1753644                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              59597477                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    926729300                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1105413310                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3095064                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6286720                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2041524394                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          368391                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         33333670                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003466                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.058768                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               33218144     99.65%     99.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115526      0.35%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           33333670                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        25204206978                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1129500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       35295410102                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       21026275011                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         267100118                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         646797339                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40334                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40334                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136600                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              66161                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           65                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        70504                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48070                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230966                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230966                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353998                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48090                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156082                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492464                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             17794000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 2000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             9530000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               91000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            16563000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               71000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           339092871                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            44416000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            84714602                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              144000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1133,25 +424,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    79163453                       # DTB read hits
-system.cpu0.dtb.read_misses                     85617                       # DTB read misses
-system.cpu0.dtb.write_hits                   72660708                       # DTB write hits
-system.cpu0.dtb.write_misses                    28291                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1291                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    78485873                       # DTB read hits
+system.cpu0.dtb.read_misses                     85123                       # DTB read misses
+system.cpu0.dtb.write_hits                   72027961                       # DTB write hits
+system.cpu0.dtb.write_misses                    28205                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1285                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21000                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   52340                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              21048                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    509                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   51602                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3792                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4002                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9968                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                79249070                       # DTB read accesses
-system.cpu0.dtb.write_accesses               72688999                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9811                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                78570996                       # DTB read accesses
+system.cpu0.dtb.write_accesses               72056166                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        151824161                       # DTB hits
-system.cpu0.dtb.misses                         113908                       # DTB misses
-system.cpu0.dtb.accesses                    151938069                       # DTB accesses
+system.cpu0.dtb.hits                        150513834                       # DTB hits
+system.cpu0.dtb.misses                         113328                       # DTB misses
+system.cpu0.dtb.accesses                    150627162                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1173,524 +464,411 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   424925918                       # ITB inst hits
-system.cpu0.itb.inst_misses                     64800                       # ITB inst misses
+system.cpu0.itb.inst_hits                   421004293                       # ITB inst hits
+system.cpu0.itb.inst_misses                     63363                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1291                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1285                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21000                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   37053                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21048                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    509                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   36267                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               424990718                       # ITB inst accesses
-system.cpu0.itb.hits                        424925918                       # DTB hits
-system.cpu0.itb.misses                          64800                       # DTB misses
-system.cpu0.itb.accesses                    424990718                       # DTB accesses
-system.cpu0.numCycles                       511314689                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               421067656                       # ITB inst accesses
+system.cpu0.itb.hits                        421004293                       # DTB hits
+system.cpu0.itb.misses                          63363                       # DTB misses
+system.cpu0.itb.accesses                    421067656                       # DTB accesses
+system.cpu0.numCycles                       506516508                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  424739937                       # Number of instructions committed
-system.cpu0.committedOps                    499770936                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            458702697                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                419703                       # Number of float alu accesses
-system.cpu0.num_func_calls                   25504192                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     64716286                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   458702697                       # number of integer instructions
-system.cpu0.num_fp_insts                       419703                       # number of float instructions
-system.cpu0.num_int_register_reads          675611920                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         364415309                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              677474                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             352628                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           112049346                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          111774000                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    151917751                       # number of memory refs
-system.cpu0.num_load_insts                   79236622                       # Number of load instructions
-system.cpu0.num_store_insts                  72681129                       # Number of store instructions
-system.cpu0.num_idle_cycles              499253695.584872                       # Number of idle cycles
-system.cpu0.num_busy_cycles              12060993.415128                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023588                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976412                       # Percentage of idle cycles
-system.cpu0.Branches                         94879530                       # Number of branches fetched
+system.cpu0.committedInsts                  420811760                       # Number of instructions committed
+system.cpu0.committedOps                    495213745                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            454628715                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                411957                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25378118                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     63987651                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   454628715                       # number of integer instructions
+system.cpu0.num_fp_insts                       411957                       # number of float instructions
+system.cpu0.num_int_register_reads          670075882                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         361231436                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              665979                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             343448                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           110680974                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          110422200                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    150607491                       # number of memory refs
+system.cpu0.num_load_insts                   78559078                       # Number of load instructions
+system.cpu0.num_store_insts                  72048413                       # Number of store instructions
+system.cpu0.num_idle_cycles              494422986.191521                       # Number of idle cycles
+system.cpu0.num_busy_cycles              12093521.808479                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023876                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976124                       # Percentage of idle cycles
+system.cpu0.Branches                         93934421                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                346985072     69.39%     69.39% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1058214      0.21%     69.60% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    47254      0.01%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             51204      0.01%     69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.62% # Class of executed instruction
-system.cpu0.op_class::MemRead                79236622     15.85%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               72681129     14.53%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                343753597     69.37%     69.37% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1048568      0.21%     69.59% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47671      0.01%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             50027      0.01%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::MemRead                78559078     15.85%     85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite               72048413     14.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 500059496                       # Class of executed instruction
+system.cpu0.op_class::total                 495507356                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16293                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements         14476947                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.977197                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          610391871                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         14477459                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            42.161533                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8950087250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   497.229242                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     6.558404                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst     8.189551                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.971151                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.012809                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.015995                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        639762187                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       639762187                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    418346381                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    129402990                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     62642500                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      610391871                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    418346381                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    129402990                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     62642500                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       610391871                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    418346381                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    129402990                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     62642500                       # number of overall hits
-system.cpu0.icache.overall_hits::total      610391871                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6638991                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      2049875                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      6203870                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     14892736                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6638991                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      2049875                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      6203870                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      14892736                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6638991                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      2049875                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      6203870                       # number of overall misses
-system.cpu0.icache.overall_misses::total     14892736                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  27332922248                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  82496329525                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 109829251773                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  27332922248                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  82496329525                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 109829251773                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  27332922248                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  82496329525                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 109829251773                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    424985372                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    131452865                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     68846370                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    625284607                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    424985372                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    131452865                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     68846370                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    625284607                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    424985372                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    131452865                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     68846370                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    625284607                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015622                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015594                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.090112                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023818                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015622                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015594                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.090112                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023818                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015622                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015594                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.090112                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023818                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13333.945849                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13297.559350                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7374.686006                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13333.945849                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13297.559350                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7374.686006                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13333.945849                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13297.559350                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7374.686006                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        37721                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3310                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.396073                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst       415156                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       415156                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst       415156                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       415156                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst       415156                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       415156                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      2049875                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      5788714                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      7838589                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      2049875                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      5788714                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      7838589                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      2049875                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      5788714                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      7838589                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  23229700752                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  67401467898                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  90631168650                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  23229700752                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  67401467898                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  90631168650                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  23229700752                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  67401467898                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  90631168650                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012536                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012536                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012536                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11562.178939                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11562.178939                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11562.178939                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements         10128409                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999720                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          303013393                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10128921                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            29.915664                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   16313                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements         10203749                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          304434614                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10204261                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            29.834068                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.552561                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.756281                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.690878                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971782                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015149                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013068                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.228127                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.974365                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    10.797225                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969196                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.009716                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.021088                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          203                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          210                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1287987504                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1287987504                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     73967004                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     23189496                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     58636674                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      155793174                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68735212                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     21073027                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     49137576                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     138945815                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       193443                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        57150                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       141238                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       391831                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       922078                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       196143                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data       445718                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1563939                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1801315                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       562780                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1217494                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3581589                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1914885                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       606233                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data      1395393                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3916511                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    142702216                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     44262523                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data    107774250                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       294738989                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    142895659                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     44319673                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data    107915488                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      295130820                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2516282                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       796205                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data      4618007                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7930494                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1086152                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       320705                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data      4288284                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5695141                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       627582                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       187561                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       448945                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1264088                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       114405                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        43721                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data       223929                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       382055                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            5                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3602434                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1116910                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      8906291                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13625635                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4230016                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1304471                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      9355236                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14889723                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  12447991000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  82795568309                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  95243559309                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  10567240491                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 177246244923                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 187813485414                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    612526750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data   3159923284                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3772450034                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        26501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        90002                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       116503                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  23015231491                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 260041813232                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 283057044723                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  23015231491                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 260041813232                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 283057044723                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     76483286                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     23985701                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     63254681                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    163723668                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     69821364                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     21393732                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     53425860                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    144640956                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       821025                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       244711                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       590183                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1655919                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       922078                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       196143                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       445718                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1563939                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1915720                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       606501                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1441423                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3963644                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1914885                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       606234                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1395398                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3916517                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    146304650                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     45379433                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data    116680541                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    308364624                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    147125675                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     45624144                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data    117270724                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    310020543                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032900                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033195                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.073007                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.048438                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015556                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014991                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.080266                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.039374                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764388                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.766459                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.760688                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.763376                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059719                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.072087                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.155353                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.096390                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.tags.tag_accesses       1294524003                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1294524003                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     73268923                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     23739594                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data     59414779                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      156423296                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68111490                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     21735522                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data     49847350                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     139694362                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       193034                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58570                       # number of SoftPFReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total       391979                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       149338                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data        52269                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data       129188                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       330795                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1809029                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       564897                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1231072                       # number of LoadLockedReq hits
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+system.cpu0.dcache.overall_hits::cpu0.data    141573447                       # number of overall hits
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+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  12089122250                       # number of ReadReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9781004455                       # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 167855762892                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data   2453110503                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data  10603203705                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  13056314208                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    651998250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data   3227061036                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3879059286                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       150500                       # number of StoreCondReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::cpu1.data  21870126705                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 239849961849                       # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::cpu1.data  21870126705                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 239849961849                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 261720088554                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     75796601                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     24532622                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     64184481                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::cpu0.data     69196849                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     22070050                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     54127642                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    145394541                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       820000                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       253600                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       595759                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1669359                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       904400                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       191188                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       469061                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1564649                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1923033                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       610017                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1461076                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3994126                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1922190                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       609753                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1411608                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3943551                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    144993450                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     46602672                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data    118312123                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    309908245                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    145813450                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     46856272                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data    118907882                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    311577604                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033348                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032325                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.074312                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.049178                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015685                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015158                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.079078                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.039205                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764593                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.769046                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.764376                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765192                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.834876                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.726609                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data     0.724582                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.788582                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059283                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.073965                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.157421                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.097425                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024623                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024613                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.076331                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044187                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028751                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028592                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079775                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048028                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15634.153265                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17928.852925                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12009.788963                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32950.033492                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 41332.674077                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 32977.846451                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14009.897990                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14111.273145                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9874.101985                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        26501                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 18000.400000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19417.166667                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20606.164768                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29197.542864                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20773.860794                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17643.344690                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27796.392655                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19010.229050                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     21434212                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        26746                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          1267990                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            380                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.904086                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    70.384211                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1563939                       # number of fast writes performed
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024919                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024195                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.076493                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.044499                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029078                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028226                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079939                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048360                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.256508                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17144.719610                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11601.927327                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29238.223572                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36930.835195                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29447.454701                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17658.567244                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31197.546451                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10581.733502                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14450.315824                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14030.456149                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9968.594617                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        75250                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000.250000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        30643                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19396.044813                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26502.775786                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18978.168845                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16535.882510                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25233.079826                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17369.303275                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     16646814                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        16737                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          1171436                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            381                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.210605                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    43.929134                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      6807908                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6807908                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          948                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2610303                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2611251                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4360                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3551132                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3555492                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9967                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       136103                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       146070                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         5308                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      6161435                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      6166743                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         5308                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      6161435                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      6166743                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       795257                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2007704                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2802961                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       316345                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       729165                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1045510                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       187487                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       441899                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       629386                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        33754                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        87826                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121580                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            5                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7869277                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7869277                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         1021                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2728886                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2729907                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         3191                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3547950                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3551141                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data         2444                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         2444                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        10468                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       139963                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       150431                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         4212                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      6276836                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      6281048                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         4212                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      6276836                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      6281048                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       792007                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2040816                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2832823                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       331337                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       732342                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1063679                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       194976                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       448304                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       643280                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       138919                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data       337429                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       476348                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        34652                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        90041                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       124693                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      1111602                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      2736869                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      3848471                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1299089                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      3178768                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4477857                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10787340750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30936267343                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41723608093                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9783657259                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  28438527940                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38222185199                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2771251250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   9108575422                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  11879826672                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   6372956000                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data  16470207883                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  22843163883                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    406720000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1117052111                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1523772111                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        24499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        79998                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       104497                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  20570998009                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  59374795283                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  79945793292                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  23342249259                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  68483370705                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  91825619964                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    959248000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1745955500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2705203500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    898794000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1756075958                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2654869958                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1858042000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3502031458                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5360073458                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033155                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031740                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017120                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014787                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013648                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007228                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.766157                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.748749                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.380083                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055654                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060930                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.030674                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      1123344                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      2773158                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      3896502                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1318320                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      3221462                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4539782                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10425295500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30694668987                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41119964487                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8981852045                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  24997038072                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33978890117                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2907550500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   9282645690                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  12190196190                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2175272497                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data   9841405614                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  12016678111                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    423668250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1137848378                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1561516628                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       146500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        55999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       202499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19407147545                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  55691707059                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  75098854604                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22314698045                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  64974352749                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  87289050794                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    887936500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1414128501                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2302065001                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    802092250                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1441281461                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2243373711                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1690028750                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2855409962                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4545438712                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032284                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031796                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017219                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015013                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013530                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007316                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.768833                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.752492                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.385346                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.726609                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.719371                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.304444                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056805                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.061626                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.031219                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024496                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023456                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.012480                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028474                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027106                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.014444                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13564.597042                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15408.779055                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14885.547139                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30927.175264                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 39001.498893                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36558.411875                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14781.031485                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20612.346762                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18875.263625                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12049.534870                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12718.922768                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12533.082012                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        24499                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15999.600000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17416.166667                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18505.722380                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21694.423549                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20773.391119                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17968.167892                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21543.997771                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20506.599466                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024105                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023439                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.012573                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028135                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027092                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.014570                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13163.135553                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15040.390210                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14515.543148                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27107.905380                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34133.011724                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31944.684550                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14912.350751                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20706.140677                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18950.062477                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15658.567201                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29165.855970                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25226.679048                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12226.372215                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12637.002899                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12522.889240                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        73250                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13999.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33749.833333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17276.228426                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20082.414006                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19273.403325                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16926.617244                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20169.212845                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19227.586433                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1701,6 +879,143 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements         14506041                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.977027                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          610832898                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         14506553                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            42.107377                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9058180500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   497.195368                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.341031                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.440628                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.971085                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.008479                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.020392                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           73                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses        640265260                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       640265260                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    414440150                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    132748322                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     63644426                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      610832898                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    414440150                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    132748322                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     63644426                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       610832898                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    414440150                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    132748322                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     63644426                       # number of overall hits
+system.cpu0.icache.overall_hits::total      610832898                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6622096                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      2064308                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst      6239288                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     14925692                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6622096                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      2064308                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst      6239288                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      14925692                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6622096                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      2064308                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst      6239288                       # number of overall misses
+system.cpu0.icache.overall_misses::total     14925692                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  27633797750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  83140755110                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 110774552860                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  27633797750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst  83140755110                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 110774552860                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  27633797750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst  83140755110                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 110774552860                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    421062246                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    134812630                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     69883714                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    625758590                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    421062246                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    134812630                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     69883714                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    625758590                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    421062246                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    134812630                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     69883714                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    625758590                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015727                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015312                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.089281                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023852                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015727                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015312                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.089281                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.023852                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015727                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015312                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.089281                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023852                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.470309                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13325.359418                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7421.736484                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13386.470309                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13325.359418                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7421.736484                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13386.470309                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13325.359418                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7421.736484                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        42469                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3518                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.071916                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst       419022                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       419022                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst       419022                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       419022                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst       419022                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       419022                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      2064308                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      5820266                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      7884574                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      2064308                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      5820266                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      7884574                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      2064308                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      5820266                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      7884574                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  23501092750                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  67935136085                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  91436228835                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  23501092750                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  67935136085                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  91436228835                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  23501092750                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  67935136085                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  91436228835                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015312                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.083285                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012600                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015312                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.083285                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012600                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015312                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.083285                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012600                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.489500                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11672.170324                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.850868                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.489500                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11672.170324                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.850868                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.489500                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11672.170324                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.850868                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1724,25 +1039,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    24842678                       # DTB read hits
-system.cpu1.dtb.read_misses                     30288                       # DTB read misses
-system.cpu1.dtb.write_hits                   22204387                       # DTB write hits
-system.cpu1.dtb.write_misses                     9453                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1282                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    25401715                       # DTB read hits
+system.cpu1.dtb.read_misses                     30145                       # DTB read misses
+system.cpu1.dtb.write_hits                   22878884                       # DTB write hits
+system.cpu1.dtb.write_misses                     9290                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1276                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               6426                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   22120                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               6765                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    155                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   21663                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1240                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  1295                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2953                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                24872966                       # DTB read accesses
-system.cpu1.dtb.write_accesses               22213840                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     3011                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25431860                       # DTB read accesses
+system.cpu1.dtb.write_accesses               22888174                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         47047065                       # DTB hits
-system.cpu1.dtb.misses                          39741                       # DTB misses
-system.cpu1.dtb.accesses                     47086806                       # DTB accesses
+system.cpu1.dtb.hits                         48280599                       # DTB hits
+system.cpu1.dtb.misses                          39435                       # DTB misses
+system.cpu1.dtb.accesses                     48320034                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1764,56 +1079,56 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   131452865                       # ITB inst hits
-system.cpu1.itb.inst_misses                     23431                       # ITB inst misses
+system.cpu1.itb.inst_hits                   134812630                       # ITB inst hits
+system.cpu1.itb.inst_misses                     23831                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1282                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1276                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               6426                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   16167                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               6765                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    155                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   16095                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               131476296                       # ITB inst accesses
-system.cpu1.itb.hits                        131452865                       # DTB hits
-system.cpu1.itb.misses                          23431                       # DTB misses
-system.cpu1.itb.accesses                    131476296                       # DTB accesses
-system.cpu1.numCycles                      1282114185                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               134836461                       # ITB inst accesses
+system.cpu1.itb.hits                        134812630                       # DTB hits
+system.cpu1.itb.misses                          23831                       # DTB misses
+system.cpu1.itb.accesses                    134836461                       # DTB accesses
+system.cpu1.numCycles                      1276129163                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  131358204                       # Number of instructions committed
-system.cpu1.committedOps                    154205938                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            141499337                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                128756                       # Number of float alu accesses
-system.cpu1.num_func_calls                    7727196                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     20146536                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   141499337                       # number of integer instructions
-system.cpu1.num_fp_insts                       128756                       # number of float instructions
-system.cpu1.num_int_register_reads          205950168                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         112374883                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              204901                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             115300                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            34581843                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           34518712                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     47044288                       # number of memory refs
-system.cpu1.num_load_insts                   24842081                       # Number of load instructions
-system.cpu1.num_store_insts                  22202207                       # Number of store instructions
-system.cpu1.num_idle_cycles              1255604442.364680                       # Number of idle cycles
-system.cpu1.num_busy_cycles              26509742.635320                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.020677                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.979323                       # Percentage of idle cycles
-system.cpu1.Branches                         29364446                       # Number of branches fetched
+system.cpu1.committedInsts                  134717323                       # Number of instructions committed
+system.cpu1.committedOps                    158229449                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            145215192                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                135383                       # Number of float alu accesses
+system.cpu1.num_func_calls                    7898602                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     20639469                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   145215192                       # number of integer instructions
+system.cpu1.num_fp_insts                       135383                       # number of float instructions
+system.cpu1.num_int_register_reads          211626069                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         115298933                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              217457                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             117636                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            35416182                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           35358802                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     48278390                       # number of memory refs
+system.cpu1.num_load_insts                   25401257                       # Number of load instructions
+system.cpu1.num_store_insts                  22877133                       # Number of store instructions
+system.cpu1.num_idle_cycles              1248602360.762588                       # Number of idle cycles
+system.cpu1.num_busy_cycles              27526802.237412                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021571                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978429                       # Percentage of idle cycles
+system.cpu1.Branches                         30073331                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                106871098     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                  352774      0.23%     69.49% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    14834      0.01%     69.50% # Class of executed instruction
+system.cpu1.op_class::IntAlu                109658909     69.26%     69.26% # Class of executed instruction
+system.cpu1.op_class::IntMult                  355788      0.22%     69.49% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    13920      0.01%     69.50% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
 system.cpu1.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
@@ -1834,28 +1149,28 @@ system.cpu1.op_class::SimdSqrt                      0      0.00%     69.50% # Cl
 system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.50% # Class of executed instruction
 system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.50% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             17563      0.01%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             17708      0.01%     69.51% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::MemRead                24842081     16.10%     85.61% # Class of executed instruction
-system.cpu1.op_class::MemWrite               22202207     14.39%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                25401257     16.04%     85.55% # Class of executed instruction
+system.cpu1.op_class::MemWrite               22877133     14.45%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 154300599                       # Class of executed instruction
+system.cpu1.op_class::total                 158324756                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               95476448                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         64928073                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          4299413                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            64784895                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               46332623                       # Number of BTB hits
+system.cpu2.branchPred.lookups               96972708                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         66097998                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          4361259                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            65994487                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               47080178                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.517632                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS               12285804                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            131917                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            71.339562                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS               12396082                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            131444                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1879,25 +1194,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    77077341                       # DTB read hits
-system.cpu2.dtb.read_misses                    441139                       # DTB read misses
-system.cpu2.dtb.write_hits                   58693711                       # DTB write hits
-system.cpu2.dtb.write_misses                   191612                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1283                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    77639620                       # DTB read hits
+system.cpu2.dtb.read_misses                    447330                       # DTB read misses
+system.cpu2.dtb.write_hits                   59480935                       # DTB write hits
+system.cpu2.dtb.write_misses                   199454                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1277                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid              14423                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    383                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   37244                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       88                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  5986                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid              14382                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    391                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   38430                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       78                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  6154                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                    37589                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                77518480                       # DTB read accesses
-system.cpu2.dtb.write_accesses               58885323                       # DTB write accesses
+system.cpu2.dtb.perms_faults                    38837                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                78086950                       # DTB read accesses
+system.cpu2.dtb.write_accesses               59680389                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                        135771052                       # DTB hits
-system.cpu2.dtb.misses                         632751                       # DTB misses
-system.cpu2.dtb.accesses                    136403803                       # DTB accesses
+system.cpu2.dtb.hits                        137120555                       # DTB hits
+system.cpu2.dtb.misses                         646784                       # DTB misses
+system.cpu2.dtb.accesses                    137767339                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1919,390 +1234,459 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                    69012170                       # ITB inst hits
-system.cpu2.itb.inst_misses                     76652                       # ITB inst misses
+system.cpu2.itb.inst_hits                    70053409                       # ITB inst hits
+system.cpu2.itb.inst_misses                     78615                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1283                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1277                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid              14423                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    383                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   28880                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid              14382                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    391                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   29938                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                   143189                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                   146701                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                69088822                       # ITB inst accesses
-system.cpu2.itb.hits                         69012170                       # DTB hits
-system.cpu2.itb.misses                          76652                       # DTB misses
-system.cpu2.itb.accesses                     69088822                       # DTB accesses
-system.cpu2.numCycles                       465978411                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                70132024                       # ITB inst accesses
+system.cpu2.itb.hits                         70053409                       # DTB hits
+system.cpu2.itb.misses                          78615                       # DTB misses
+system.cpu2.itb.accesses                     70132024                       # DTB accesses
+system.cpu2.numCycles                       464363800                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles         177853142                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     424737263                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   95476448                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          58618427                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    260785808                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                9691059                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                   1879827                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                8981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             2007                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles      3759830                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       120446                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         3389                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 68846411                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes              2635973                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                  29904                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         449258797                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.104850                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.350365                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles         179489584                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     430854602                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   96972708                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          59476260                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    257591256                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                9826419                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                   1844126                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                7503                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             2868                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles      3763568                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       118840                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         3975                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 69883749                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes              2672352                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                  30337                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         447734787                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.124399                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.366335                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0               344689329     76.72%     76.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                13175573      2.93%     79.66% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                13441142      2.99%     82.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 9727641      2.17%     84.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                19687409      4.38%     89.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                 6520571      1.45%     90.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 7057131      1.57%     92.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                 6252659      1.39%     93.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                28707342      6.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0               341635028     76.30%     76.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                13406310      2.99%     79.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                13636635      3.05%     82.34% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 9872032      2.20%     84.55% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                19981367      4.46%     89.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                 6599798      1.47%     90.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 7144304      1.60%     92.08% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                 6328128      1.41%     93.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                29131185      6.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           449258797                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.204895                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.911496                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles               145040906                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles            213951941                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 77038080                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              9368936                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               3856816                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved            14196524                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred              1002861                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts             463271274                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts              3090116                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               3856816                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles               150407499                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               19371841                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles     168106415                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 80889236                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             26624521                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             452059055                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                70033                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               1786376                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents               1304038                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents              13315771                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.FullRegisterEvents            3626                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands          431846627                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            688168989                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       533483946                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups           696961                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            360553438                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                71293189                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts           9871202                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts       8455912                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 51921554                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            73490892                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores           61773042                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          9381483                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores        10099562                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 429589038                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded            9855415                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                428971223                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           602179                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined       55645947                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     38557670                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        233014                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    449258797                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.954842                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.673453                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           447734787                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.208829                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.927838                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles               146627317                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles            209331987                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 78382912                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              9473245                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               3917341                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved            14361500                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred              1009950                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts             470418171                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts              3106090                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               3917341                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles               152067726                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               18239112                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles     166025180                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 82266415                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             25216691                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             459074168                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                65027                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               1852942                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents               1258209                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents              11783264                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.FullRegisterEvents            3675                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands          439034296                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            699577887                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       541505861                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups           695779                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            366271083                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                72763213                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts          10011965                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts       8575733                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 52414102                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            74518711                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores           62619461                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          9405778                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores        10283621                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 436211457                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded            9985811                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                434881060                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           606856                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined       56709441                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     39627449                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        236091                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    447734787                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.971292                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.683506                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0          283324312     63.06%     63.06% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1           67630078     15.05%     78.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2           31491211      7.01%     85.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3           22481401      5.00%     90.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           17057859      3.80%     93.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5           11702074      2.60%     96.53% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            7876083      1.75%     98.29% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7            4650016      1.04%     99.32% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8            3045763      0.68%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0          279611354     62.45%     62.45% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1           68418670     15.28%     77.73% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2           31957007      7.14%     84.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3           22824194      5.10%     89.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           17260103      3.85%     93.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5           11876528      2.65%     96.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            7949958      1.78%     98.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7            4742790      1.06%     99.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8            3094183      0.69%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      449258797                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      447734787                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                2154851     25.07%     25.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                 17173      0.20%     25.27% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                   1684      0.02%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               3571205     41.55%     66.84% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite              2850152     33.16%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                2194515     25.29%     25.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                 17472      0.20%     25.49% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                   1369      0.02%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               1      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               3568581     41.12%     66.62% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite              2897037     33.38%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            289729991     67.54%     67.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult             1034875      0.24%     67.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                48976      0.01%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                286      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc         48552      0.01%     67.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     67.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            78627004     18.33%     86.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite           59481539     13.87%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            294218561     67.65%     67.65% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult             1060208      0.24%     67.90% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                49487      0.01%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                203      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc         49890      0.01%     67.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     67.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            79213886     18.22%     86.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite           60288825     13.86%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             428971223                       # Type of FU issued
-system.cpu2.iq.rate                          0.920582                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    8595065                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.020036                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads        1315569237                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        495173501                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    412035990                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             829250                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            394091                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       358547                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             437122606                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 443682                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads         3384290                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             434881060                       # Type of FU issued
+system.cpu2.iq.rate                          0.936509                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    8678975                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.019957                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads        1325952907                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        503003259                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    418204813                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             829831                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            395434                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       359511                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             443116084                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 443951                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads         3398365                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads     12185839                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses        16415                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation       485486                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores      6512236                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads     12383710                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses        15996                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation       500564                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores      6611339                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      2660066                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked      6807125                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      2691934                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked      6258076                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               3856816                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               10978406                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              6986714                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          439540206                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts          1332617                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             73490892                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts            61773042                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts           8263038                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                174452                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              6729882                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents        485486                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect       1971342                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect      1708494                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts             3679836                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            423953682                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             77064700                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts          4393197                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               3917341                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               10960428                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              5883186                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          446296417                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts          1350381                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             74518711                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts            62619461                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts           8384922                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                176072                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              5630257                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents        500564                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect       2018361                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect      1727301                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts             3745662                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            429773841                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             77626990                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts          4469356                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        95753                       # number of nop insts executed
-system.cpu2.iew.exec_refs                   135758319                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                78468818                       # Number of branches executed
-system.cpu2.iew.exec_stores                  58693619                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.909814                       # Inst execution rate
-system.cpu2.iew.wb_sent                     413267935                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    412394537                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                203830371                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                353623803                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        99149                       # number of nop insts executed
+system.cpu2.iew.exec_refs                   137107534                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                79765421                       # Number of branches executed
+system.cpu2.iew.exec_stores                  59480544                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.925511                       # Inst execution rate
+system.cpu2.iew.wb_sent                     419443427                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    418564324                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                206922501                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                359375214                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.885008                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.576405                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.901372                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.575784                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts       59831265                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls        9622401                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts          3310537                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    439132239                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.864557                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.865641                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts       60955622                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls        9749720                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts          3365248                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    437429844                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.880802                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.877626                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0    302394835     68.86%     68.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1     65341940     14.88%     83.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2     24189817      5.51%     89.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     10943430      2.49%     91.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4      7703754      1.75%     93.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5      4855013      1.11%     94.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      4328620      0.99%     95.59% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7      2957558      0.67%     96.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8     16417272      3.74%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0    298552711     68.25%     68.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1     66327454     15.16%     83.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2     24603217      5.62%     89.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     11085486      2.53%     91.57% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      7951378      1.82%     93.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5      4924801      1.13%     94.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      4385642      1.00%     95.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7      3037837      0.69%     96.21% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8     16561318      3.79%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    439132239                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           323541810                       # Number of instructions committed
-system.cpu2.commit.committedOps             379654747                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    437429844                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           328410291                       # Number of instructions committed
+system.cpu2.commit.committedOps             385289118                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                     116565859                       # Number of memory references committed
-system.cpu2.commit.loads                     61305053                       # Number of loads committed
-system.cpu2.commit.membars                    2541238                       # Number of memory barriers committed
-system.cpu2.commit.branches                  72175443                       # Number of branches committed
-system.cpu2.commit.fp_insts                    344817                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                348881889                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             9429592                       # Number of function calls committed.
+system.cpu2.commit.refs                     118143123                       # Number of memory references committed
+system.cpu2.commit.loads                     62135001                       # Number of loads committed
+system.cpu2.commit.membars                    2566531                       # Number of memory barriers committed
+system.cpu2.commit.branches                  73369628                       # Number of branches committed
+system.cpu2.commit.fp_insts                    345769                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                353907438                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             9528374                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       262221519     69.07%     69.07% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult         789172      0.21%     69.28% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           36211      0.01%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.29% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc        41986      0.01%     69.30% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.30% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.30% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.30% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead       61305053     16.15%     85.44% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite      55260806     14.56%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       266264239     69.11%     69.11% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult         801904      0.21%     69.32% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           36966      0.01%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc        42886      0.01%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead       62135001     16.13%     85.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite      56008122     14.54%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        379654747                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events             16417272                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        385289118                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events             16561318                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   859553355                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  889110894                       # The number of ROB writes
-system.cpu2.timesIdled                        2948522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       16719614                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                 99518769709                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  323541810                       # Number of Instructions Simulated
-system.cpu2.committedOps                    379654747                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.440242                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.440242                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.694328                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.694328                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               498743361                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              295064264                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                   684469                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                  420852                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                 90009576                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                90769749                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads             1656723881                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes               9715045                       # number of misc regfile writes
-system.iocache.tags.replacements               115464                       # number of replacements
-system.iocache.tags.tagsinuse               10.421560                       # Cycle average of tags in use
+system.cpu2.rob.rob_reads                   864512984                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  902807617                       # The number of ROB writes
+system.cpu2.timesIdled                        2960923                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       16629013                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                 99452987332                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  328410291                       # Number of Instructions Simulated
+system.cpu2.committedOps                    385289118                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.413975                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.413975                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.707226                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.707226                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               505452117                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              299365113                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                   681432                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                  426556                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                 91860984                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                92633679                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads             1668736685                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes               9854923                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40323                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40323                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136665                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30001                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48070                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48090                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156082                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13663000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy             7273000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy               33000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            16992000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy           330247943                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            38409000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy            36054619                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              144000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115453                       # number of replacements
+system.iocache.tags.tagsinuse               10.417239                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115480                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13085874574509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.547265                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.874295                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221704                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429643                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651348                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13085938891009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.549977                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.867262                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221874                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429204                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651077                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040224                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040224                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039605                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8819                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8856                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           65                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           65                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8819                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8859                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8808                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8848                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8819                       # number of overall misses
-system.iocache.overall_misses::total             8859                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8808                       # number of overall misses
+system.iocache.overall_misses::total             8848                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      2752000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1272471430                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1275223430                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     58617716                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     61369716                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9336377608                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9336377608                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      2752000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1272471430                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1275223430                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide     58617716                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     61369716                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      2752000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1272471430                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1275223430                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide     58617716                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     61369716                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8819                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8856                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106729                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106729                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8819                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8859                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8808                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8848                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8819                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8859                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8808                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8848                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000609                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000609                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -2310,63 +1694,755 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 144287.496315                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 143995.418925                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide  6655.054042                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total  6938.351159                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87530.728343                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 87530.728343                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 144287.496315                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 143946.656508                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide  6655.054042                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total  6935.998644                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 144287.496315                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 143946.656508                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36080                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide  6655.054042                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total  6935.998644                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56930                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3735                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7229                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.659973                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.875225                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106630                       # number of writebacks
+system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           16                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         5668                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         5684                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          391                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          407                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        34376                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        34376                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           16                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         5668                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         5684                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          391                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          407                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           16                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         5668                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         5684                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          391                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          407                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      1920000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    977655446                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    979575446                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2261356027                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2261356027                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     38284716                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     40204716                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7548587846                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7548587846                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      1920000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    977655446                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    979575446                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     38284716                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     40204716                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      1920000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    977655446                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    979575446                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     38284716                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     40204716                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet     0.432432                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.641825                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.046015                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.322283                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.322283                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.641607                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.045999                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.641607                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.045999                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet       120000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172486.846507                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 172339.100281                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 97914.874680                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 98783.085995                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219588.894752                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219588.894752                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 172486.846507                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 172339.100281                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 97914.874680                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 98783.085995                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 172486.846507                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 172339.100281                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 97914.874680                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 98783.085995                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1295349                       # number of replacements
+system.l2c.tags.tagsinuse                65279.372199                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   28812912                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1358291                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.212621                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   37161.709727                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   165.709328                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   242.089797                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3863.683177                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     8425.677492                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    52.724328                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    79.048207                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      858.449063                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3027.055416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker   115.755562                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker   187.843721                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2139.828130                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     8959.798251                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.567043                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002529                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.128566                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000805                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.001206                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1023          299                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62643                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          299                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          576                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2774                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4979                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54179                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004562                       # Percentage of cache occupancy per task id
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+system.l2c.tags.tag_accesses                273263421                       # Number of tag accesses
+system.l2c.tags.data_accesses               273263421                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu0.itb.walker       129157                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu0.data            3133333                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        70837                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total               21994233                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         7869277                       # number of Writeback hits
+system.l2c.Writeback_hits::total              7869277                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data       350049                       # number of WriteInvalidateReq hits
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+system.l2c.UpgradeReq_hits::cpu1.data            1538                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data            3474                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                9882                       # number of UpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_hits::total              1604749                       # number of ReadExReq hits
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+system.l2c.overall_hits::total               23598982                       # number of overall hits
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+system.l2c.ReadReq_misses::cpu0.itb.walker         1949                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            44357                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           135315                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker          578                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker          479                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst            11197                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            37623                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker         1473                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.itb.walker         1443                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst            33232                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data           109198                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               378829                       # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.data       405013                       # number of WriteInvalidateReq misses
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+system.l2c.WriteInvalidateReq_misses::total       506690                       # number of WriteInvalidateReq misses
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+system.l2c.UpgradeReq_misses::cpu1.data          5625                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total             35727                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_miss_latency::cpu2.data    149653065                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    213558817                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       144500                       # number of SCUpgradeReq miss cycles
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+system.l2c.Writeback_accesses::writebacks      7869277                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          7869277                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data       755062                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781996                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.785285                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.784317                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.783332                       # miss rate for UpgradeReq accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009773                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75894.153842                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::total 42471.035597                       # average ReadReq miss latency
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+system.l2c.WriteInvalidateReq_avg_miss_latency::total     1.828455                       # average WriteInvalidateReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11846.201615                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5977.518879                       # average UpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 96241.447012                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 43629.572708                       # average ReadExReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 74829.475472                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu2.inst 78597.774735                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 92507.827187                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 43131.790668                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 74829.475472                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 78834.688391                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 83610.358974                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 78597.774735                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 92507.827187                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 43131.790668                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks             1097767                       # number of writebacks
+system.l2c.writebacks::total                  1097767                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker           11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.itb.walker           22                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data             4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                37                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.dtb.walker           11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.itb.walker           22                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 37                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.dtb.walker           11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.itb.walker           22                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                37                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          578                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          479                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst        11197                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data        37623                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker         1462                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.itb.walker         1421                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst        33232                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data       109194                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          195186                       # number of ReadReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data        30137                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu2.data        71540                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::total       101677                       # number of WriteInvalidateReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         5625                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data        12633                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        18258                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        77509                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data       168114                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        245623                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker          578                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker          479                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        11197                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       115132                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker         1462                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker         1421                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst        33232                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data       277308                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           440809                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker          578                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker          479                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        11197                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       115132                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker         1462                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker         1421                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst        33232                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data       277308                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          440809                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     37895750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     31757500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    686314500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data   2382171250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     97090496                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    101432248                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst   2196003250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data   8117820950                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  13650485944                       # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data    616367003                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data   1933767537                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total   2550134540                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     56255625                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    126429131                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    182684756                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       130501                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4766611080                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14083669373                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  18850280453                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     37895750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     31757500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    686314500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   7148782330                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     97090496                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    101432248                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   2196003250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data  22201490323                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  32500766397                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     37895750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     31757500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    686314500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   7148782330                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     97090496                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    101432248                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   2196003250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data  22201490323                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  32500766397                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    816699000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1310911000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2127610000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    743754000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1345310999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2089064999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1560453000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2656221999                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4216674999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009528                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005424                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.036826                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.042406                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.008724                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.216939                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.212015                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.082570                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.785285                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.784317                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.400316                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.239097                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.233358                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.116541                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.009528                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005424                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.085549                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.084150                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.018006                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.009528                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005424                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.085549                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.084150                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.018006                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61294.498526                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63316.887276                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66080.983690                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74343.104475                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 69935.784042                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20452.168530                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 27030.577817                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25080.741367                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10007.846988                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.737540                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        60250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61497.517450                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 83774.518321                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 76744.769232                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61294.498526                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62092.053730                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66080.983690                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80060.763927                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 73729.815854                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61294.498526                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62092.053730                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66080.983690                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80060.763927                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 73729.815854                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              464434                       # Transaction distribution
+system.membus.trans_dist::ReadResp             464434                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33772                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33772                       # Transaction distribution
+system.membus.trans_dist::Writeback           1204397                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       613284                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       613284                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36382                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36386                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            502275                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           502275                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122952                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4037051                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4166813                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337307                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       337307                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4504120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156082                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159247392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    159417170                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14194688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14194688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               173611858                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              579                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2743991                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2743991    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2743991                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            42257500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             1290500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy          6097591000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         4309666748                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy           38158381                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq           22879889                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          22879700                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33772                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33772                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          7869277                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1265786                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1231410                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           45609                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          45616                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2107606                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2107606                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29099470                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28504181                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       848529                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1761011                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              60213191                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    928591700                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1156912126                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3110208                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6320128                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2094934162                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          368424                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         34177702                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003380                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.058037                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               34062190     99.66%     99.66% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115512      0.34%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           34177702                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        26362663917                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           981000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy       35502866905                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy       21222039348                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         273701566                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         651522269                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index b5546b4d2..cd3f04231 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,164 +1,158 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.316753                       # Number of seconds simulated
-sim_ticks                                51316753294500                       # Number of ticks simulated
-final_tick                               51316753294500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.358466                       # Number of seconds simulated
+sim_ticks                                51358465585500                       # Number of ticks simulated
+final_tick                               51358465585500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136598                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160520                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7792719388                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 670460                       # Number of bytes of host memory used
-host_seconds                                  6585.22                       # Real time elapsed on the host
-sim_insts                                   899526584                       # Number of instructions simulated
-sim_ops                                    1057057755                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 124397                       # Simulator instruction rate (inst/s)
+host_op_rate                                   146176                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7088870517                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 677952                       # Number of bytes of host memory used
+host_seconds                                  7244.94                       # Real time elapsed on the host
+sim_insts                                   901249371                       # Number of instructions simulated
+sim_ops                                    1059038863                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        436032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       324288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       511488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3575488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         35714136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       305664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       479488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3431104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         34340592                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             79118280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3575488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3431104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7006592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     46041344                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      50417380                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      49769472                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         153054692                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6813                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         5067                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         7992                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             55867                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            558041                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         4776                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         7492                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             53611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            536577                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1236236                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          719396                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           790023                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           777648                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2393731                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          6319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          9967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               69675                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              695955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          5956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          9344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               66861                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              669189                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1541763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          69675                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          66861                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             136536                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            897199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          133027                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             982474                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             969848                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2982548                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            897199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          141524                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         6319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         9967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              69675                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1678429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         5956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         9344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              66861                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1639037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4524311                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1236236                       # Number of read requests accepted
-system.physmem.writeReqs                      2393731                       # Number of write requests accepted
-system.physmem.readBursts                     1236236                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2393731                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 78915968                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    203136                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 148972800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  79118280                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              153054692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     3174                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   66016                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          38473                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               78969                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               76054                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               70113                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               71416                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               73251                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               79391                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               70957                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               70585                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               72320                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              103108                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              75527                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              73923                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              74067                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              84199                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              79405                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              79777                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              143281                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              127790                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              148899                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              137605                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              197374                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              124383                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              109194                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              129383                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              151210                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              186118                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             208778                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             141342                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             123729                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             141617                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             124170                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             132827                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker       144192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       134400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3960256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         28248856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       172736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       160128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3375488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         26920496                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        423040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             63539592                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3960256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3375488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7335744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     82068736                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          82089316                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2253                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2100                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             61879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            441396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2699                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             52742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            420638                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                992819                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1282324                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1284897                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2617                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               77110                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              550033                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               65724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              524169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1237179                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          77110                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          65724                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             142834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1597959                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1598360                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1597959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2617                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              77110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             550434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              65724                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             524169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2835539                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        992819                       # Number of read requests accepted
+system.physmem.writeReqs                      1909642                       # Number of write requests accepted
+system.physmem.readBursts                      992819                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1909642                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 63506944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 121761344                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  63539592                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              122072996                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7111                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          37069                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               60948                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               60211                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               58469                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               57182                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               59427                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               69894                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               60719                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               60135                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               57063                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               84498                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              60252                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              64911                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              58664                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              62105                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              58293                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              59525                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              119395                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              117730                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              117506                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              117615                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              116969                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              124824                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              116994                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              119672                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              117205                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              123532                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             118074                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             121555                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             115761                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             122535                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             116498                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             116656                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         128                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51316752176000                       # Total gap between requests
+system.physmem.numWrRetry                          94                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51358464467000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1236221                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  992804                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2391158                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    748020                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    328495                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    109863                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     42754                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       432                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       243                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       45                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1907069                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    594810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    261742                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     92458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     39543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1048                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       475                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       420                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       332                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       232                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       158                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       99                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       71                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -168,177 +162,207 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       745                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    48235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    79967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    90575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   105567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   121035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   143044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   145669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   159604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   163480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   180978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   163179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   154131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   135532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   135592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   103470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    98111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    96185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    91160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     8423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     6931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     6049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     5454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     5353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     5092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     4812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     4475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     4359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     4005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     3822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     3600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     3551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     3323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     3157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     3047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     3111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     2761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     2716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     1616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     1233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      336                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       678102                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      336.067624                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.620268                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     366.767956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         271362     40.02%     40.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       148250     21.86%     61.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55753      8.22%     70.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        26626      3.93%     74.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        20429      3.01%     77.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13236      1.95%     78.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10909      1.61%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        14852      2.19%     82.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       116685     17.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         678102                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         81261                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.173946                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      173.903253                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          81255     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            3      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-12287            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           81261                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         81261                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        28.644737                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       24.485973                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.407420                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                56      0.07%      0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15              139      0.17%      0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           47231     58.12%     58.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            7834      9.64%     68.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39           13023     16.03%     84.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            3682      4.53%     88.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            2148      2.64%     91.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             950      1.17%     92.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71            2747      3.38%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79            1058      1.30%     97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             767      0.94%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             240      0.30%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            341      0.42%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           185      0.23%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           486      0.60%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             8      0.01%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            31      0.04%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            23      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            18      0.02%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            31      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            73      0.09%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            62      0.08%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            51      0.06%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             8      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            17      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            17      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             9      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             7      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           81261                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    27538646010                       # Total ticks spent queuing
-system.physmem.totMemAccLat               50658558510                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6165310000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22333.55                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::0                       824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      735                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      734                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    38063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    69896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    79199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    93003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   104514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   119076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   117779                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   128388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   124328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   136701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   126686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   112871                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   105936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   106364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    92202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    90503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    89684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    85602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     5964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     4975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     4275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     4024                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     3728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     3450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     3239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     3237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     3041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     2633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     2541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     2466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     2243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     2077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      225                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       619163                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      299.223151                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     170.216009                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.259099                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         254617     41.12%     41.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       146485     23.66%     64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        55354      8.94%     73.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28104      4.54%     78.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20475      3.31%     81.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12983      2.10%     83.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10576      1.71%     85.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9506      1.54%     86.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        81063     13.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         619163                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         77925                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.733693                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       58.402560                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           77917     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           77925                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         77925                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.414771                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       21.404795                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       17.389828                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                83      0.11%      0.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                12      0.02%      0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               10      0.01%      0.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              84      0.11%      0.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           52239     67.04%     67.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2830      3.63%     70.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             709      0.91%     71.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            6561      8.42%     80.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            7338      9.42%     89.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39            1031      1.32%     90.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43            1085      1.39%     92.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47            1174      1.51%     93.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             800      1.03%     94.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             285      0.37%     95.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59             381      0.49%     95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63             214      0.27%     96.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             366      0.47%     96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71             298      0.38%     96.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75             251      0.32%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             217      0.28%     97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             385      0.49%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87             175      0.22%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91             111      0.14%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95             109      0.14%     98.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             293      0.38%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            79      0.10%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            56      0.07%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            98      0.13%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115           168      0.22%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            47      0.06%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            31      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            43      0.06%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131           108      0.14%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            28      0.04%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139            23      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            23      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            29      0.04%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            14      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155            15      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159            12      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            14      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167            22      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171            10      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             7      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179            16      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             7      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           77925                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    27174725250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               45780275250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4961480000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27385.70                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41083.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.90                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.54                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46135.70                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.24                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.37                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.38                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     964323                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1918333                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.41                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14136974.85                       # Average gap between requests
-system.physmem.pageHitRate                      80.96                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49243370940756                       # Time in different power states
-system.physmem.memoryStateTime::REF      1713579140000                       # Time in different power states
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         8.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     765740                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1509913                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.36                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17694799.16                       # Average gap between requests
+system.physmem.pageHitRate                      78.61                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49399135941008                       # Time in different power states
+system.physmem.memoryStateTime::REF      1714971960000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      359802419244                       # Time in different power states
+system.physmem.memoryStateTime::ACT      244357347492                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2507478120                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2618973000                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1368167625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1429003125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               4607662800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               5010142800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              7244050320                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              7839445680                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3351760797840                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3351760797840                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1283842483380                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1294175764575                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29663873874750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29654809593000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34315204514835                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34317643720020                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.694001                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.741533                       # Core power per rank (mW)
+system.physmem.actEnergy::0                2363029200                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                2317843080                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1289351250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1264696125                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               3798436200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               3941425800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              6160568400                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              6167767680                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3354485153760                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3354485153760                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1233743623290                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1233089726130                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29732846799750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29733420393750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34334686961850                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34334687006325                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.530261                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.530262                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst         1408                       # Number of bytes read from this memory
@@ -361,722 +385,22 @@ system.realview.nvmem.bw_total::cpu0.inst           15                       # T
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           27                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              43                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              532705                       # Transaction distribution
-system.membus.trans_dist::ReadResp             532705                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33859                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33859                       # Transaction distribution
-system.membus.trans_dist::Writeback            719396                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1671762                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1671762                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            38473                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           38479                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            739347                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           739347                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6390536                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6520668                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       228990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       228990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6749658                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    224910444                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    225082704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7262528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7262528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               232345232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2042                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3647418                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3647418    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3647418                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            99715500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               54328                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5596000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         23226177977                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        13225855665                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186556779                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   929985                       # number of replacements
-system.l2c.tags.tagsinuse                64575.668438                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   30861842                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   992077                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    31.108313                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             13810399676500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   34297.192611                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   188.067974                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   294.738587                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4135.506905                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11979.022995                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   180.539676                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   275.280153                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3419.385027                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9805.934509                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.523334                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002870                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004497                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063103                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.182785                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002755                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004200                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.052176                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.149627                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.985347                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          456                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61636                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          436                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2227                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5080                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54047                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.006958                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.940491                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                289012546                       # Number of tag accesses
-system.l2c.tags.data_accesses               289012546                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       544051                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       184997                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            8073705                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3475971                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       537537                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       184939                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            7954467                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3403637                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               24359304                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7101304                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7101304                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            6521                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            6161                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               12682                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           714827                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           684126                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1398953                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        544051                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        184997                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             8073705                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4190798                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        537537                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        184939                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7954467                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4087763                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                25758257                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       544051                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       184997                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            8073705                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4190798                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       537537                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       184939                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            7954467                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4087763                       # number of overall hits
-system.l2c.overall_hits::total               25758257                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         5086                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         8033                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            43375                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           182199                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         4792                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         7524                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            45500                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           173082                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               469591                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         19389                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         18469                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             37858                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            3                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            3                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               6                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         376161                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         363798                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             739959                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         5086                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         8033                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             43375                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            558360                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         4792                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         7524                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             45500                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            536880                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1209550                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         5086                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         8033                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            43375                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           558360                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         4792                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         7524                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            45500                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           536880                       # number of overall misses
-system.l2c.overall_misses::total              1209550                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    402067961                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    620871486                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   3358802499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14928489876                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    371387969                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    584303733                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   3543805470                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  14055803105                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    37865532099                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    215945240                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    206928138                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    422873378                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data        45998                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        45998                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        91996                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  33150632854                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  32508892128                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  65659524982                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    402067961                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    620871486                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3358802499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  48079122730                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    371387969                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    584303733                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3543805470                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  46564695233                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    103525057081                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    402067961                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    620871486                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3358802499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  48079122730                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    371387969                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    584303733                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3543805470                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  46564695233                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   103525057081                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       549137                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       193030                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst        8117080                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        3658170                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       542329                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       192463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst        7999967                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data        3576719                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total           24828895                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      7101304                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          7101304                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        25910                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        24630                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           50540                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            9                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            14                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1090988                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1047924                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2138912                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       549137                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       193030                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         8117080                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         4749158                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       542329                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       192463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         7999967                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         4624643                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            26967807                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       549137                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       193030                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        8117080                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4749158                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       542329                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       192463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        7999967                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        4624643                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           26967807                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009262                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.041615                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.005344                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.049806                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008836                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.039093                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.005688                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.048391                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018913                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.748321                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.749858                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.749070                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.333333                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.600000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.344789                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.347161                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.345951                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009262                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.041615                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005344                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.117570                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008836                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.039093                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005688                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.116091                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.044852                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009262                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.041615                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005344                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.117570                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008836                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.039093                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005688                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.116091                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.044852                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79053.865710                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 77290.114030                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77436.368853                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 81935.081290                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77501.662980                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 77658.656699                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77885.834505                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 81208.924700                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 80635.131634                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11137.513023                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11204.079160                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 11169.987268                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15332.666667                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15332.666667                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15332.666667                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88128.840720                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 89359.732951                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 88734.004157                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79053.865710                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 77290.114030                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 77436.368853                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 86107.748997                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77501.662980                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 77658.656699                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 77885.834505                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 86732.035526                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 85589.729305                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79053.865710                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 77290.114030                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 77436.368853                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 86107.748997                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77501.662980                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 77658.656699                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 77885.834505                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 86732.035526                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 85589.729305                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              719396                       # number of writebacks
-system.l2c.writebacks::total                   719396                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           19                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           41                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            10                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           16                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           32                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               131                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker           19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           41                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           32                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                131                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker           19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.itb.walker           41                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.dtb.walker           16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.itb.walker           32                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               131                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         5067                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         7992                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        43374                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       182189                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         4776                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         7492                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        45500                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       173070                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          469460                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        19389                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        18469                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        37858                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            6                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       376161                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       363798                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        739959                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         5067                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         7992                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        43374                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       558350                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         4776                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         7492                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        45500                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       536868                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1209419                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         5067                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         7992                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        43374                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       558350                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         4776                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.inst        45500                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       536868                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1209419                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    337731462                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2814140251                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  12660420650                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    310477469                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    489154483                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2972644030                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data  11900726415                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  32003757746                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  18731109098                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data  18506673413                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total  37237782511                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    194429364                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    185281438                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    379710802                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        60006                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  28452194992                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  27967189734                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  56419384726                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    337731462                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    518462986                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   2814140251                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  41112615642                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    310477469                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    489154483                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   2972644030                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  39867916149                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  88423142472                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    337731462                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    518462986                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   2814140251                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  41112615642                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    310477469                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    489154483                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   2972644030                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  39867916149                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  88423142472                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3015317250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2261474250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6356714999                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3033164500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2138382499                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5171546999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6048481750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4399856749                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11528261998                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009227                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.041403                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005344                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.049803                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008806                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.038927                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005688                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.048388                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018908                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.748321                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.749858                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.749070                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.344789                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347161                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.345951                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.009227                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.041403                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005344                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.117568                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008806                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.038927                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005688                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.116089                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.044847                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.009227                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.041403                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005344                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.117568                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008806                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.038927                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005688                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.116089                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.044847                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64880.809955                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69490.587522                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65332.835824                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68762.503120                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 68171.426205                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.818041                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.023282                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.869565                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75638.343667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76875.600564                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 76246.636268                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64880.809955                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73632.337498                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65332.835824                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74260.183414                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 73112.083134                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64880.809955                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73632.337498                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65332.835824                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74260.183414                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 73112.083134                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq           25440595                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25432319                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33859                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33859                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7101304                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1671768                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1565098                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           50543                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            14                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          50557                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2138912                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2138912                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     32275606                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29216023                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       915477                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2586660                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              64993766                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1032811840                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1154800272                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3083944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8731728                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2199427784                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          664547                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         36349119                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003178                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.056284                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               36233600     99.68%     99.68% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115519      0.32%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           36349119                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        52855909091                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2566500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       72684313037                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       43208232692                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         533902381                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1509803178                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40375                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40375                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136543                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq          190                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354216                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334216                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334216                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492622                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981411596                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           178989221                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups              132719565                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         89993236                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5932836                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            90710148                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               64716268                       # Number of BTB hits
+system.cpu0.branchPred.lookups              131952150                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         89649773                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5822015                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            90992883                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               64634149                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.344022                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17452568                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            191045                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.032093                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17244860                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            187476                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1100,25 +424,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   106360367                       # DTB read hits
-system.cpu0.dtb.read_misses                    615971                       # DTB read misses
-system.cpu0.dtb.write_hits                   81393112                       # DTB write hits
-system.cpu0.dtb.write_misses                   266071                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   105327476                       # DTB read hits
+system.cpu0.dtb.read_misses                    614604                       # DTB read misses
+system.cpu0.dtb.write_hits                   81433492                       # DTB write hits
+system.cpu0.dtb.write_misses                   261715                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1084                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              22107                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    543                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   56260                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      229                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9041                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21241                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   54785                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      190                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8902                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    57266                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               106976338                       # DTB read accesses
-system.cpu0.dtb.write_accesses               81659183                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    53829                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               105942080                       # DTB read accesses
+system.cpu0.dtb.write_accesses               81695207                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        187753479                       # DTB hits
-system.cpu0.dtb.misses                         882042                       # DTB misses
-system.cpu0.dtb.accesses                    188635521                       # DTB accesses
+system.cpu0.dtb.hits                        186760968                       # DTB hits
+system.cpu0.dtb.misses                         876319                       # DTB misses
+system.cpu0.dtb.accesses                    187637287                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1140,461 +464,760 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    95391690                       # ITB inst hits
-system.cpu0.itb.inst_misses                    104013                       # ITB inst misses
+system.cpu0.itb.inst_hits                    94794688                       # ITB inst hits
+system.cpu0.itb.inst_misses                    101824                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1084                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              22107                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    543                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41837                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21241                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   41122                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   207435                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   203923                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                95495703                       # ITB inst accesses
-system.cpu0.itb.hits                         95391690                       # DTB hits
-system.cpu0.itb.misses                         104013                       # DTB misses
-system.cpu0.itb.accesses                     95495703                       # DTB accesses
-system.cpu0.numCycles                       684418323                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                94896512                       # ITB inst accesses
+system.cpu0.itb.hits                         94794688                       # DTB hits
+system.cpu0.itb.misses                         101824                       # DTB misses
+system.cpu0.itb.accesses                     94896512                       # DTB accesses
+system.cpu0.numCycles                       673746678                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         248384937                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     589536301                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  132719565                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          82168836                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    395321090                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13514905                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2556917                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               20977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             5408                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5551519                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       175554                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         1648                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 95166614                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3687085                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  41415                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         658775231                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.047637                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.297009                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         246770894                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     586838334                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  131952150                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          81879009                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    386930341                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13253583                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2358226                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               20576                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             5110                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5338145                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       169787                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         2046                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 94573624                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3603023                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  38939                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         648221646                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.060144                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.307830                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               512971129     77.87%     77.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18432133      2.80%     80.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18348661      2.79%     83.45% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13411814      2.04%     85.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28741584      4.36%     89.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 9038627      1.37%     91.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9794305      1.49%     92.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8428424      1.28%     93.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39608554      6.01%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               503028040     77.60%     77.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                18376002      2.83%     80.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18277372      2.82%     83.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13314289      2.05%     85.31% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28669690      4.42%     89.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8974243      1.38%     91.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9730545      1.50%     92.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8410547      1.30%     93.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                39440918      6.08%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           658775231                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.193916                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.861368                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               200994103                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            333361407                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105045785                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             14028144                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5343793                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19697248                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1433030                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             641923192                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4435962                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5343793                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               208785389                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               28964603                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     262496699                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                111103202                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             42079210                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             626316852                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                80050                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2362679                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1879089                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              21911490                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            5199                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          599577423                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            966250594                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       740756106                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           877957                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            502593400                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96984018                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15462984                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13497488                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 79320336                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           100980804                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85727659                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13927717                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14882282                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 593862929                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15564372                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                595387827                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           831090                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       76362787                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     53001437                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        356285                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    658775231                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.903780                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.628017                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           648221646                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.195848                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.871007                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               200186064                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            323821330                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                105067312                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13887509                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5257280                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19546951                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1388336                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             640651678                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4275147                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5257280                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               207892852                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               28836524                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     254594010                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                111072647                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             40565977                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             625329125                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                73391                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2369804                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1783636                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              20590537                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            4721                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          598881072                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            965488055                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       739733763                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           970310                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            502829107                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                96051965                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15333341                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13384841                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 78497988                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           100792231                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           85691546                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13482087                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14436592                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 593155856                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15408534                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                593869164                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           811141                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       75391106                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     52735595                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        350692                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    648221646                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.916151                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.637744                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          423143545     64.23%     64.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          100533840     15.26%     79.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43588427      6.62%     86.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           31078402      4.72%     90.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           23328962      3.54%     94.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           15913876      2.42%     96.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10814135      1.64%     98.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6320463      0.96%     99.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4053581      0.62%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          413675393     63.82%     63.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           99838135     15.40%     79.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           43354420      6.69%     85.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           30999055      4.78%     90.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           23185151      3.58%     94.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           15937923      2.46%     96.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10813303      1.67%     98.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6331141      0.98%     99.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4087125      0.63%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      658775231                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      648221646                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2985575     25.28%     25.28% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 23079      0.20%     25.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   3324      0.03%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               2      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5019003     42.51%     68.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3776946     31.99%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2980479     25.39%     25.39% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 23946      0.20%     25.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2481      0.02%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               3      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4885958     41.63%     67.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3844513     32.75%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            402885613     67.67%     67.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1422777      0.24%     67.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                64552      0.01%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 67      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         58868      0.01%     67.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           108485553     18.22%     86.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82470396     13.85%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            402330448     67.75%     67.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1450246      0.24%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                67448      0.01%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         71724      0.01%     68.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           107439270     18.09%     86.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           82509979     13.89%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             595387827                       # Type of FU issued
-system.cpu0.iq.rate                          0.869918                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11807929                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019832                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1861125914                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        685987174                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    571772727                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1063990                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            505463                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       456200                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             606627126                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 568629                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4761213                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             593869164                       # Type of FU issued
+system.cpu0.iq.rate                          0.881443                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11737380                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019764                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1847356027                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        684092325                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    571253396                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1152468                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            551459                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       500772                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             604990335                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 616209                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4719298                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16799552                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        22497                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       714171                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      9156054                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16584124                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        22051                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       699484                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8981937                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3900719                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      9933744                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3863484                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8859794                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5343793                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15674856                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles             11567544                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          609566615                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1794840                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            100980804                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85727659                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13194913                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                258499                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents             11189475                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        714171                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2685620                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2322794                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5008414                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            588648436                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            106351748                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5872018                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5257280                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15355080                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles             11717568                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          608700724                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1772426                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            100792231                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            85691546                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13094550                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                251810                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents             11354978                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        699484                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2666409                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2277536                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4943945                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            587171511                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            105317678                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5833659                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       139314                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   187749395                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               108957932                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81397647                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.860071                       # Inst execution rate
-system.cpu0.iew.wb_sent                     573457881                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    572228927                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                281462520                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                488752044                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       136334                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   186754203                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               108711734                       # Number of branches executed
+system.cpu0.iew.exec_stores                  81436525                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.871502                       # Inst execution rate
+system.cpu0.iew.wb_sent                     572939308                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    571754168                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                281506422                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                489082927                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.836081                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575880                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.848619                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575580                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       82137816                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15208087                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4518905                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    644781794                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.817863                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.810443                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       81075036                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15057842                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4452233                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    634439872                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.831521                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.823079                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    449449526     69.71%     69.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     97358122     15.10%     84.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33578375      5.21%     90.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     14917712      2.31%     92.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10631887      1.65%     93.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6530680      1.01%     94.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5822825      0.90%     95.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3984235      0.62%     96.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22508432      3.49%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    439457438     69.27%     69.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     96886239     15.27%     84.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     33460731      5.27%     89.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15060049      2.37%     92.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10644464      1.68%     93.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6550765      1.03%     94.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5894426      0.93%     95.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      4022234      0.63%     96.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22463526      3.54%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    644781794                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           448706085                       # Number of instructions committed
-system.cpu0.commit.committedOps             527343007                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    634439872                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           448815056                       # Number of instructions committed
+system.cpu0.commit.committedOps             527549931                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     160752856                       # Number of memory references committed
-system.cpu0.commit.loads                     84181251                       # Number of loads committed
-system.cpu0.commit.membars                    3744837                       # Number of memory barriers committed
-system.cpu0.commit.branches                 100346754                       # Number of branches committed
-system.cpu0.commit.fp_insts                    436641                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                484032213                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13338237                       # Number of function calls committed.
+system.cpu0.commit.refs                     160917716                       # Number of memory references committed
+system.cpu0.commit.loads                     84208107                       # Number of loads committed
+system.cpu0.commit.membars                    3677805                       # Number of memory barriers committed
+system.cpu0.commit.branches                 100249360                       # Number of branches committed
+system.cpu0.commit.fp_insts                    481111                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                484287281                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13244362                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       365400890     69.29%     69.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1092025      0.21%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           47793      0.01%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        49443      0.01%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84181251     15.96%     85.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      76571605     14.52%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       365417797     69.27%     69.27% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1102287      0.21%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           49909      0.01%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        62180      0.01%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       84208107     15.96%     85.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      76709609     14.54%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        527343007                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22508432                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total        527549931                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22463526                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                  1227661689                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1232973286                       # The number of ROB writes
-system.cpu0.timesIdled                        4104064                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       25643092                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 54070741689                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  448706085                       # Number of Instructions Simulated
-system.cpu0.committedOps                    527343007                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.525315                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.525315                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.655602                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.655602                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               693970255                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              408353798                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   822679                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  492268                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                125884227                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               126919674                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             2342378074                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15341166                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements         16116656                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.960235                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          173052626                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16117168                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.737161                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11668105000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   286.930366                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   225.029869                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.560411                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.439511                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999922                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                  1216684794                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1231052317                       # The number of ROB writes
+system.cpu0.timesIdled                        4081993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       25525032                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 47131326354                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  448815056                       # Number of Instructions Simulated
+system.cpu0.committedOps                    527549931                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.501168                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.501168                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.666148                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.666148                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               692564361                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              407943900                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   896391                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  528896                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                125905812                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               126977702                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             2322757937                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15198906                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10638925                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.983549                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          304517896                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10639437                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.621617                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1654841000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   289.769940                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   222.213609                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.565957                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.434011                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses       1345465491                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1345465491                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79979109                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     80848758                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      160827867                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67346505                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     67891780                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     135238285                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204132                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       199440                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       403572                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       171160                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       153591                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       324751                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1784441                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1798021                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3582462                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2031437                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2062591                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4094028                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147325614                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148740538                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       296066152                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147529746                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    148939978                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      296469724                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6500737                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6533272                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     13034009                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6519313                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6481267                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     13000580                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       668156                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       654202                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1322358                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       633593                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       607646                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total      1241239                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       311874                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       325474                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       637348                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           10                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13020050                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     13014539                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      26034589                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     13688206                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     13668741                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     27356947                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111607932917                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111225009746                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 222832942663                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 259750103307                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 246979475075                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 506729578382                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  25310357673                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  23982059689                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  49292417362                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4526632473                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4625804945                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   9152437418                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       268001                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       294001                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 371358036224                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 358204484821                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 729562521045                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 371358036224                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 358204484821                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 729562521045                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     86479846                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     87382030                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    173861876                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     73865818                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     74373047                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    148238865                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       872288                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       853642                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1725930                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       804753                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       761237                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1565990                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2096315                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2123495                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4219810                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2031439                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2062601                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4094040                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160345664                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    161755077                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    322100741                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161217952                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    162608719                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    323826671                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075171                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074767                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.074968                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088259                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087145                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.087700                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.765981                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.766366                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766171                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.787314                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.798235                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.792623                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.148772                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.153273                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.151037                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081200                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.080458                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.080827                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.084905                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.084059                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.084480                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17168.504574                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17024.396006                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17096.270431                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39843.171099                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.665730                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38977.459343                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39947.344230                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39467.156353                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39712.269242                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14514.298957                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14212.517574                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14360.188497                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26800.100000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24500.083333                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28522.013066                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27523.409382                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 28022.816917                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27129.781377                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26206.106680                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 26668.272635                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     59155859                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        42706                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3724749                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            967                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.881838                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    44.163392                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks      8137324                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8137324                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3661999                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3663033                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      7325032                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5427863                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5389700                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10817563                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         3334                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3491                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         6825                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       189406                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       198198                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       387604                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9089862                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      9052733                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     18142595                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9089862                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      9052733                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     18142595                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2838738                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2870239                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5708977                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1091450                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1091567                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2183017                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       661474                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       648177                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1309651                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       630259                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       604155                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1234414                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122468                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127276                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       249744                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           10                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3930188                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3961806                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7891994                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4591662                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4609983                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9201645                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43024166867                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  43656462738                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  86680629605                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  40600883832                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38849310828                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  79450194660                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13171462044                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12577725489                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25749187533                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  23923452719                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  22638090123                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  46561542842                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1614671914                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1630090692                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3244762606                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       247999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       269999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83625050699                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82505773566                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 166130824265                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  96796512743                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  95083499055                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 191880011798                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2877179750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2839380752                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5716560502                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2798393044                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2781680461                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5580073505                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5675572794                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5621061213                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11296634007                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032825                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032847                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032836                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014776                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014677                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014726                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758321                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759308                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758809                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.783171                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.793649                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.788264                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058421                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059937                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059184                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024511                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024493                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024502                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028481                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028350                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028415                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15156.089384                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15210.044438                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15183.215768                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37199.032326                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35590.404279                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36394.675195                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19912.289892                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19404.769822                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19661.106305                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37958.129466                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37470.665844                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37719.551821                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13184.439315                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12807.526101                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12992.354595                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24799.900000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22499.916667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21277.620994                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20825.293708                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21050.551263                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21080.931642                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20625.563924                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20852.794451                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements         16118591                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.955303                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          173100510                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16119103                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.738843                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13625340000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   274.422577                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   237.532726                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.535982                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.463931                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        206428941                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       206428941                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     86457913                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     86594713                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      173052626                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     86457913                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     86594713                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       173052626                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     86457913                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     86594713                       # number of overall hits
-system.cpu0.icache.overall_hits::total      173052626                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8696178                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8562854                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17259032                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8696178                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8562854                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17259032                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8696178                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8562854                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17259032                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115519417356                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113985057745                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 229504475101                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 115519417356                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 113985057745                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 229504475101                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 115519417356                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 113985057745                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 229504475101                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     95154091                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     95157567                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    190311658                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     95154091                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     95157567                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    190311658                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     95154091                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     95157567                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    190311658                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091390                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.089986                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.090688                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091390                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.089986                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.090688                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091390                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.089986                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.090688                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13283.929717                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13311.573191                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13297.644683                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13283.929717                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13311.573191                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13297.644683                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13283.929717                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13311.573191                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13297.644683                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        66644                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        206488523                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       206488523                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     85967347                       # number of ReadReq hits
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+system.cpu0.icache.overall_miss_rate::total     0.090712                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13371.811270                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13316.434796                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13343.992783                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13371.811270                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13316.434796                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13343.992783                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13371.811270                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13316.434796                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13343.992783                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        69035                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             6194                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             6155                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    10.759445                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.216084                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       579009                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       562740                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1141749                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       579009                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       562740                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1141749                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       579009                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       562740                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1141749                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8117169                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8000114                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16117283                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8117169                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8000114                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8117169                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8000114                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16117283                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  94378713924                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  93158518069                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 187537231993                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  94378713924                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  93158518069                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 187537231993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  94378713924                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  93158518069                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 187537231993                       # number of overall MSHR miss cycles
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+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  93925882851                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  94357511095                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 188283393946                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  93925882851                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  94357511095                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 188283393946                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  93925882851                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  94357511095                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 188283393946                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    916338250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    595537750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1511876000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    916338250                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    595537750                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1511876000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.085306                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084072                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084689                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.085306                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084072                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.084689                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.085306                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084072                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.084689                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11627.048042                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11644.648822                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11635.784517                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11627.048042                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11644.648822                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11635.784517                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11627.048042                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11644.648822                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11635.784517                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084674                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.084674                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.084674                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11680.635901                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11680.635901                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11680.635901                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1602,293 +1225,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements         10609337                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.983537                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          304225194                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10609849                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.673848                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1654841000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   299.046294                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   212.937243                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.584075                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.415893                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1343384056                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1343384056                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80019383                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     80708532                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      160727915                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67091357                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     67952351                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135043708                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       206774                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       197330                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       404104                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       787450                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       777648                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1565098                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1810718                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1758217                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3568935                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2068647                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2014712                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4083359                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147110740                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    148660883                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       295771623                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147317514                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    148858213                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      296175727                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6473624                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6388313                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12861937                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6626672                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6359050                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12985722                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       668006                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       645779                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1313785                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       322811                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       316162                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       638973                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            9                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           14                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13100296                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12747363                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25847659                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13768302                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13393142                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     27161444                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116104812410                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112446419858                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 228551232268                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 283825834860                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 276276891882                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 560102726742                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4581170687                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4543459438                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   9124630125                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       155503                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       103503                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       259006                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 399930647270                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 388723311740                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 788653959010                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 399930647270                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 388723311740                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 788653959010                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     86493007                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     87096845                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    173589852                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73718029                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74311401                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    148029430                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       874780                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       843109                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1717889                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       787450                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       777648                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1565098                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2133529                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2074379                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4207908                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2068656                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2014717                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4083373                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    160211036                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    161408246                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    321619282                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    161085816                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    162251355                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    323337171                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074846                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.073347                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.074094                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.089892                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.085573                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087724                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.763627                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.765950                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764767                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.151304                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152413                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.151851                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081769                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.078976                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.080367                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085472                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.082546                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.084003                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17935.056532                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17601.895815                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17769.581072                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42830.825920                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43446.252488                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43132.197558                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14191.494983                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14370.668955                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14280.149748                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 17278.111111                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20700.600000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18500.428571                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30528.367242                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30494.409843                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 30511.620376                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29047.201846                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29024.056621                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 29035.789077                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     69133267                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        73151                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          4037000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1206                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.124911                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    60.655887                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1565098                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7101304                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7101304                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3596643                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3569355                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      7165998                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5504075                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5281537                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10785612                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       195820                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       191080                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       386900                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9100718                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8850892                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17951610                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9100718                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8850892                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17951610                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2876981                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2818958                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5695939                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1110111                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1065853                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2175964                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       660985                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       639380                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1300365                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126991                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       125082                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       252073                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            9                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           14                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3987092                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3884811                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7871903                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4648077                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4524191                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9172268                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44486434450                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  43558695911                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  88045130361                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  45021160958                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  43869767531                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  88890928489                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13293961502                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12330781777                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25624743279                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  29043542969                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  28669048764                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  57712591733                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1626539446                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1632214456                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3258753902                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       137497                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        93497                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       230994                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  89507595408                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  87428463442                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 176936058850                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102801556910                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  99759245219                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 202560802129                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3260677254                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2455829253                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5716506507                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3279198543                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2300797457                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5579996000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6539875797                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4756626710                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11296502507                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033263                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032366                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032813                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015059                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014343                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014700                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.755601                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.758360                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756955                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059522                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060299                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059905                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024887                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024068                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024476                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028855                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027884                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028368                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15462.887815                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15452.055657                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15457.526908                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40555.548912                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41159.303892                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40851.286367                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20112.349754                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19285.529383                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19705.808199                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12808.304888                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13049.155402                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12927.818140                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15277.444444                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18699.400000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16499.571429                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22449.342881                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22505.203842                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22476.910456                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22117.008154                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22050.184269                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22084.047493                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              132695624                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90331188                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5850625                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            91191115                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               65101533                       # Number of BTB hits
+system.cpu1.branchPred.lookups              133577738                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         90779695                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5949901                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            90899106                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               65330171                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.390215                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17167330                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            185817                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.871082                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17378415                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            188946                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1912,25 +1257,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   106438912                       # DTB read hits
-system.cpu1.dtb.read_misses                    617019                       # DTB read misses
-system.cpu1.dtb.write_hits                   81859907                       # DTB write hits
-system.cpu1.dtb.write_misses                   262953                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1095                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   106064392                       # DTB read hits
+system.cpu1.dtb.read_misses                    610373                       # DTB read misses
+system.cpu1.dtb.write_hits                   82025488                       # DTB write hits
+system.cpu1.dtb.write_misses                   271302                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1088                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21187                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    524                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   54609                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      175                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8788                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              22250                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55877                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      229                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8683                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    55422                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               107055931                       # DTB read accesses
-system.cpu1.dtb.write_accesses               82122860                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    56886                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               106674765                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82296790                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        188298819                       # DTB hits
-system.cpu1.dtb.misses                         879972                       # DTB misses
-system.cpu1.dtb.accesses                    189178791                       # DTB accesses
+system.cpu1.dtb.hits                        188089880                       # DTB hits
+system.cpu1.dtb.misses                         881675                       # DTB misses
+system.cpu1.dtb.accesses                    188971555                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1952,468 +1297,1193 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    95390425                       # ITB inst hits
-system.cpu1.itb.inst_misses                    103002                       # ITB inst misses
+system.cpu1.itb.inst_hits                    96043604                       # ITB inst hits
+system.cpu1.itb.inst_misses                    103294                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1095                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1088                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21187                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    524                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40480                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              22250                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   41299                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202732                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   205516                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                95493427                       # ITB inst accesses
-system.cpu1.itb.hits                         95390425                       # DTB hits
-system.cpu1.itb.misses                         103002                       # DTB misses
-system.cpu1.itb.accesses                     95493427                       # DTB accesses
-system.cpu1.numCycles                       672741965                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                96146898                       # ITB inst accesses
+system.cpu1.itb.hits                         96043604                       # DTB hits
+system.cpu1.itb.misses                         103294                       # DTB misses
+system.cpu1.itb.accesses                     96146898                       # DTB accesses
+system.cpu1.numCycles                       675301208                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         246640136                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     590780429                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  132695624                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          82268863                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    386429410                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13305333                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2543340                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               19984                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             4103                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5378147                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       163710                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         1900                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 95165721                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3597908                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  39974                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         647833125                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.067316                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.314702                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         248765293                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     593949498                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  133577738                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          82708586                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    386843919                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13545666                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2415137                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               21504                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             4007                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5459319                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       169387                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         1822                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 95816300                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3685759                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  39432                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         650452950                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.068285                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.315163                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               501796172     77.46%     77.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18436133      2.85%     80.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18485753      2.85%     83.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13501389      2.08%     85.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28566375      4.41%     89.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9032490      1.39%     91.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9749840      1.50%     92.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8516033      1.31%     93.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                39748940      6.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               503682671     77.44%     77.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18498717      2.84%     80.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18563467      2.85%     83.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13597541      2.09%     85.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                28733288      4.42%     89.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 9099977      1.40%     91.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9814186      1.51%     92.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8571904      1.32%     93.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39891199      6.13%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           647833125                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.197246                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.878168                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               200194473                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            322668892                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                105843727                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13827399                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5296426                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19681907                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1375410                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             644487824                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4238266                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5296426                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               207887374                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               28633275                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     252987067                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                111782593                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             41244065                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             628972841                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents               101309                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2336709                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1765264                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              21471594                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            4932                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          601986706                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            968135800                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       743741537                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           921788                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            504541868                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                97444838                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15091316                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13114684                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 77880403                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           101483347                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           86159667                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13596196                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14436334                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 596800589                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15137564                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                597335702                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           820098                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       76624490                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     53348640                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        353802                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    647833125                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.922052                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.644482                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           650452950                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.197805                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.879533                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               201647992                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            323236826                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                106239229                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13947017                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5379639                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19860273                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1413177                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             647237018                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4350385                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5379639                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               209424655                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               28067269                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     255930457                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                112228565                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             39419858                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             631550288                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                96632                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2287540                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1813390                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              19429955                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            4996                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          604714007                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            972949887                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       746652224                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           816553                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            506435319                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                98278683                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15335388                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13342018                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 78452935                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101901110                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           86377507                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13921613                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14837029                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 598946566                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15418828                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                598874973                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           821829                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       77129289                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     53862821                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        352968                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    650452950                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.920705                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.641335                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          412924221     63.74%     63.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           99304245     15.33%     79.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43461350      6.71%     85.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31157407      4.81%     90.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23474401      3.62%     94.21% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16043027      2.48%     96.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10934122      1.69%     98.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6355751      0.98%     99.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4178601      0.65%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          414330356     63.70%     63.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          100076970     15.39%     79.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43847279      6.74%     85.83% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           31289942      4.81%     90.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           23378361      3.59%     94.23% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16103120      2.48%     96.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10912961      1.68%     98.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6384879      0.98%     99.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4129082      0.63%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      647833125                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      650452950                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3005947     25.29%     25.29% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 24266      0.20%     25.49% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   2049      0.02%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               4      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4972015     41.83%     67.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3881824     32.66%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3013028     25.67%     25.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 23161      0.20%     25.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   2816      0.02%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               2      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4848351     41.30%     67.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3852019     32.81%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            404183986     67.66%     67.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1499549      0.25%     67.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                69544      0.01%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                173      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              9      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             16      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         70359      0.01%     67.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           108574781     18.18%     86.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           82937260     13.88%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            405949153     67.79%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1474390      0.25%     68.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                66030      0.01%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                142      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         56962      0.01%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           108207982     18.07%     86.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           83120313     13.88%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             597335702                       # Type of FU issued
-system.cpu1.iq.rate                          0.887912                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11886105                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019899                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1854102856                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        688730877                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    574087973                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1107876                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            525044                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       478100                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             608629489                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 592317                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4742542                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             598874973                       # Type of FU issued
+system.cpu1.iq.rate                          0.886826                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11739377                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019602                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1859775645                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        691731884                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    576296193                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             988457                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            469794                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       425393                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             610086136                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 528213                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4764786                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16809176                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        22821                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       704571                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      9065130                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16932520                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        21750                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       718636                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      9175857                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3904838                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      9464363                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3929336                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      8527630                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5296426                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               15503911                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles             11248845                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          612073318                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1785807                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            101483347                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            86159667                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12828539                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                251466                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents             10878256                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        704571                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2684400                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2302903                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4987303                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            590552056                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            106426998                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5916414                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5379639                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               15396107                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             10835641                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          614503705                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1815595                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            101901110                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            86377507                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13042378                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                259470                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents             10465486                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        718636                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2720399                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2342418                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5062817                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            592014750                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            106053814                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5994040                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       135165                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   188286771                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               109138667                       # Number of branches executed
-system.cpu1.iew.exec_stores                  81859773                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.877828                       # Inst execution rate
-system.cpu1.iew.wb_sent                     575751009                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    574566073                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                283200911                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                491579029                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       138311                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   188080635                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               109728675                       # Number of branches executed
+system.cpu1.iew.exec_stores                  82026821                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.876668                       # Inst execution rate
+system.cpu1.iew.wb_sent                     577948748                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    576721586                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                284303568                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                493660086                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.854066                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.576105                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.854021                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575910                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       82275122                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14783762                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4494113                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    633863514                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.835692                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.830647                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       82926260                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15065860                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4556436                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    636355753                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.835207                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.827690                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    439265925     69.30%     69.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     95913161     15.13%     84.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33589452      5.30%     89.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15187737      2.40%     92.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10634281      1.68%     93.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6553980      1.03%     94.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5971917      0.94%     95.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      4055542      0.64%     96.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22691519      3.58%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    440359254     69.20%     69.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     97084176     15.26%     84.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     33726039      5.30%     89.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15156809      2.38%     92.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10762314      1.69%     93.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6601636      1.04%     94.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5939289      0.93%     95.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      4020807      0.63%     96.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22705429      3.57%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    633863514                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           450820499                       # Number of instructions committed
-system.cpu1.commit.committedOps             529714748                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    636355753                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           452434315                       # Number of instructions committed
+system.cpu1.commit.committedOps             531488932                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     161768708                       # Number of memory references committed
-system.cpu1.commit.loads                     84674171                       # Number of loads committed
-system.cpu1.commit.membars                    3651509                       # Number of memory barriers committed
-system.cpu1.commit.branches                 100548022                       # Number of branches committed
-system.cpu1.commit.fp_insts                    459048                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                486295386                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13182426                       # Number of function calls committed.
+system.cpu1.commit.refs                     162170239                       # Number of memory references committed
+system.cpu1.commit.loads                     84968589                       # Number of loads committed
+system.cpu1.commit.membars                    3740598                       # Number of memory barriers committed
+system.cpu1.commit.branches                 101032588                       # Number of branches committed
+system.cpu1.commit.fp_insts                    407528                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                487762142                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13294479                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       366696799     69.23%     69.23% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1136926      0.21%     69.44% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           51579      0.01%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        60694      0.01%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       84674171     15.98%     85.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77094537     14.55%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       368091914     69.26%     69.26% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1129647      0.21%     69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           49240      0.01%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        47892      0.01%     69.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84968589     15.99%     85.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      77201650     14.53%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        529714748                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22691519                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total        531488932                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22705429                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                  1219313535                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1237971918                       # The number of ROB writes
-system.cpu1.timesIdled                        4075861                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       24908840                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 47205322910                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  450820499                       # Number of Instructions Simulated
-system.cpu1.committedOps                    529714748                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.492261                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.492261                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.670124                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.670124                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               696110289                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              410149745                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   853704                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  525664                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                126283635                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               127381072                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             2332819849                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14911197                       # number of misc regfile writes
-system.iocache.tags.replacements               115453                       # number of replacements
-system.iocache.tags.tagsinuse               10.425607                       # Cycle average of tags in use
+system.cpu1.rob.rob_reads                  1224024924                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1242947045                       # The number of ROB writes
+system.cpu1.timesIdled                        4091922                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       24848258                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 54236174505                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  452434315                       # Number of Instructions Simulated
+system.cpu1.committedOps                    531488932                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.492595                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.492595                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.669974                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.669974                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               697864723                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              411651158                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   767907                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  473740                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                126991866                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               128085324                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             2338745159                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15183498                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354224                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492654                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042420321                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           178996533                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115458                       # number of replacements
+system.iocache.tags.tagsinuse               10.429567                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13088656983000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544416                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.881191                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221526                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430074                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651600                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13090570223000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.541524                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.888043                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221345                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430503                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651848                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041134                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041134                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039650                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8809                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8846                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide          190                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total          190                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8809                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8849                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8809                       # number of overall misses
-system.iocache.overall_misses::total             8849                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5533000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1914739091                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1920272091                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
+system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1921756799                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1927241799                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5872000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1914739091                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1920611091                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5872000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1914739091                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1920611091                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28951102989                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28951102989                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1921756799                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1927580799                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1921756799                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1927580799                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8809                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8846                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106854                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106854                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8809                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8849                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8809                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8849                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.001778                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.001778                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149540.540541                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 217361.685889                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 217078.011644                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 218059.321343                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217767.434915                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       146800                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 217361.685889                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 217042.726975                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       146800                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 217361.685889                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 217042.726975                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         52653                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271423.376106                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271423.376106                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 218059.321343                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 217731.932565                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 218059.321343                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 217731.932565                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        227766                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27719                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.590710                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.216963                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106630                       # number of writebacks
+system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8809                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8846                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8809                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8849                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8809                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8849                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3609000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1456535121                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1460144121                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1463357813                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1466918813                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6643047696                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6643047696                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3792000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1456535121                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1460327121                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3792000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1456535121                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1460327121                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23404023041                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23404023041                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1463357813                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1467101813                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1463357813                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1467101813                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97540.540541                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165346.250539                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 165062.640855                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166045.366277                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 165753.538192                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94800                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 165346.250539                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 165027.361397                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94800                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 165346.250539                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 165027.361397                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219418.201464                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219418.201464                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 166045.366277                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 165718.040551                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 166045.366277                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 165718.040551                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1389484                       # number of replacements
+system.l2c.tags.tagsinuse                65352.106394                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   31455593                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1452181                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.660931                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               2484843000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35806.671040                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   143.176301                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   245.153324                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3359.514416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    11467.907347                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   184.237244                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   273.594467                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3844.520884                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    10027.331371                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.546366                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002185                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003741                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.051262                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.174986                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002811                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004175                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.058663                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.153005                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997194                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          343                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62354                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          341                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          538                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2779                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5047                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53889                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005234                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                295633480                       # Number of tag accesses
+system.l2c.tags.data_accesses               295633480                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       538849                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       186240                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst            7977279                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data            3458474                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker       540473                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       189439                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst            8047769                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data            3485516                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total               24424039                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         8137324                       # number of Writeback hits
+system.l2c.Writeback_hits::total              8137324                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data       356242                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::cpu1.data       359953                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::total       716195                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.data            4893                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            5150                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               10043                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             2                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             7                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 9                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           790931                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           806807                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1597738                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        538849                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker        186240                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             7977279                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4249405                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker        540473                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker        189439                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             8047769                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             4292323                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                26021777                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       538849                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       186240                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            7977279                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            4249405                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker       540473                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker       189439                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            8047769                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4292323                       # number of overall hits
+system.l2c.overall_hits::total               26021777                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         2272                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         2136                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            49402                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           157936                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker         2713                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker         2545                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst            44633                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data           153451                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               415088                       # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.data       274017                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::cpu1.data       244202                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::total       518219                       # number of WriteInvalidateReq misses
+system.l2c.UpgradeReq_misses::cpu0.data         17737                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         18576                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             36313                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data            3                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         284159                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         267759                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             551918                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         2272                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         2136                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             49402                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            442095                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2713                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2545                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             44633                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            421210                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                967006                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         2272                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         2136                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            49402                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           442095                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2713                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2545                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            44633                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           421210                       # number of overall misses
+system.l2c.overall_misses::total               967006                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    184273245                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker    176430743                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst   3875377998                       # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu1.data    215407746                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    425316733                       # number of UpgradeReq miss cycles
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782939                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.783351                       # miss rate for UpgradeReq accesses
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+system.l2c.overall_mshr_misses::cpu1.data       421202                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          966869                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    154831495                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    147977993                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   3255321002                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11404425184                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    185796240                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    171797741                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2937376759                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data  11125453714                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  29382980128                       # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  10490770082                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   9554022676                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total  20044792758                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    177667232                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    186014070                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    363681302                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       132001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       132001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  24275927309                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  22531972819                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  46807900128                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    154831495                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    147977993                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   3255321002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  35680352493                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    185796240                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    171797741                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   2937376759                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  33657426533                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  76190880256                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    154831495                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    147977993                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   3255321002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  35680352493                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    185796240                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    171797741                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   2937376759                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  33657426533                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  76190880256                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2657099750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2619741250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6356764499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2581434500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2590216000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5171650500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5238534250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5209957250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11528414999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.043668                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.042167                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016706                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.434769                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.404204                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.419810                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.783783                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782939                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.783351                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.300000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.264312                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.249179                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.256747                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.094230                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.089360                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.035825                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.094230                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.089360                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.035825                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72215.099662                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72505.449672                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 70810.722538                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38285.106698                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39123.441561                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38680.157922                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.757738                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10013.677326                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.181946                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 44000.333333                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44000.333333                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85430.788076                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84150.197823                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 84809.519037                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80709.806083                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79908.040638                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 78801.657987                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80709.806083                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79908.040638                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 78801.657987                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              478201                       # Transaction distribution
+system.membus.trans_dist::ReadResp             478201                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33860                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33860                       # Transaction distribution
+system.membus.trans_dist::Writeback           1282324                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       624745                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       624745                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37074                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           37077                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            551298                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           551298                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6868                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4264222                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4394358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335421                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335421                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4729779                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    171538732                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    171711000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14073856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14073856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               185784856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2907                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2919339                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2919339    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2919339                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            99723000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               54328                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5540499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         18597273982                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         9904783124                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186654467                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq           25451799                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25443711                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33860                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33860                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          8137324                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1341081                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1234414                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46359                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46371                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2149656                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2149656                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     32279635                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29644963                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       905204                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2573359                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              65403161                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1032942144                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1201952920                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3042880                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8674456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2246612400                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          665707                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         37265900                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003100                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.055590                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               37150380     99.69%     99.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115520      0.31%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           37265900                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        56232033216                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy          3430500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy       72693447528                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy       43148678653                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         527770675                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy        1503131700                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16389                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   16411                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 3f21941cc..549c3e2c6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,177 +1,158 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.861029                       # Number of seconds simulated
-sim_ticks                                51861029093000                       # Number of ticks simulated
-final_tick                               51861029093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.781932                       # Number of seconds simulated
+sim_ticks                                51781931516000                       # Number of ticks simulated
+final_tick                               51781931516000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 655308                       # Simulator instruction rate (inst/s)
-host_op_rate                                   770071                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            39176575505                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 667356                       # Number of bytes of host memory used
-host_seconds                                  1323.78                       # Real time elapsed on the host
-sim_insts                                   867480679                       # Number of instructions simulated
-sim_ops                                    1019401547                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 513884                       # Simulator instruction rate (inst/s)
+host_op_rate                                   603881                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31103019215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 672564                       # Number of bytes of host memory used
+host_seconds                                  1664.85                       # Real time elapsed on the host
+sim_insts                                   855540358                       # Number of instructions simulated
+sim_ops                                    1005371984                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide        385536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       227072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       396672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2360360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         30329136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       251456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       422720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2259596                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         29551000                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             66183548                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2360360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2259596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4619956                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     36744512                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      49590532                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      50357856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         143519396                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6024                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         3548                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         6198                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             64295                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            473896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3929                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         6605                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             48299                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            461744                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1074538                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          574133                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           774853                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           789092                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2244742                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             7434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          4378                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          7649                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               45513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              584816                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8151                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43570                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              569811                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1276171                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          45513                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43570                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89083                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            708519                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          131631                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             956220                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             971015                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2767384                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            708519                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          139065                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4378                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         7649                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              45513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1541035                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4849                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8151                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43570                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1540827                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4043555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1074538                       # Number of read requests accepted
-system.physmem.writeReqs                      2244742                       # Number of write requests accepted
-system.physmem.readBursts                     1074538                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2244742                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 68582272                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    188160                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 138957696                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  66183548                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              143519396                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2940                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   73507                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          34757                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               71255                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               63640                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               66612                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               61740                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               60545                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               71198                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               58053                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               57022                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               61158                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              112029                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              66876                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              66235                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              62785                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              68778                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              63805                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              59867                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              127784                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              113302                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              227736                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              110987                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              128170                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              133310                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              113658                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104648                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              114567                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              129854                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             127393                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             118149                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             133562                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             181801                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             180172                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             126121                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker       107200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       102528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2434152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20994800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        96832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       103680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2545804                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         20458904                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        379200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             47223100                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2434152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2545804                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4979956                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68447104                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          68467684                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1675                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1602                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             65448                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            328047                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1513                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1620                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             52771                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            319680                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           5925                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                778281                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1069486                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1072059                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               47008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              405446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               49164                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              395097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  911961                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          47008                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          49164                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              96172                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1321834                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1322231                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1321834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              47008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             405447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              49164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             395495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2234192                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        778281                       # Number of read requests accepted
+system.physmem.writeReqs                      1672780                       # Number of write requests accepted
+system.physmem.readBursts                      778281                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1672780                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 49778368                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     31616                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 106609920                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  47223100                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              106913828                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      494                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6998                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          34417                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               49121                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               48968                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               43998                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               44044                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               46923                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               50978                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               43709                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               43367                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               43043                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               89491                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              47224                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              49584                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              42821                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              45810                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              42383                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46323                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              104557                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              105414                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              105583                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              103819                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              104348                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              108141                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              101114                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              100245                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               99850                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              106510                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102540                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             107777                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             103459                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             105336                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             101779                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             105308                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51861026536500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51781928959500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1031422                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  735165                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2242169                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1023941                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     42084                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       554                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       705                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       186                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       99                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       81                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       79                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       41                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1670207                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    745946                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     26414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1937                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       535                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       685                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       348                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       274                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       204                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       78                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       44                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -184,850 +165,201 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    85670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                   108888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   136245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   120874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   128354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   124706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   123045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   137746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   127099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   129811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   118729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   118092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   115613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   114537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   111395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   110878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   111594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   108741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       38                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       634955                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      326.856851                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.109909                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     357.606066                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         251774     39.65%     39.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       143572     22.61%     62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53819      8.48%     70.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        28426      4.48%     75.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19160      3.02%     78.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        14370      2.26%     80.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10671      1.68%     82.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        11114      1.75%     83.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       102049     16.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         634955                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        109417                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean         9.793551                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      155.538286                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         109409     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-6143            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::18432-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          109417                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        109417                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.843480                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.459226                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.174824                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                51      0.05%      0.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                17      0.02%      0.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               14      0.01%      0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15             145      0.13%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           52162     47.67%     47.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23           51235     46.83%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            1984      1.81%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1760      1.61%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             951      0.87%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             159      0.15%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             147      0.13%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              71      0.06%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              99      0.09%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              20      0.02%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              21      0.02%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              18      0.02%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             372      0.34%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              33      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              39      0.04%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              25      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              36      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               9      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             4      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             9      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             7      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          109417                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    11994975500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               32087438000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5357990000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11193.54                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::0                      1607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1535                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      1509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      1486                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::8                      1410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      1402                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19                    95463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   110001                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   113998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    99922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   100596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    98621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    96222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    93100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    89862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    88090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    83497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    82653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    82465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    81037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      901                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       531423                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      294.281520                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     167.194093                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.137010                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         219913     41.38%     41.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       131435     24.73%     66.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44338      8.34%     74.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23886      4.49%     78.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15966      3.00%     81.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10709      2.02%     83.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7995      1.50%     85.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7287      1.37%     86.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        69894     13.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         531423                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         80476                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean         9.664621                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       89.984802                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          80471     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-7167            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           80476                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         80476                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.699090                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.496721                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.527834                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7               200      0.25%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15              177      0.22%      0.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           72247     89.77%     90.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            4200      5.22%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            1327      1.65%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             446      0.55%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             582      0.72%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             137      0.17%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             223      0.28%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             119      0.15%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             159      0.20%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              60      0.07%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            172      0.21%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            43      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            70      0.09%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            53      0.07%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           161      0.20%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            11      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            23      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            15      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            11      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           80476                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     9983720499                       # Total ticks spent queuing
+system.physmem.totMemAccLat               24567226749                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3888935000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12836.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29943.54                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.32                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.77                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31586.06                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.06                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.06                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.58                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     810923                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1796931                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15624179.50                       # Average gap between requests
-system.physmem.pageHitRate                      80.42                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49513780638000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1731753660000                       # Time in different power states
+system.physmem.avgWrQLen                        10.17                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     580589                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1331554                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.65                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21126332.21                       # Average gap between requests
+system.physmem.pageHitRate                      78.25                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49696712332000                       # Time in different power states
+system.physmem.memoryStateTime::REF      1729112320000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      615493469500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      356106481500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2375299080                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2424960720                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1296046125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1323143250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               3978491400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               4379902800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              6866175600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              7203291120                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3387310158960                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3387310158960                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1391264257590                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1403130352860                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29896208916750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29885800061250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34689299345505                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34691571870960                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.889557                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.933377                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              477149                       # Transaction distribution
-system.membus.trans_dist::ReadResp             477149                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33873                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33873                       # Transaction distribution
-system.membus.trans_dist::Writeback            574133                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1668036                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1668036                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34762                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34763                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            634040                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           634040                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6948                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5908571                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6038767                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       228229                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       228229                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6266996                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    202490912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    202661260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7212032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7212032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               209873292                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2859                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3311225                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3311225    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3311225                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107353000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5576998                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         22591732739                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        12337625717                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186623209                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   742012                       # number of replacements
-system.l2c.tags.tagsinuse                64270.398590                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   26902368                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   803524                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    33.480478                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             13975543266000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37175.370722                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   164.612464                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   268.035680                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3943.940555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8908.960135                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   136.845941                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   225.029794                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3060.985707                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    10386.617592                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.567251                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004090                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.060180                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.135940                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002088                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003434                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.046707                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.158487                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.980688                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          429                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61083                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          418                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1800                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5332                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53777                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.006546                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.932053                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                254875429                       # Number of tag accesses
-system.l2c.tags.data_accesses               254875429                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       223794                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       158122                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            6853057                       # number of ReadReq hits
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-system.l2c.UpgradeReq_miss_latency::cpu1.data    203951249                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    408424971                       # number of UpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.771092                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.774241                       # miss rate for UpgradeReq accesses
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-system.l2c.demand_miss_rate::cpu1.itb.walker     0.039530                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.itb.walker     0.037719                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005089                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.110192                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.itb.walker     0.039530                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005003                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.107052                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.044245                       # miss rate for overall accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74117.429264                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74510.214928                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76947.251209                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 77972.672218                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74038.356359                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 74072.220148                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 74398.137495                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11876.273744                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 11942.599813                       # average UpgradeReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 77972.672218                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74038.356359                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72415.462463                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 72839.575216                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76455.820180                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 76749.394966                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 72887.596911                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 77972.672218                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74038.356359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72415.462463                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 72839.575216                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
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-system.l2c.ReadReq_mshr_misses::cpu1.data       153129                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data        17173                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        34199                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::total        634600                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3548                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         6198                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        35053                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       474153                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         3929                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         6605                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        34440                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       462035                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1025961                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3548                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         6198                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        35053                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       474153                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         3929                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         6605                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        34440                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       462035                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1025961                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    227345750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    399113250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2153950252                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data   9192788002                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    253621250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    433387500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2113544507                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data   9415706501                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  24189457012                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  15500196009                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data  15731390003                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total  31231586012                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    170328525                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    171847671                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    342176196                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  19341366760                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18175312800                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  37516679560                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    227345750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    399113250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   2153950252                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  28534154762                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    253621250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    433387500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   2113544507                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  27591019301                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  61706136572                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    227345750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    399113250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   2153950252                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  28534154762                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    253621250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    433387500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   2113544507                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  27591019301                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  61706136572                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2513836750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2774658752                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7537465502                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2415529500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2751057500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5166587000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4929366250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5525716252                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12704052502                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.015606                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.037719                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005089                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.045452                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.016512                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.039530                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005003                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.046432                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018519                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.777443                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.771092                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.774241                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.314164                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.303416                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.308839                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.015606                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.037719                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005089                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.110192                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.016512                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.039530                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005003                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.107052                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.044245                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.015606                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.037719                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005089                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.110192                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.016512                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.039530                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005003                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.107052                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.044245                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61448.385359                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61921.392452                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61368.888124                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61488.721934                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61808.552748                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.024727                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.852093                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.444487                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59385.087720                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58837.681366                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 59118.625213                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61448.385359                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 60179.213802                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61368.888124                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59716.297036                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60144.719509                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61448.385359                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 60179.213802                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61368.888124                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59716.297036                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60144.719509                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.physmem.actEnergy::0                2031447600                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                1986110280                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1108428750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1083691125                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               2894642400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               3172057200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              5399272080                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              5394982320                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3382143697920                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3382143697920                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1286313063165                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1285469654400                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29940811051500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29941550883750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34620701603415                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34620801076995                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.586590                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.588511                       # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq           21596881                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          21588675                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33873                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33873                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          6657868                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1668053                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1561372                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           44174                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          44175                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2054795                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2054795                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     27631338                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27242891                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       786774                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1184296                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              56845299                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    881615316                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1077879160                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2651280                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3722288                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             1965868044                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          493907                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         31944858                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003617                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.060036                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               31829300     99.64%     99.64% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115558      0.36%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           31944858                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        48864007000                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          3007500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       62042103256                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       39821087024                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         456077500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         719536250                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40403                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40403                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136728                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            5                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231002                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231002                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354272                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334440                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334440                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492846                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981115277                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179046791                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1051,25 +383,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    81298671                       # DTB read hits
-system.cpu0.dtb.read_misses                     94598                       # DTB read misses
-system.cpu0.dtb.write_hits                   74077534                       # DTB write hits
-system.cpu0.dtb.write_misses                    29691                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51863                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    80391901                       # DTB read hits
+system.cpu0.dtb.read_misses                     93388                       # DTB read misses
+system.cpu0.dtb.write_hits                   73043030                       # DTB write hits
+system.cpu0.dtb.write_misses                    28813                       # DTB write misses
+system.cpu0.dtb.flush_tlb                       51784                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              19908                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   72449                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   70641                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4385                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4105                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9644                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                81393269                       # DTB read accesses
-system.cpu0.dtb.write_accesses               74107225                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9619                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                80485289                       # DTB read accesses
+system.cpu0.dtb.write_accesses               73071843                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        155376205                       # DTB hits
-system.cpu0.dtb.misses                         124289                       # DTB misses
-system.cpu0.dtb.accesses                    155500494                       # DTB accesses
+system.cpu0.dtb.hits                        153434931                       # DTB hits
+system.cpu0.dtb.misses                         122201                       # DTB misses
+system.cpu0.dtb.accesses                    153557132                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1091,480 +423,368 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   433719693                       # ITB inst hits
-system.cpu0.itb.inst_misses                     76771                       # ITB inst misses
+system.cpu0.itb.inst_hits                   427471663                       # ITB inst hits
+system.cpu0.itb.inst_misses                     76376                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51863                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                       51784                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              19908                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   53078                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   52019                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               433796464                       # ITB inst accesses
-system.cpu0.itb.hits                        433719693                       # DTB hits
-system.cpu0.itb.misses                          76771                       # DTB misses
-system.cpu0.itb.accesses                    433796464                       # DTB accesses
-system.cpu0.numCycles                     51861670459                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               427548039                       # ITB inst accesses
+system.cpu0.itb.hits                        427471663                       # DTB hits
+system.cpu0.itb.misses                          76376                       # DTB misses
+system.cpu0.itb.accesses                    427548039                       # DTB accesses
+system.cpu0.numCycles                     51782412762                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  433465167                       # Number of instructions committed
-system.cpu0.committedOps                    509426348                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            467950836                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                437595                       # Number of float alu accesses
-system.cpu0.num_func_calls                   25817816                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     66030471                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   467950836                       # number of integer instructions
-system.cpu0.num_fp_insts                       437595                       # number of float instructions
-system.cpu0.num_int_register_reads          681169150                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         371166205                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              709571                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             361724                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           113513031                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          113190912                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    155365727                       # number of memory refs
-system.cpu0.num_load_insts                   81295009                       # Number of load instructions
-system.cpu0.num_store_insts                  74070718                       # Number of store instructions
-system.cpu0.num_idle_cycles              50261080538.032112                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1600589920.967886                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.030863                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.969137                       # Percentage of idle cycles
-system.cpu0.Branches                         96751437                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                353168573     69.29%     69.29% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1074186      0.21%     69.50% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    48850      0.01%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             52802      0.01%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::MemRead                81295009     15.95%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               74070718     14.53%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                  427217866                       # Number of instructions committed
+system.cpu0.committedOps                    502133426                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            461356318                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                442453                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25480565                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     64997329                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   461356318                       # number of integer instructions
+system.cpu0.num_fp_insts                       442453                       # number of float instructions
+system.cpu0.num_int_register_reads          669433821                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         365789159                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              711452                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             379824                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           111391626                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          111077654                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    153423964                       # number of memory refs
+system.cpu0.num_load_insts                   80387324                       # Number of load instructions
+system.cpu0.num_store_insts                  73036640                       # Number of store instructions
+system.cpu0.num_idle_cycles              50249111943.842865                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1533300818.157139                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.029610                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.970390                       # Percentage of idle cycles
+system.cpu0.Branches                         95379703                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                347836061     69.23%     69.23% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1052847      0.21%     69.44% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47944      0.01%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  6      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  5      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  9      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.45% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             55653      0.01%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::MemRead                80387324     16.00%     85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite               73036640     14.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 509710139                       # Class of executed instruction
+system.cpu0.op_class::total                 502416489                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16204                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements         13772027                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.894677                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          854244882                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13772539                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            62.025229                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      31522505250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   257.415454                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   254.479223                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.502765                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.497030                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999794                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        881789970                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       881789970                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    426831583                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    427413299                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      854244882                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    426831583                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    427413299                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       854244882                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    426831583                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    427413299                       # number of overall hits
-system.cpu0.icache.overall_hits::total      854244882                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6888110                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6884434                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     13772544                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6888110                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      6884434                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      13772544                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6888110                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      6884434                       # number of overall misses
-system.cpu0.icache.overall_misses::total     13772544                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92034347501                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  91949004755                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 183983352256                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  92034347501                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  91949004755                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 183983352256                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  92034347501                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  91949004755                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 183983352256                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    433719693                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    434297733                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    868017426                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    433719693                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    434297733                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    868017426                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    433719693                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    434297733                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    868017426                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015881                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015852                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.015867                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015881                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015852                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.015867                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015881                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015852                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.015867                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13361.335330                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13356.073245                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13358.704990                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13361.335330                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13356.073245                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13358.704990                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13361.335330                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13356.073245                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13358.704990                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6888110                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6884434                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     13772544                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6888110                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6884434                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13772544                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6888110                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6884434                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13772544                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  78245563999                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  78167770745                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 156413334744                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  78245563999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  78167770745                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 156413334744                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  78245563999                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  78167770745                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 156413334744                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2831704500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   2831704500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015881                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015852                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015867                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015881                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015852                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.015867                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015881                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015852                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.015867                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11359.511390                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11354.277018                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11356.894902                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11359.511390                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11354.277018                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11356.894902                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11359.511390                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11354.277018                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11356.894902                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          9844382                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.969698                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          301160300                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9844894                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.590507                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   16160                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          9666641                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.969685                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          297154926                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9667153                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.738618                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       3092948250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   231.008949                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.960750                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.451189                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.548751                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   283.466253                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   228.503431                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.553645                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.446296                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           86                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1254251724                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1254251724                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     76026969                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     76417394                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      152444363                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     70302658                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     70301847                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     140604505                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       192417                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       194709                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       387126                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       774852                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       786520                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1561372                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1759844                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1765909                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3525753                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1907304                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1911679                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3818983                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    146329627                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    146719241                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       293048868                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    146522044                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    146913950                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      293435994                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2535096                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2582985                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      5118081                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1068169                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1052040                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2120209                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       619845                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       606565                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1226410                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148352                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       146540                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       294892                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1237347722                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1237347722                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     75260834                       # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190562                       # number of SoftPFReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total       382139                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       171619                       # number of WriteInvalidateReq hits
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+system.cpu0.dcache.WriteInvalidateReq_hits::total       332435                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1711920                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1739353                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3451273                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1857030                       # number of StoreCondReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total      3742274                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    144610498                       # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::cpu0.data    144801060                       # number of overall hits
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+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       612872                       # number of WriteInvalidateReq misses
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+system.cpu0.dcache.WriteInvalidateReq_misses::total      1225901                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145963                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       146688                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       292651                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3603265                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3635025                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       7238290                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4223110                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      4241590                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      8464700                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40091643502                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  40963569001                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  81055212503                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  35409870035                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33994777971                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  69404648006                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2096828250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2109514250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4206342500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        26501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  75501513537                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  74958346972                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 150459860509                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  75501513537                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  74958346972                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 150459860509                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     78562065                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     79000379                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    157562444                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     71370827                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     71353887                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    142724714                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       812262                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       801274                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1613536                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       774852                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       786520                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1561372                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1908196                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1912449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3820645                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1907305                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1911679                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3818984                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    149932892                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    150354266                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    300287158                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    150745154                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    151155540                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    301900694                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032269                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032696                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032483                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014966                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014744                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.014855                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.763110                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.757001                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760076                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077745                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076624                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077184                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_misses::cpu0.data      3507371                       # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total      8289887                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38409075253                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  39279047002                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  77688122255                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  27659575882                       # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total  55347220413                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  13571753508                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13540403000                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27112156508                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2071723750                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4166884000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        75000                       # number of StoreCondReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::cpu0.data  66068651135                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  66966691533                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 133035342668                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  66068651135                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  66966691533                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 133035342668                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     77740657                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       795893                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1573408                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031899                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total     0.032275                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014601                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014937                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.014769                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754909                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.759293                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757127                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.781235                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.792186                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078564                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077776                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078167                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024033                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024176                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.024105                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028015                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028061                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.028038                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15814.645087                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15859.003827                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15837.031986                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33150.063365                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32313.199090                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 32734.814354                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14134.142108                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14395.484168                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14264.010214                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        26501                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        26501                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20953.638863                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20621.136573                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20786.658245                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17878.178294                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17672.228332                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17774.978500                       # average overall miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023680                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024235                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.023957                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027498                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028162                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.027830                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15488.635783                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15465.805291                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15477.084288                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26918.037777                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26331.268241                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 26621.271350                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 22144.515507                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 22087.703844                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 22116.106038                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14193.485678                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14283.105980                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14238.406840                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        75000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18837.086563                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18647.197348                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18741.020107                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16136.644568                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15961.312351                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16047.907851                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1561372                       # number of fast writes performed
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      6657868                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6657868                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         2373                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2635                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total         5008                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9569                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11674                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21243                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        34459                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35374                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        69833                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        11942                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        14309                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        26251                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        11942                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        14309                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        26251                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2532723                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2580350                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5113073                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1058600                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1040366                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2098966                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       619670                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       606373                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1226043                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113893                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       111166                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       225059                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7479557                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7479557                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3745                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2865                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total         6610                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10175                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11006                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21181                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        34675                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35236                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        69911                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        13920                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data        13871                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        27791                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        13920                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data        13871                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        27791                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2476078                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2536870                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5012948                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1017373                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1040506                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2057879                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       586808                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       604126                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1190934                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       612872                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       613029                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1225901                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       111288                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       111452                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       222740                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3591323                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3620716                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7212039                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4210993                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4227089                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      8438082                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  34851412248                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  35605867999                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  70457280247                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32909222465                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31498383779                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  64407606244                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   9405033000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   9253843000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18658876000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  25180083991                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  25557110497                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  50737194488                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1372984750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1359653250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2732638000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        24499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        24499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  67760634713                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  67104251778                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 134864886491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  77165667713                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  76358094778                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 153523762491                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2724103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3004117998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5728220998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2593769750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2980348000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5574117750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5317872750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5984465998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11302338748                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032238                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032663                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032451                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014832                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014580                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014706                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.762894                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.756761                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759849                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059686                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058128                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058906                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3493451                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3577376                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7070827                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4080259                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4181502                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      8261761                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  33166863497                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  33981034998                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  67147898495                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25195325118                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  25212990469                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  50408315587                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   8922621248                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   8744886500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17667507748                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  12346009492                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12314345000                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  24660354492                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1340334000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1349733250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2690067250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        73000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        73000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58362188615                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  59194025467                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 117556214082                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  67284809863                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  67938911967                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 135223721830                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2674522248                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3054322749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5728844997                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2557892750                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3016153500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5574046250                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5232414998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6070476249                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11302891247                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031850                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032613                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032232                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014456                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014780                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014618                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754722                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759054                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756914                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.781235                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.792186                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786673                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059900                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059093                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059494                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023953                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024081                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024017                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027935                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027965                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027950                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13760.451596                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13798.852093                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13779.830690                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31087.495244                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30276.252568                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30685.397593                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15177.486404                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15260.974681                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.777808                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12055.040696                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12230.837216                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12141.873909                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        24499                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        24499                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18867.875352                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18533.420400                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18699.966333                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18324.815005                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18063.990320                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18194.153896                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023586                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024141                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023864                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027404                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028067                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.027736                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        73000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1575,6 +795,136 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements         13477112                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.892486                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          842591946                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         13477624                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            62.517840                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      32076200250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.322157                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   270.570329                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471332                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.528458                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999790                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses        869547204                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       869547204                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    420727456                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    421864490                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      842591946                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    420727456                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    421864490                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       842591946                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    420727456                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    421864490                       # number of overall hits
+system.cpu0.icache.overall_hits::total      842591946                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6744207                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      6733422                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     13477629                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6744207                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      6733422                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      13477629                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6744207                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      6733422                       # number of overall misses
+system.cpu0.icache.overall_misses::total     13477629                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  90268756253                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90304288753                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 180573045006                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  90268756253                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  90304288753                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 180573045006                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  90268756253                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  90304288753                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 180573045006                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    427471663                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    428597912                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    856069575                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    427471663                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    428597912                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    856069575                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    427471663                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    428597912                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    856069575                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015777                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015710                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.015744                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015777                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015710                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.015744                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015777                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015710                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.015744                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13384.636067                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13411.351428                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13397.983058                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13397.983058                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13397.983058                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6744207                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6733422                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     13477629                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6744207                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      6733422                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     13477629                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6744207                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      6733422                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     13477629                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  76767439747                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  76823488247                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 153590927994                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  76767439747                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  76823488247                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 153590927994                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  76767439747                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  76823488247                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 153590927994                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2831704500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2831704500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015744                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.015744                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.015744                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11395.990199                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1598,25 +948,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    81731723                       # DTB read hits
-system.cpu1.dtb.read_misses                     99102                       # DTB read misses
-system.cpu1.dtb.write_hits                   74078403                       # DTB write hits
-system.cpu1.dtb.write_misses                    30075                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51867                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    80485889                       # DTB read hits
+system.cpu1.dtb.read_misses                     94650                       # DTB read misses
+system.cpu1.dtb.write_hits                   73083689                       # DTB write hits
+system.cpu1.dtb.write_misses                    28922                       # DTB write misses
+system.cpu1.dtb.flush_tlb                       51788                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              20925                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   72169                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                   69957                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4438                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4240                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9782                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                81830825                       # DTB read accesses
-system.cpu1.dtb.write_accesses               74108478                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9564                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                80580539                       # DTB read accesses
+system.cpu1.dtb.write_accesses               73112611                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        155810126                       # DTB hits
-system.cpu1.dtb.misses                         129177                       # DTB misses
-system.cpu1.dtb.accesses                    155939303                       # DTB accesses
+system.cpu1.dtb.hits                        153569578                       # DTB hits
+system.cpu1.dtb.misses                         123572                       # DTB misses
+system.cpu1.dtb.accesses                    153693150                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1638,224 +988,916 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   434297733                       # ITB inst hits
-system.cpu1.itb.inst_misses                     78021                       # ITB inst misses
+system.cpu1.itb.inst_hits                   428597912                       # ITB inst hits
+system.cpu1.itb.inst_misses                     76336                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51867                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                       51788                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              20925                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   53659                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                   51781                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               434375754                       # ITB inst accesses
-system.cpu1.itb.hits                        434297733                       # DTB hits
-system.cpu1.itb.misses                          78021                       # DTB misses
-system.cpu1.itb.accesses                    434375754                       # DTB accesses
-system.cpu1.numCycles                     51860387727                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               428674248                       # ITB inst accesses
+system.cpu1.itb.hits                        428597912                       # DTB hits
+system.cpu1.itb.misses                          76336                       # DTB misses
+system.cpu1.itb.accesses                    428674248                       # DTB accesses
+system.cpu1.numCycles                     51781450270                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  434015512                       # Number of instructions committed
-system.cpu1.committedOps                    509975199                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            468434913                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                458508                       # Number of float alu accesses
-system.cpu1.num_func_calls                   25828963                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     66119194                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   468434913                       # number of integer instructions
-system.cpu1.num_fp_insts                       458508                       # number of float instructions
-system.cpu1.num_int_register_reads          681011171                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         371474138                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              735722                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             396908                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           113358693                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          113081851                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    155802990                       # number of memory refs
-system.cpu1.num_load_insts                   81728236                       # Number of load instructions
-system.cpu1.num_store_insts                  74074754                       # Number of store instructions
-system.cpu1.num_idle_cycles              50263670387.895683                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1596717339.104316                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030789                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969211                       # Percentage of idle cycles
-system.cpu1.Branches                         96920557                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                353254188     69.23%     69.23% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1106936      0.22%     69.45% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    48650      0.01%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             58473      0.01%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::MemRead                81728236     16.02%     85.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite               74074754     14.52%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                  428322492                       # Number of instructions committed
+system.cpu1.committedOps                    503238558                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            462373470                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                457847                       # Number of float alu accesses
+system.cpu1.num_func_calls                   25589000                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     65138542                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   462373470                       # number of integer instructions
+system.cpu1.num_fp_insts                       457847                       # number of float instructions
+system.cpu1.num_int_register_reads          672243876                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         366665103                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              741025                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             381476                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           111687570                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          111401234                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    153562143                       # number of memory refs
+system.cpu1.num_load_insts                   80482788                       # Number of load instructions
+system.cpu1.num_store_insts                  73079355                       # Number of store instructions
+system.cpu1.num_idle_cycles              50246687172.676186                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1534763097.323812                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029639                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970361                       # Percentage of idle cycles
+system.cpu1.Branches                         95580848                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                348749586     69.26%     69.26% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1110324      0.22%     69.48% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    49704      0.01%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  2      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  8      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 12      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             56056      0.01%     69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
+system.cpu1.op_class::MemRead                80482788     15.98%     85.49% # Class of executed instruction
+system.cpu1.op_class::MemWrite               73079355     14.51%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 510271279                       # Class of executed instruction
+system.cpu1.op_class::total                 503527836                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iocache.tags.replacements               115483                       # number of replacements
-system.iocache.tags.tagsinuse               10.461502                       # Cycle average of tags in use
+system.iobus.trans_dist::ReadReq                40424                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40424                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354314                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7493014                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042410724                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
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 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
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 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13154061165000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.844281                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.617221                       # Average occupied blocks per requestor
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 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
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-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
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 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
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-system.iocache.ReadReq_misses::total             8874                       # number of ReadReq misses
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 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
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-system.iocache.ReadReq_miss_latency::realview.ide   1908690112                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1914175112                       # number of ReadReq miss cycles
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 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
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-system.iocache.ReadReq_accesses::total           8874                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
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-system.iocache.demand_accesses::total            8877                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8837                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8877                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
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 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
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-system.iocache.WriteInvalidateReq_miss_rate::total     0.000047                       # miss rate for WriteInvalidateReq accesses
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 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::realview.ide 215988.470295                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 215706.007663                       # average ReadReq miss latency
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 215755.594379                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 215988.470295                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 215671.297961                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 215988.470295                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 215671.297961                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         51929                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 215720.949876                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 215720.949876                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        223529                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27514                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.458834                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.124191                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8837                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8874                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8858                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8895                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
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+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8837                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8877                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8858                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8837                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8877                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1449081112                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1452642112                       # number of ReadReq MSHR miss cycles
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+system.iocache.overall_mshr_misses::total         8898                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3555000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1452961512                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1456516512                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6526726956                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6526726956                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1449081112                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1452825112                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1449081112                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1452825112                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3738000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1452961512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1456699512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3738000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1452961512                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1456699512                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163978.851646                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 163696.429119                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164028.167984                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 163745.532546                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 163978.851646                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 163661.722654                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 163978.851646                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 163661.722654                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218311.637338                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218311.637338                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1132290                       # number of replacements
+system.l2c.tags.tagsinuse                65332.905134                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   26887895                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1194294                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    22.513631                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               6379783000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   38092.537924                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   152.896952                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   229.074218                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2954.015231                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9873.444708                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.350600                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   215.925176                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4167.527871                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9496.132455                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.581246                       # Average percentage of cache occupancy
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784775                       # miss rate for UpgradeReq accesses
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+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78278.750826                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79706.790123                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74342.471346                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 74796.530151                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74753.947123                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78250.298507                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80710.674157                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 74300.843370                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 74723.623204                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78278.750826                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79706.790123                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74342.471346                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 74796.530151                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74753.947123                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks              962855                       # number of writebacks
+system.l2c.writebacks::total                   962855                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1675                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1602                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        36219                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       126965                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         1513                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1620                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst        38912                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data       123410                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          331916                       # number of ReadReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       247597                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       246465                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::total       494062                       # number of WriteInvalidateReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        17085                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        16773                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        33858                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       201754                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       196780                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        398534                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1675                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1602                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        36219                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       328719                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         1513                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         1620                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        38912                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       320190                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           730450                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1675                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1602                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        36219                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       328719                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         1513                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         1620                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        38912                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       320190                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          730450                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2232246754                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8054556756                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2399864755                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data   7845308002                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  20959851267                       # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data   5354998508                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   5322652000                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total  10677650508                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    170934584                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    167796772                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    338731356                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        60000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        60000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  12329683548                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  12037605009                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  24367288557                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   2232246754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  20384240304                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   2399864755                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  19882913011                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  45327139824                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2232246754                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  20384240304                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   2399864755                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  19882913011                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  45327139824                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2468159752                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2821001751                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   7538131503                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2382381500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2784161000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5166542500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4850541252                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5605162751                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12704674003                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.039999                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.037944                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016054                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.403995                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.402045                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.403019                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781743                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784775                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.783242                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.202662                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.193086                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.197818                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.078835                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.074958                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.032192                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.078835                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.074958                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.032192                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63439.189981                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63571.088259                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63148.059349                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21627.881226                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21595.975088                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21611.964709                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.950776                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.980922                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.470317                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        60000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61112.461453                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61172.908878                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61142.307951                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62011.141139                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62097.232927                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 62053.720068                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62011.141139                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62097.232927                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 62053.720068                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              417721                       # Transaction distribution
+system.membus.trans_dist::ReadResp             417721                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33871                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33871                       # Transaction distribution
+system.membus.trans_dist::Writeback           1069486                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       600721                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       600721                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34423                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34424                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            397977                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           397977                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3570318                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3700502                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       334782                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       334782                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4035284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    140106848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    140277172                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14030080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14030080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               154307252                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3630                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2443419                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2443419    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2443419                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           107392500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5575997                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         16318205493                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         7697194309                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186789727                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq           21137473                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          21129474                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33871                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33871                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          7479557                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1332565                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1225901                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           43231                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          43232                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2014651                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2014651                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     27041508                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27036574                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       774452                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1144323                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              55996857                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    862740756                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1097639072                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2601008                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3569856                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             1966550692                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          492520                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         31930568                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003619                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.060051                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               31815006     99.64%     99.64% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115562      0.36%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           31930568                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        50801737999                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy          4033500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy       60715950506                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy       38798201181                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         449711000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         698488000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 2703d8c6d..d01497065 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,135 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.125902                       # Number of seconds simulated
-sim_ticks                                5125902116500                       # Number of ticks simulated
-final_tick                               5125902116500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.125918                       # Number of seconds simulated
+sim_ticks                                5125917808500                       # Number of ticks simulated
+final_tick                               5125917808500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 226565                       # Simulator instruction rate (inst/s)
-host_op_rate                                   447853                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2846393388                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 748824                       # Number of bytes of host memory used
-host_seconds                                  1800.84                       # Real time elapsed on the host
-sim_insts                                   408006726                       # Number of instructions simulated
-sim_ops                                     806511598                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 163224                       # Simulator instruction rate (inst/s)
+host_op_rate                                   322646                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2051147218                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 753920                       # Number of bytes of host memory used
+host_seconds                                  2499.05                       # Real time elapsed on the host
+sim_insts                                   407905794                       # Number of instructions simulated
+sim_ops                                     806307064                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1043840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10813760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1044736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10779456                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11891200                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1043840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1043840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6604544                       # Number of bytes written to this memory
-system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9594624                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           75                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16310                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168965                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11857920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1044736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1044736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9592896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9592896                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           78                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16324                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168429                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185800                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          103196                       # Number of write requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149916                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            936                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               203640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2109631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                185280                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149889                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149889                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               203814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2102932                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2319826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203640                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203640                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1288465                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       583328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1871792                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1288465                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           936                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2109631                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       588859                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4191618                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185800                       # Number of read requests accepted
-system.physmem.writeReqs                       149916                       # Number of write requests accepted
-system.physmem.readBursts                      185800                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149916                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11876224                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     14976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9592960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11891200                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9594624                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      234                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1736                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11489                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10946                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11982                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11463                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11671                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11298                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11252                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11687                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11071                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11217                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11355                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12125                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11861                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12651                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12184                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11314                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9710                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9082                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8978                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8996                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9462                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9601                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9097                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8837                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9327                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9159                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9532                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9463                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9618                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9862                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9881                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9285                       # Per bank write bursts
+system.physmem.bw_read::total                 2313326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          203814                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             203814                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1871449                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1871449                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1871449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              203814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2102932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5531                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4184776                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185280                       # Number of read requests accepted
+system.physmem.writeReqs                       196609                       # Number of write requests accepted
+system.physmem.readBursts                      185280                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     196609                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11848512                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  12427072                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11857920                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               12582976                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2411                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           1705                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11356                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10792                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11765                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11427                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11775                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11293                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11205                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11692                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11087                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11285                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11605                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              12031                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11880                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12674                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11994                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11272                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               13000                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               12435                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               11147                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               11517                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               12452                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               12346                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11719                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               11239                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               12215                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               12097                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              12764                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              12134                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              12379                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              12264                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              12219                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              12246                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5125902065000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5125917756500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185800                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185280                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149916                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    170703                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12067                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2038                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 196609                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170576                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11800                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2009                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       409                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -159,296 +156,320 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     8527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    10246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9929                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        72846                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.719271                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.256286                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     318.919065                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          28471     39.08%     39.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17446     23.95%     63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7310     10.03%     73.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4243      5.82%     78.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2987      4.10%     82.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1984      2.72%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1403      1.93%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1126      1.55%     89.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7876     10.81%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          72846                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7377                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.152094                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      560.212559                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7376     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     9692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    11040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    11520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    12479                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22                    14075                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    13662                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::25                    13150                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28                    10547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8969                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8463                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        74985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      323.738348                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     187.730188                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.091209                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27875     37.17%     37.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17344     23.13%     60.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7346      9.80%     70.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4205      5.61%     75.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3044      4.06%     79.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1991      2.66%     82.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1466      1.96%     84.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1106      1.47%     85.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10608     14.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          74985                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7802                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.727634                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      544.765031                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7801     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7377                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7377                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.318558                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.615023                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.539295                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6330     85.81%     85.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              64      0.87%     86.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              33      0.45%     87.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             268      3.63%     90.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             287      3.89%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              24      0.33%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              24      0.33%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              16      0.22%     95.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              20      0.27%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.03%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.08%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.03%     95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             237      3.21%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.04%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.03%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.04%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              11      0.15%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              12      0.16%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.04%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             6      0.08%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.18%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7377                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2068154250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5547516750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    927830000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11145.11                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7802                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7802                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.887593                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.377135                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.103132                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6364     81.57%     81.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              53      0.68%     82.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              22      0.28%     82.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             275      3.52%     86.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             179      2.29%     88.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              53      0.68%     89.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              27      0.35%     89.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              51      0.65%     90.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             164      2.10%     92.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.22%     92.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              13      0.17%     92.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.18%     92.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              32      0.41%     93.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              25      0.32%     93.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.09%     93.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              50      0.64%     94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             101      1.29%     95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.04%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               9      0.12%     95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              29      0.37%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             150      1.92%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             8      0.10%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             7      0.09%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             3      0.04%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            28      0.36%     98.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.05%     98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            11      0.14%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             4      0.05%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            23      0.29%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             7      0.09%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.04%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            14      0.18%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            10      0.13%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             9      0.12%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             4      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.01%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             3      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7802                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2011030750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5482274500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    925665000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10862.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29895.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.32                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29612.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.42                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.45                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     151753                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110856                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.78                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15268566.48                       # Average gap between requests
-system.physmem.pageHitRate                      78.28                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4919748958000                       # Time in different power states
-system.physmem.memoryStateTime::REF      171165020000                       # Time in different power states
+system.physmem.avgWrQLen                        21.38                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     151985                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    152335                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13422533.14                       # Average gap between requests
+system.physmem.pageHitRate                      80.23                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4919402035500                       # Time in different power states
+system.physmem.memoryStateTime::REF      171165540000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       34988035500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       35350129500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 267185520                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 283530240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 145785750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 154704000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                715946400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                731460600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               477984240                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               493302960                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          334798779120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          334798779120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          129305495790                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          129519356940                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2962113436500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2961925839000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3427824613320                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3427906972860                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.726542                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.742609                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                86911006                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86911006                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            901724                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80066722                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78189070                       # Number of BTB hits
+system.physmem.actEnergy::0                 274957200                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 291929400                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 150026250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 159286875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                712179000                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                731850600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               621140400                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               637100640                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          334799796240                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          334799796240                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          129444240060                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          129652397505                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          2962001074500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2961818480250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3428003413650                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3428090841510                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.759392                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.776448                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                86891854                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86891854                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            902474                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80057154                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78172464                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.654891                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1556278                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             178526                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.645819                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1556145                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             178539                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449563158                       # number of cpu cycles simulated
+system.cpu.numCycles                        449528542                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27553144                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      429142218                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86911006                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79745348                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     417985667                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1891240                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     143316                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                50930                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        210883                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       127962                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          502                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9183903                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                446388                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4881                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          447018024                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.894555                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.051977                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27579139                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429063602                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86891854                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79728609                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417924990                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1892404                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     141641                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                49747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        210937                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       127048                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          749                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9185584                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                447344                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4767                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          446980453                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.894336                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051866                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                281457902     62.96%     62.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2285728      0.51%     63.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72178245     16.15%     79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1597297      0.36%     79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2150673      0.48%     80.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2329203      0.52%     80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1531441      0.34%     81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1871505      0.42%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81616030     18.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281454432     62.97%     62.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2285018      0.51%     63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72162718     16.14%     79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1595292      0.36%     79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2151182      0.48%     80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2328836      0.52%     80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1532887      0.34%     81.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1872269      0.42%     81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81597819     18.26%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            447018024                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.193323                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.954576                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22975502                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             264891753                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150781344                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7423805                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 945620                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              838588132                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 945620                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25820685                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               223318475                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       13301995                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154670533                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              28960716                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              835102889                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                477440                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12397064                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 181319                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               13705397                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           997542850                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1813799502                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1115056777                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               257                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964533940                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 33008908                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             469072                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         473209                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  39003947                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17327064                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10187947                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1305152                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1075480                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  829577990                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1211603                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 824337264                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            238496                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23343623                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     36066469                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         155814                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     447018024                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.844081                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.418172                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            446980453                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193296                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.954475                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23006879                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264875775                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150713064                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7438533                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 946202                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              838427175                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 946202                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25861517                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               223289477                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13277674                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154607234                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              28998349                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              834936902                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                476513                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12412504                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 177326                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               13726812                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           997336716                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1813473834                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114859292                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               146                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964283425                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 33053286                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             468997                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         473016                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  39075310                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17327574                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10191135                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1313699                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1076527                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  829405798                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1211413                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 824144334                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            238741                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23374016                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     36157635                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         155810                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     446980453                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.843804                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418028                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           262761301     58.78%     58.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13855312      3.10%     61.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10080747      2.26%     64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6920313      1.55%     65.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74355494     16.63%     82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4460811      1.00%     83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72820656     16.29%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1197568      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              565822      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262751782     58.78%     58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13860127      3.10%     61.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10088289      2.26%     64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6929216      1.55%     65.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74323701     16.63%     82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4464363      1.00%     83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72802131     16.29%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1196176      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              564668      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       447018024                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       446980453                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1976611     71.80%     71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    212      0.01%     71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                    1052      0.04%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 614146     22.31%     94.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                161054      5.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1984017     71.87%     71.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    212      0.01%     71.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                    1649      0.06%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 613790     22.24%     94.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                160788      5.82%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            292817      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795957789     96.56%     96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150640      0.02%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                125262      0.02%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            292283      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795766200     96.56%     96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150572      0.02%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125282      0.02%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   8      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
@@ -472,98 +493,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18413325      2.23%     98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9397431      1.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18411850      2.23%     98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9398139      1.14%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              824337264                       # Type of FU issued
-system.cpu.iq.rate                           1.833641                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2753075                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003340                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2098683906                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         854145561                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819784123                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 216                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                406                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           61                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826797420                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     102                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1878905                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              824144334                       # Type of FU issued
+system.cpu.iq.rate                           1.833353                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2760456                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003349                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2098268090                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         854003641                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819590055                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 227                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                270                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           62                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826612402                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     105                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1877597                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3325392                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14284                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14518                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1760345                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3329866                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14364                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14470                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1763076                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2224613                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         71287                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2224552                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         71468                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 945620                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               205593402                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9425350                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830789593                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            184731                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17327064                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10187947                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             714327                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 416093                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8107674                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14518                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         515540                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       536896                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1052436                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822725796                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              18017825                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1477348                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 946202                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               205595274                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9411486                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830617211                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            184433                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17327584                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10191135                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             714161                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 416193                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8093117                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14470                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         516905                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       536436                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1053341                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822534076                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              18016449                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1476395                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27187593                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83308581                       # Number of branches executed
-system.cpu.iew.exec_stores                    9169768                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.830056                       # Inst execution rate
-system.cpu.iew.wb_sent                      822221777                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819784184                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 641108962                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1050701242                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27187129                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83286990                       # Number of branches executed
+system.cpu.iew.exec_stores                    9170680                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.829771                       # Inst execution rate
+system.cpu.iew.wb_sent                      822027813                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819590117                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640953314                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1050450596                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.823513                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610172                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.823222                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610170                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        24183935                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1055789                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            913678                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443381671                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.819001                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.675688                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        24215626                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1055602                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            914308                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443339838                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.818711                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.675515                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272578077     61.48%     61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11201647      2.53%     64.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3542666      0.80%     64.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74562549     16.82%     81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2432578      0.55%     82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1609465      0.36%     82.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       914477      0.21%     82.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71049223     16.02%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5490989      1.24%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272569121     61.48%     61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11207092      2.53%     64.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3543073      0.80%     64.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74545535     16.81%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2433206      0.55%     82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1610406      0.36%     82.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       913346      0.21%     82.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71032181     16.02%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5485878      1.24%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443381671                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            408006726                       # Number of instructions committed
-system.cpu.commit.committedOps              806511598                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443339838                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407905794                       # Number of instructions committed
+system.cpu.commit.committedOps              806307064                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22429273                       # Number of memory references committed
-system.cpu.commit.loads                      14001671                       # Number of loads committed
-system.cpu.commit.membars                      475333                       # Number of memory barriers committed
-system.cpu.commit.branches                   82207365                       # Number of branches committed
+system.cpu.commit.refs                       22425775                       # Number of memory references committed
+system.cpu.commit.loads                      13997716                       # Number of loads committed
+system.cpu.commit.membars                      475203                       # Number of memory barriers committed
+system.cpu.commit.branches                   82185787                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735317995                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155841                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       174216      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783641693     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144853      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121563      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735131032                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155610                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       174231      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783440615     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144913      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121530      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
@@ -590,167 +611,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        14001671      1.74%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8427602      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13997716      1.74%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8428059      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806511598                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5490989                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         806307064                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5485878                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1268507964                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1665044622                       # The number of ROB writes
-system.cpu.timesIdled                          294262                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2545134                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9802241311                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   408006726                       # Number of Instructions Simulated
-system.cpu.committedOps                     806511598                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.101852                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.101852                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907563                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907563                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1092659743                       # number of integer regfile reads
-system.cpu.int_regfile_writes               656162059                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        61                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416306470                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                322125902                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265627452                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402647                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1657683                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996297                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19131015                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1658195                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.537253                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   1268298437                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1664703185                       # The number of ROB writes
+system.cpu.timesIdled                          295137                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2548089                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9802307300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407905794                       # Number of Instructions Simulated
+system.cpu.committedOps                     806307064                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.102040                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.102040                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907408                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907408                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1092406866                       # number of integer regfile reads
+system.cpu.int_regfile_writes               656005719                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        62                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416194474                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                322040205                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265569258                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402671                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1659070                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.990007                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19130419                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1659582                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.527251                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996297                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.990007                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999980                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999980                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          203                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88314142                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88314142                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10979297                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10979297                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8084679                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8084679                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64358                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64358                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19063976                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19063976                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19128334                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19128334                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1796007                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1796007                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       333248                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       333248                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406393                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406393                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2129255                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2129255                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2535648                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2535648                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26565336178                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26565336178                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12842853467                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12842853467                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39408189645                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39408189645                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39408189645                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39408189645                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12775304                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12775304                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8417927                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8417927                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470751                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470751                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21193231                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21193231                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21663982                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21663982                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140584                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.140584                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039588                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039588                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863287                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.863287                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100469                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100469                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117044                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117044                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18507.970931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15541.664160                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       378856                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88317394                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88317394                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10978879                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10978879                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8084521                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8084521                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        64338                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         64338                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19063400                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19063400                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19127738                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19127738                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1796470                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1796470                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       333911                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       333911                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406328                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406328                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2130381                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2130381                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2536709                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2536709                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26526077953                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26526077953                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12856931699                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12856931699                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39383009652                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39383009652                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39383009652                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39383009652                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12775349                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12775349                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8418432                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8418432                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       470666                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       470666                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21193781                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21193781                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21664447                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21664447                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140620                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.140620                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039664                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039664                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863304                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.863304                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100519                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100519                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117091                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117091                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18486.369176                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18486.369176                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15525.237484                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15525.237484                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       375690                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             39922                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             39932                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.489905                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.408244                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1559289                       # number of writebacks
-system.cpu.dcache.writebacks::total           1559289                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       827651                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       827651                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44088                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44088                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       871739                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       871739                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       871739                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       871739                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       968356                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       968356                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289160                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289160                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402927                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402927                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1257516                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1257516                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1660443                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1660443                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12252685521                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12252685521                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11181268784                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11181268784                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5616168251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5616168251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23433954305                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23433954305                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29050122556                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29050122556                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97390324000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97390324000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2564320000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2564320000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99954644000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99954644000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075799                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075799                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034350                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034350                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855924                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855924                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059336                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059336                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076645                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076645                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1560667                       # number of writebacks
+system.cpu.dcache.writebacks::total           1560667                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       827312                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       827312                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44114                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44114                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       871426                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       871426                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       871426                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       871426                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       969158                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       969158                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289797                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289797                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402869                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402869                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1258955                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1258955                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1661824                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1661824                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12253110515                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12253110515                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11193391556                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11193391556                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5590029250                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5590029250                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23446502071                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23446502071                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29036531321                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29036531321                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97386643000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97386643000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2557063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2557063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99943706000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99943706000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075862                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075862                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034424                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034424                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855955                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855955                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059402                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059402                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076707                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076707                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -758,58 +779,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        74377                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.812457                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       116780                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        74392                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.569792                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.replacements        73854                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.812426                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       117340                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        73869                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.588488                       # Average number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.812457                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988279                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988279                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.812426                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988277                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988277                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       459926                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       459926                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       116782                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       116782                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       116782                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       116782                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       116782                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       116782                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        75454                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        75454                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        75454                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        75454                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        75454                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        75454                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    927232955                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    927232955                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    927232955                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    927232955                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    927232955                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    927232955                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192236                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       192236                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192236                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       192236                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192236                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       192236                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.392507                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.392507                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.392507                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       459584                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       459584                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       117385                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       117385                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       117385                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       117385                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       117385                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       117385                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74938                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        74938                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74938                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        74938                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74938                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        74938                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    912423463                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    912423463                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    912423463                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    912423463                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    912423463                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    912423463                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192323                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       192323                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192323                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       192323                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192323                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       192323                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.389647                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.389647                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.389647                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -818,180 +839,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        21876                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        21876                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        75454                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        75454                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        75454                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        75454                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        75454                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        75454                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    776178235                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    776178235                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    776178235                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.392507                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.392507                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.392507                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        19615                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        19615                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74938                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74938                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74938                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        74938                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74938                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        74938                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    762426693                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    762426693                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    762426693                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.389647                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.389647                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.389647                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10174.099829                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            994393                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.035216                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8125717                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            994905                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.167330                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            996223                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.034964                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8125334                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            996735                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.151950                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      147627648000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.035216                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996163                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996163                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.034964                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          141                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10178850                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10178850                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8125717                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8125717                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8125717                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8125717                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8125717                       # number of overall hits
-system.cpu.icache.overall_hits::total         8125717                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1058185                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1058185                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1058185                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1058185                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1058185                       # number of overall misses
-system.cpu.icache.overall_misses::total       1058185                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14693875503                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14693875503                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14693875503                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14693875503                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14693875503                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14693875503                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9183902                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9183902                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9183902                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9183902                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9183902                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9183902                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115222                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.115222                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.115222                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.115222                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.115222                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.115222                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13885.923069                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13885.923069                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7023                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10182364                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10182364                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8125334                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8125334                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8125334                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::cpu.inst      8125334                       # number of overall hits
+system.cpu.icache.overall_hits::total         8125334                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1060246                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1060246                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst      1060246                       # number of overall misses
+system.cpu.icache.overall_misses::total       1060246                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14710988702                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14710988702                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14710988702                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14710988702                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14710988702                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14710988702                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9185580                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9185580                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9185580                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9185580                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9185580                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9185580                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115425                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115425                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115425                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115425                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115425                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115425                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13875.071165                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13875.071165                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8852                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               297                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.646465                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    29.408638                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63237                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        63237                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        63237                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        63237                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        63237                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        63237                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       994948                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       994948                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       994948                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       994948                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       994948                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       994948                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12059629101                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12059629101                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12059629101                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12059629101                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12059629101                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12059629101                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108336                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108336                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108336                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63462                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        63462                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        63462                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        63462                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total        63462                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       996784                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       996784                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       996784                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total       996784                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12075236643                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12075236643                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12075236643                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12075236643                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12075236643                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12075236643                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108516                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108516                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108516                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12114.195897                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        14092                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.014059                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        26262                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        14107                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.861629                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.014059                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375879                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.375879                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements        13757                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.017843                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26179                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13772                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.900886                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.017843                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376115                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.376115                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        97491                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        97491                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26263                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26263                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        96280                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        96280                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26178                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        26178                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26265                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26265                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26265                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26265                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14987                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        14987                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14987                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        14987                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14987                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        14987                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    174073497                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    174073497                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    174073497                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    174073497                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    174073497                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    174073497                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41250                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        41250                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26180                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        26180                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26180                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        26180                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14640                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14640                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14640                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14640                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14640                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14640                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    168910997                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    168910997                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    168910997                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    168910997                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    168910997                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    168910997                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40818                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        40818                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41252                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        41252                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41252                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        41252                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.363321                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.363321                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.363304                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.363304                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.363304                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.363304                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40820                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        40820                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40820                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        40820                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358665                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358665                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358648                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.358648                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358648                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.358648                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11537.636407                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1000,177 +1021,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3303                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3303                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14987                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14987                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14987                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        14987                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14987                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        14987                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    144083525                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    144083525                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    144083525                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    144083525                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    144083525                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    144083525                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.363321                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.363321                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.363304                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.363304                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.363304                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.363304                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9613.900380                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9613.900380                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9613.900380                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         3000                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         3000                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14640                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14640                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14640                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14640                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14640                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14640                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    139618019                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    139618019                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    139618019                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    139618019                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    139618019                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    139618019                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358665                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358665                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358648                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358648                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9536.749932                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           113085                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64818.383323                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3831425                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176970                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.650138                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           113048                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64817.930454                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3838289                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           177093                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.673861                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    22.760500                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.143343                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3264.453296                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.769536                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50426.330308                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    22.730844                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.138507                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3266.844648                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.769445                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000347                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049812                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.169353                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989050                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63885                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          634                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3305                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5793                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54091                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974808                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         35031209                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        35031209                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68532                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12501                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        2394205                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1584468                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1584468                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       153669                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001093                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016396                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823731                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        86780                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951                       # average ReadReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        86780                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        86780                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732                       # average overall miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12164.793750                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12164.793750                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69809.607301                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69809.607301                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83391.025641                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78666.666667                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76529.967536                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71844.537926                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72261.321474                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83391.025641                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78666.666667                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76529.967536                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71844.537926                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72261.321474                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1179,99 +1200,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103196                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103196                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       103222                       # number of writebacks
+system.cpu.l2cache.writebacks::total           103222                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           75                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16310                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35874                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        52266                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1444                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1444                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133393                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133393                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           75                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           75                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16310                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       473000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1049198000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2439336749                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3494586749                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14472940                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14472940                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7638617543                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       473000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1049198000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10077954292                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11133204292                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       473000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1049198000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10077954292                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11133204292                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89275584000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89275584000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2397149000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2397149000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91672733000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91672733000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026176                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021364                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823731                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823731                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464684                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464684                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102118                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067919                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102118                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067919                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571                       # average overall mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89272220000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89272220000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2390455500                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91662675500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91662675500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819113                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819113                       # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102099                       # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67021.734201                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66081.951717                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10672.514583                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10672.514583                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57252.964800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57252.964800                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average overall mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
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 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1279,62 +1300,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3066870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3066328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1584468                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46724                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           10                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1989808                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126047                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        30798                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       165937                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8312590                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63671040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207694139                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1011904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5790912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278167995                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       58568                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4377947                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.010880                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103740                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        3068576                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3068035                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13841                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13841                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1583282                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2219                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2219                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287706                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287706                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1993478                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6130100                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29738                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       161735                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8315051                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63788416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207873825                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       966272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5555008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278183521                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       59487                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4379111                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.010877                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103722                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4330313     98.91%     98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47634      1.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            4331481     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47630      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4377947                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4068281890                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4379111                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4067623882                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       567000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       571500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1496480643                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1499268850                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3139987945                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3141964932                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      22488486                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      21966489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     113254360                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     112467385                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               225681                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225681                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57721                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57721                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               225657                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225657                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57676                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              10956                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1641                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1641                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
@@ -1350,15 +1372,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       471544                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       471406                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  570092                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3282                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3282                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  569948                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
@@ -1374,19 +1396,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       242058                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       241980                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3276458                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3917656                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3276368                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3911656                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1416,44 +1438,46 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           422009356                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           448438152                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           460543000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           460450000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52362257                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52358513                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1644000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1641000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                47575                       # number of replacements
-system.iocache.tags.tagsinuse                0.091458                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.091509                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992976867000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091458                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005716                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005716                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992976927000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091509                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005719                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005719                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
 system.iocache.tags.data_accesses              428670                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::pc.south_bridge.ide          910                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               910                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          910                       # number of overall misses
 system.iocache.overall_misses::total              910                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    152161446                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    152161446                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    152161446                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    152161446                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    152161446                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    152161446                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151600663                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    151600663                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12348426976                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  12348426976                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    151600663                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    151600663                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    151600663                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    151600663                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1464,117 +1488,127 @@ system.iocache.overall_accesses::pc.south_bridge.ide          910
 system.iocache.overall_accesses::total            910                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167210.380220                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167210.380220                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167210.380220                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           308                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166594.135165                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 166594.135165                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 166594.135165                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         70653                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   26                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9154                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.846154                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.718265                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      46720                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::pc.south_bridge.ide          910                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          910                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          910                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    104814946                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2846577667                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2846577667                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    104814946                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    104814946                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    104259663                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    104259663                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    104259663                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115181.259341                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115181.259341                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              662592                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662582                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13889                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13889                       # Transaction distribution
-system.membus.trans_dist::Writeback            103196                       # Transaction distribution
+system.membus.trans_dist::ReadReq              662598                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662586                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13841                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13841                       # Transaction distribution
+system.membus.trans_dist::Writeback            149889                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2215                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1736                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133104                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133101                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           10                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471544                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           20                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1724494                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94793                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94793                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1822575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242058                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550129                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18467392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20259579                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23284587                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              949                       # Total snoops (count)
-system.membus.snoop_fanout::samples            338415                       # Request fanout histogram
+system.membus.trans_dist::UpgradeReq             2184                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1723                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133213                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133211                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1641                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1641                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3282                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3282                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471406                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775060                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723935                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141460                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141460                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1868677                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241980                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550117                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18435776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20227873                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                26239557                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1606                       # Total snoops (count)
+system.membus.snoop_fanout::samples            385212                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  338415    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  385212    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              338415                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           251687000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              385212                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           251510000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583226500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583228000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3288000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3282000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1575195000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1995467500                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               13500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               16000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1644000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1641000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3157657266                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3158524545                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           54931743                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54933487                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 443c7ed9f..1dbb00ab9 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,159 +1,152 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.137752                       # Number of seconds simulated
-sim_ticks                                5137751757500                       # Number of ticks simulated
-final_tick                               5137751757500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.133759                       # Number of seconds simulated
+sim_ticks                                5133759356500                       # Number of ticks simulated
+final_tick                               5133759356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 338442                       # Simulator instruction rate (inst/s)
-host_op_rate                                   672864                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7140802707                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 935656                       # Number of bytes of host memory used
-host_seconds                                   719.49                       # Real time elapsed on the host
-sim_insts                                   243506025                       # Number of instructions simulated
-sim_ops                                     484120527                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 270712                       # Simulator instruction rate (inst/s)
+host_op_rate                                   538208                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5706161187                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 956212                       # Number of bytes of host memory used
+host_seconds                                   899.69                       # Real time elapsed on the host
+sim_insts                                   243556000                       # Number of instructions simulated
+sim_ops                                     484219202                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           475328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5564736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           130048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2113344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           362880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2752000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           473664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5506752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           151296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1916928                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         2560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           343744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2959424                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11429696                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       475328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       130048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       362880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          968256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6180416                       # Number of bytes written to this memory
-system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9170496                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7427                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             86949                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             33021                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           42                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             43000                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11383040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       473664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       151296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       343744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          968704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9167488                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9167488                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              7401                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             86043                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2364                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             29952                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           40                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5371                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             46241                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                178589                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96569                       # Number of write requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143289                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               92517                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1083107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               25312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              411336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               70630                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              535643                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2224649                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          92517                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          25312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          70630                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             188459                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1202942                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       581982                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1784924                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1202942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              92517                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1083107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              25312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             411336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              70630                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             535643                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       587501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4009573                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         84209                       # Number of read requests accepted
-system.physmem.writeReqs                        74716                       # Number of write requests accepted
-system.physmem.readBursts                       84209                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      74716                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5376960                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     12416                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4781824                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5389376                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4781824                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      194                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            805                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5309                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4164                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4421                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5747                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5625                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4848                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4889                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                4803                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5153                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5288                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4847                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5280                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5573                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6540                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6055                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5473                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4689                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                3818                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                3922                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4862                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4936                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4229                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4848                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4482                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4577                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4853                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4451                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4689                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4903                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5464                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5149                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4844                       # Per bank write bursts
+system.physmem.num_reads::total                177860                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143242                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143242                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               92265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1072655                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               29471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              373397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           499                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               66958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              576463                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2217291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          92265                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          29471                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          66958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             188693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1785726                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1785726                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1785726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              92265                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1072655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              29471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             373397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          499                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              66958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             576463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5523                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4003017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         84411                       # Number of read requests accepted
+system.physmem.writeReqs                       105225                       # Number of write requests accepted
+system.physmem.readBursts                       84411                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     105225                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5391616                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10688                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6646720                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5402304                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6734400                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      167                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1370                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            877                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5556                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4342                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4498                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5943                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5610                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4878                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                4789                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                4605                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5348                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5424                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               4968                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5291                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5168                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6289                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5888                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5647                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6974                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5943                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5537                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6451                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6503                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5766                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6233                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6363                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6662                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6738                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7192                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7225                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6202                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7261                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6520                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6285                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5136577016500                       # Total gap between requests
+system.physmem.totGap                    5132576110500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   84209                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   84411                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  74716                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     79815                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      3315                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       428                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 105225                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     78589                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4433                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       775                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -169,445 +162,449 @@ system.physmem.rdQLenPdf::29                        0                       # Wh
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                       123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     3849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6913                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5783                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        37237                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      272.814244                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.615678                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     301.614315                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15278     41.03%     41.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9118     24.49%     65.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3769     10.12%     75.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2135      5.73%     81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1492      4.01%     85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          936      2.51%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          657      1.76%     89.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          562      1.51%     91.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3290      8.84%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          37237                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3726                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.548309                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      194.901220                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3723     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            1      0.03%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-6143            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3726                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3726                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.052603                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.849959                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.299765                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                61      1.64%      1.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 9      0.24%      1.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.03%      1.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               4      0.11%      2.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3105     83.33%     85.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              37      0.99%     86.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              24      0.64%     86.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             154      4.13%     91.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             145      3.89%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               6      0.16%     95.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              11      0.30%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.05%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              14      0.38%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.11%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.03%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             119      3.19%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.13%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.03%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.03%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.16%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               4      0.11%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.03%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.24%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3726                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      920887750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2496169000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    420075000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10960.99                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        39329                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      306.093112                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.896548                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.057147                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15327     38.97%     38.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9261     23.55%     62.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3835      9.75%     72.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2116      5.38%     77.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1579      4.01%     81.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          961      2.44%     84.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          670      1.70%     85.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          553      1.41%     87.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5027     12.78%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39329                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4061                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.744644                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      186.795472                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            4058     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5632-6143            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4061                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4061                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.573750                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.065998                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       25.155630                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                71      1.75%      1.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15                7      0.17%      1.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            3181     78.33%     80.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             170      4.19%     84.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             129      3.18%     87.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              48      1.18%     88.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             114      2.81%     91.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              18      0.44%     92.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              31      0.76%     92.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              38      0.94%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              54      1.33%     95.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              16      0.39%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             98      2.41%     97.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             9      0.22%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            19      0.47%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             5      0.12%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            15      0.37%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             3      0.07%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            11      0.27%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             4      0.10%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.10%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             3      0.07%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             4      0.10%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.05%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4061                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      954764500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2534339500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    421220000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11333.32                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29710.99                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30083.32                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.93                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.29                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.93                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        12.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      66918                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     54576                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                     32320761.47                       # Average gap between requests
-system.physmem.pageHitRate                      76.54                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4942660463000                       # Time in different power states
-system.physmem.memoryStateTime::REF      171560740000                       # Time in different power states
+system.physmem.readRowHits                      67051                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81719                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.59                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                     27065410.10                       # Average gap between requests
+system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4938610465000                       # Time in different power states
+system.physmem.memoryStateTime::REF      171427360000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       23528333250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       23717365000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 135618840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 145892880                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  73998375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  79604250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                310486800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                344830200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               231893280                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               252266400                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          335572807440                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          335572807440                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          122729524065                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          123386936985                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2974992236250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2974415558250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3434046565050                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3434197896405                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.395092                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.424547                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 143949960                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 153377280                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                  78544125                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                  83688000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                313723800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                343379400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               322509600                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               350470800                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          335311916160                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          335311916160                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          122830725285                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          123321765465                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          2972506855500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2972076118500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3431508224430                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3431640715605                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.420699                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.446507                       # Core power per rank (mW)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                       818767223                       # number of cpu cycles simulated
+system.cpu0.numCycles                       816782821                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72040073                       # Number of instructions committed
-system.cpu0.committedOps                    146798683                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            134677148                       # Number of integer alu accesses
+system.cpu0.committedInsts                   71499658                       # Number of instructions committed
+system.cpu0.committedOps                    145804776                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            133691400                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     957492                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14259376                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   134677148                       # number of integer instructions
+system.cpu0.num_func_calls                     937441                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14175274                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   133691400                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          247199145                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         115729599                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          245252400                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         114908320                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            83822967                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55940767                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13836630                       # number of memory refs
-system.cpu0.num_load_insts                   10218166                       # Number of load instructions
-system.cpu0.num_store_insts                   3618464                       # Number of store instructions
-system.cpu0.num_idle_cycles              776544159.837226                       # Number of idle cycles
-system.cpu0.num_busy_cycles              42223063.162775                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.051569                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.948431                       # Percentage of idle cycles
-system.cpu0.Branches                         15573109                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                95028      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                132757091     90.43%     90.50% # Class of executed instruction
-system.cpu0.op_class::IntMult                   59427      0.04%     90.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    51115      0.03%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::MemRead                10218166      6.96%     97.54% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3618464      2.46%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            83238542                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55564556                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13632532                       # number of memory refs
+system.cpu0.num_load_insts                   10074437                       # Number of load instructions
+system.cpu0.num_store_insts                   3558095                       # Number of store instructions
+system.cpu0.num_idle_cycles              775198881.273652                       # Number of idle cycles
+system.cpu0.num_busy_cycles              41583939.726348                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050912                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949088                       # Percentage of idle cycles
+system.cpu0.Branches                         15460140                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                93742      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                131973601     90.51%     90.58% # Class of executed instruction
+system.cpu0.op_class::IntMult                   57512      0.04%     90.62% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47972      0.03%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.65% # Class of executed instruction
+system.cpu0.op_class::MemRead                10074437      6.91%     97.56% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3558095      2.44%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 146799291                       # Class of executed instruction
+system.cpu0.op_class::total                 145805359                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          1637866                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999423                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19673585                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1638378                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            12.007965                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1638252                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999461                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19656533                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1638764                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.994731                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.297276                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.648639                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.053508                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246674                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.548142                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205183                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.389920                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.383418                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.226123                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246855                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.547624                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205520                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          270                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88453877                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88453877                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5010669                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2623262                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      3898583                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11532514                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3480346                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1810737                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2788314                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8079397                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20263                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10587                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29029                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        59879                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8491015                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4433999                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6686897                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19611911                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8511278                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4444586                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6715926                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19671790                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       362952                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       164891                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       772037                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1299880                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       133960                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        65129                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       126515                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       325604                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       151937                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        64294                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       190363                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406594                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       496912                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       230020                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       898552                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1625484                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       648849                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       294314                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1088915                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2032078                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2296036750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  11919855793                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14215892543                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2581335822                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3855689962                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6437025784                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4877372572                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  15775545755                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  20652918327                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4877372572                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  15775545755                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  20652918327                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5373621                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2788153                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4670620                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12832394                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3614306                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1875866                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2914829                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8405001                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        74881                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       219392                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466473                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8987927                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4664019                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7585449                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21237395                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9160127                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4738900                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7804841                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21703868                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067543                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059140                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.165296                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.101297                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.037064                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034719                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043404                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038739                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.882329                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.858616                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867684                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871635                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055287                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049318                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.118457                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.076539                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070834                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062106                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.139518                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.093627                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13924.572900                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15439.487736                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10936.311462                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39634.200157                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30476.148773                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19769.492340                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21204.123867                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17556.630841                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 12705.703856                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16572.003275                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14487.398700                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10163.447627                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       128010                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88454507                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88454507                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4870617                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2557813                       # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::cpu1.data      1747628                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total       8076625                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20088                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10280                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29520                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        59888                       # number of SoftPFReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      8289029                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      4305441                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      7000364                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19594834                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8309117                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      4315721                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      7029884                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19654722                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       359255                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       161570                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       796344                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1317169                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       135705                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        61031                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       128691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       325427                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       152338                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        62833                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       191442                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       406613                       # number of SoftPFReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       494960                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       222601                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       925035                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1642596                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       647298                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       285434                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1116477                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2049209                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2259833750                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13132608806                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  15392442556                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2339164805                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3938449787                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6277614592                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   4598998555                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  17071058593                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  21670057148                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   4598998555                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  17071058593                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  21670057148                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5229872                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2719383                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4886123                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     12835378                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3554117                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1808659                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3039276                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8402052                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172426                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        73113                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       220962                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       466501                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8783989                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4528042                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7925399                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21237430                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8956415                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4601155                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      8146361                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21703931                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068693                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059414                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.162981                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.102620                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038182                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.033744                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042343                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038732                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.883498                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.859396                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866402                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871623                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056348                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049161                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116718                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.077344                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072272                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062035                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.137052                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.094416                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.716284                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16491.125451                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11686.004268                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.486114                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30603.925581                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19290.392598                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20660.278054                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18454.500201                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13192.566613                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16112.301110                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15290.112195                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10574.839925                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       135105                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            27734                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            28093                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.615634                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.809205                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1547592                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1547592                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           59                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       355847                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       355906                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1633                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        30941                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        32574                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1692                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       386788                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       388480                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1692                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       386788                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       388480                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       164832                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       416190                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       581022                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        63496                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        95574                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       159070                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64293                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186824                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       251117                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       228328                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       511764                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       740092                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       292621                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       698588                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       991209                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1964999750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5660700319                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7625700069                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2364352650                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3101755528                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5466108178                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    883443250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2757990753                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3641434003                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4329352400                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8762455847                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13091808247                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5212795650                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11520446600                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16733242250                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30452050000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32985877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63437927000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    577982500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    687759500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1265742000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31030032500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33673636500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64703669000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059119                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.089108                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045278                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033849                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032789                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018926                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.858602                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.851553                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.538331                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048955                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.067467                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034849                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061749                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.089507                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045670                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1547770                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1547770                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           57                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       372578                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       372635                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1579                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        31008                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        32587                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1636                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       403586                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       405222                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1636                       # number of overall MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total       405222                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       161513                       # number of ReadReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_misses::total       585279                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59452                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total       157135                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        62832                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       187900                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       250732                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       220965                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       521449                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       742414                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       283797                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       709349                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       993146                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1935504250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5902265073                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7837769323                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2132980169                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3177778177                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5310758346                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    865437000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2825430002                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3690867002                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4068484419                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9080043250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13148527669                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4933921419                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11905473252                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16839394671                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30454123000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33015030500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63469153500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    582453000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    716246000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1298699000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31036576000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33731276500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64767852500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059393                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086728                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045599                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032871                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032140                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018702                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.859382                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850372                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.537474                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048799                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065795                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034958                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061680                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087076                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.045759                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11983.581817                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13928.123240                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13391.509559                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35877.349273                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32531.537494                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33797.424800                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13773.825439                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15036.881330                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14720.366774                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18412.347743                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17413.099364                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17710.506091                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17385.389624                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16783.661148                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16955.608411                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -618,520 +615,520 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           866413                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.840210                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          130156159                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           866925                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           150.135432                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           869855                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.839263                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129296965                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           870367                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           148.554535                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle     149014386250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   138.994027                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.522548                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.323634                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271473                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520552                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205710                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997735                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   139.113677                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.308370                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.417216                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271706                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520134                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205893                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997733                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          296                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131912504                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131912504                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     87639896                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39531787                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2984476                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      130156159                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     87639896                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39531787                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2984476                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       130156159                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     87639896                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39531787                       # number of overall hits
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-system.cpu0.icache.overall_hits::total      130156159                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       328528                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       162109                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       398768                       # number of ReadReq misses
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-system.cpu0.icache.overall_misses::cpu0.inst       328528                       # number of overall misses
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-system.cpu0.icache.overall_misses::cpu2.inst       398768                       # number of overall misses
-system.cpu0.icache.overall_misses::total       889405                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2245844750                       # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_miss_latency::total   7852170944                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2245844750                       # number of demand (read+write) miss cycles
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-system.cpu0.icache.demand_miss_latency::total   7852170944                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2245844750                       # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total   7852170944                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     87968424                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39693896                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::cpu0.inst     87968424                       # number of overall (read+write) accesses
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-system.cpu0.icache.overall_accesses::total    131045564                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003735                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004084                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117866                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006787                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003735                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004084                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117866                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006787                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003735                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004084                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117866                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006787                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8828.566226                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8828.566226                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8828.566226                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4938                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131061052                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131061052                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     86941528                       # number of ReadReq hits
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+system.cpu0.icache.overall_hits::total      129296965                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       320636                       # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total       893702                       # number of overall misses
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+system.cpu0.icache.ReadReq_miss_latency::total   8009207336                       # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total   8009207336                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::total   8009207336                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     87262164                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003674                       # miss rate for ReadReq accesses
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+system.cpu0.icache.overall_miss_rate::total     0.006865                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13993.777201                       # average ReadReq miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::total  8961.832172                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8961.832172                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8961.832172                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4336                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              262                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              258                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.847328                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.806202                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22465                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        22465                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        22465                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        22465                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        22465                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        22465                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       162109                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376303                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       538412                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       162109                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       376303                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       538412                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       162109                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       376303                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       538412                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1920905250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4627637688                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6548542938                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1920905250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4627637688                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6548542938                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1920905250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4627637688                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6548542938                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004109                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004109                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004109                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23317                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        23317                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        23317                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        23317                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        23317                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        23317                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       160378                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       389371                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       549749                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       160378                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       389371                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       549749                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       160378                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       389371                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       549749                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1922680000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4757652042                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6680332042                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1922680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4757652042                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6680332042                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1922680000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4757652042                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6680332042                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004223                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004223                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004223                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12151.603808                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2606022983                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2604022160                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35939339                       # Number of instructions committed
-system.cpu1.committedOps                     69774923                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64844483                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35714054                       # Number of instructions committed
+system.cpu1.committedOps                     69387825                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64459883                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     499287                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6580388                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64844483                       # number of integer instructions
+system.cpu1.num_func_calls                     492416                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6558216                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64459883                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          120226227                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55826198                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          119340959                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55539831                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36586824                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27309791                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4927873                       # number of memory refs
-system.cpu1.num_load_insts                    3050339                       # Number of load instructions
-system.cpu1.num_store_insts                   1877534                       # Number of store instructions
-system.cpu1.num_idle_cycles              2477290986.248718                       # Number of idle cycles
-system.cpu1.num_busy_cycles              128731996.751282                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.049398                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.950602                       # Percentage of idle cycles
-system.cpu1.Branches                          7259898                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                35461      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64754697     92.80%     92.86% # Class of executed instruction
-system.cpu1.op_class::IntMult                   31756      0.05%     92.90% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    25505      0.04%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     92.94% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3050339      4.37%     97.31% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1877534      2.69%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36447320                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27215061                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4790084                       # number of memory refs
+system.cpu1.num_load_insts                    2979771                       # Number of load instructions
+system.cpu1.num_store_insts                   1810313                       # Number of store instructions
+system.cpu1.num_idle_cycles              2477161896.436619                       # Number of idle cycles
+system.cpu1.num_busy_cycles              126860263.563381                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.048717                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.951283                       # Percentage of idle cycles
+system.cpu1.Branches                          7226981                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                35150      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64505894     92.96%     93.01% # Class of executed instruction
+system.cpu1.op_class::IntMult                   31723      0.05%     93.06% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    25263      0.04%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.10% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2979771      4.29%     97.39% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1810313      2.61%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69775292                       # Class of executed instruction
+system.cpu1.op_class::total                  69388114                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29000272                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29000272                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           311632                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26370508                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25723888                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29235559                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29235559                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           325219                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26520697                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25831839                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.547943                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 573459                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             63282                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       153009050                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.402564                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 591824                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             65511                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       154416401                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10521285                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     142969715                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29000272                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26297347                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    141031314                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 650011                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     92984                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                4408                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             9006                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        47091                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles         2529                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          579                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3383247                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               163781                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3234                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         152033550                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.852472                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.031588                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10884284                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     144162908                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29235559                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26423663                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    142028644                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 680270                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    102603                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                5389                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             9165                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        58663                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles         3537                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          505                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3520608                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               170393                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3486                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         153432274                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.849912                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.030749                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                97124192     63.88%     63.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  819598      0.54%     64.42% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23594190     15.52%     79.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  577537      0.38%     80.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  790978      0.52%     80.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  823076      0.54%     81.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  560198      0.37%     81.75% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  693420      0.46%     82.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27050361     17.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                98146892     63.97%     63.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  849455      0.55%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23639563     15.41%     79.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  596355      0.39%     80.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  820460      0.53%     80.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  843182      0.55%     81.40% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  578600      0.38%     81.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  712944      0.46%     82.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27244823     17.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           152033550                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.189533                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.934387                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9712542                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             92934302                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 23280371                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              5017317                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                325657                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             278875678                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                325657                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                11857648                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               75889768                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4419845                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 25919685                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             12857653                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             277706863                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               221466                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5888159                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 42783                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4808995                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          331833488                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            605194394                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       371618079                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               36                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            320107208                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                11726280                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            151218                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        152719                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 24489304                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6338862                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3553328                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           367719                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          319565                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 275826769                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             413139                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                273878584                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            98557                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8364175                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     12972199                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         61453                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    152033550                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.801435                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.398557                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           153432274                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.189329                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.933598                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10016257                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             93700057                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23552939                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5059225                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                340786                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             280915475                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                340786                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12183481                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               76207577                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4633489                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 26208589                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             13095410                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             279683437                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               223314                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5946104                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 66230                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4950669                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          334110880                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            610223912                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       374707495                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               50                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            321802825                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                12308055                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            159496                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        160992                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 24728287                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6624186                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3707561                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           399799                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          335575                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 277732310                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             423659                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                275640781                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           103956                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8785176                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     13632215                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         64646                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    153432274                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.796498                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.396081                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           89826062     59.08%     59.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5325607      3.50%     62.59% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3883778      2.55%     65.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3618974      2.38%     67.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           22318323     14.68%     82.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2568868      1.69%     83.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23837030     15.68%     99.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             450577      0.30%     99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             204331      0.13%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           90704132     59.12%     59.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5447937      3.55%     62.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3973753      2.59%     65.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3694975      2.41%     67.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           22399331     14.60%     82.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2621812      1.71%     83.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23895005     15.57%     99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             478633      0.31%     99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             216696      0.14%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      152033550                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      153432274                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1765790     86.71%     86.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                213483     10.48%     97.20% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                57008      2.80%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1775129     86.29%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                220574     10.72%     97.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                61430      2.99%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            75484      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            263736524     96.30%     96.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               54819      0.02%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                47031      0.02%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6686249      2.44%     98.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3278477      1.20%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            78003      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            265083835     96.17%     96.20% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               56667      0.02%     96.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                50646      0.02%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6950861      2.52%     98.76% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3420769      1.24%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             273878584                       # Type of FU issued
-system.cpu2.iq.rate                          1.789950                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2036382                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007435                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         701925596                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        284608270                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    272313229                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 61                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                68                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             275839453                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     29                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          685704                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             275640781                       # Type of FU issued
+system.cpu2.iq.rate                          1.785049                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2057234                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007463                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         706874938                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        286945707                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    274032875                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 88                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                98                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           22                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             277619970                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     42                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          720639                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1161006                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6104                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4803                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       634153                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1236107                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6357                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5250                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       663784                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       755552                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        21313                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       755898                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        23011                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                325657                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               70767994                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              1741893                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          276239908                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            40444                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6338884                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3553328                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            236248                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                194416                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              1250638                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4803                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        177191                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       184398                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              361589                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            273320009                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6554812                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           510377                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                340786                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               71022096                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              1766284                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          278155969                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            42225                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6624208                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3707561                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            245817                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                196681                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              1270617                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5250                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        184655                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       193373                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              378028                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            275054919                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6809103                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           532643                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9748811                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27755327                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3193999                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.786300                       # Inst execution rate
-system.cpu2.iew.wb_sent                     273134840                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    272313245                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                212432379                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                348339663                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                    10142277                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27929616                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3333174                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.781255                       # Inst execution rate
+system.cpu2.iew.wb_sent                     274858802                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    274032897                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                213637344                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                350353641                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.779720                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609843                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.774636                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609776                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        8691419                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         351686                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           314047                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    150733678                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.774964                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.652543                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        9127323                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         359013                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           328005                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    152066658                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.769136                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.649747                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     93656646     62.13%     62.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4148238      2.75%     64.89% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1235888      0.82%     65.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24514613     16.26%     81.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4      1002757      0.67%     82.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       665638      0.44%     83.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       467092      0.31%     83.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23101150     15.33%     98.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1941656      1.29%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     94590362     62.20%     62.20% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4261266      2.80%     65.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1284145      0.84%     65.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24598382     16.18%     82.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      1032712      0.68%     82.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       681511      0.45%     83.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       477761      0.31%     83.47% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23127222     15.21%     98.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2013297      1.32%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    150733678                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           135526613                       # Number of instructions committed
-system.cpu2.commit.committedOps             267546921                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    152066658                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           136342288                       # Number of instructions committed
+system.cpu2.commit.committedOps             269026601                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8097053                       # Number of memory references committed
-system.cpu2.commit.loads                      5177878                       # Number of loads committed
-system.cpu2.commit.membars                     162019                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27358633                       # Number of branches committed
+system.cpu2.commit.refs                       8431878                       # Number of memory references committed
+system.cpu2.commit.loads                      5388101                       # Number of loads committed
+system.cpu2.commit.membars                     162694                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27513301                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                244351653                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              425746                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        44568      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       259307312     96.92%     96.94% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          52493      0.02%     96.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           45495      0.02%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.97% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5177878      1.94%     98.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2919175      1.09%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                245807321                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              438928                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        45809      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       260445608     96.81%     96.83% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          54412      0.02%     96.85% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           48894      0.02%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5388101      2.00%     98.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3043777      1.13%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        267546921                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1941656                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        269026601                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2013297                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   425004820                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  553782312                       # The number of ROB writes
-system.cpu2.timesIdled                         113608                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                         975500                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4910108147                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  135526613                       # Number of Instructions Simulated
-system.cpu2.committedOps                    267546921                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.128996                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.128996                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.885742                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.885742                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               363608614                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              218247524                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72984                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                138904210                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               106846664                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               88678814                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                129757                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3554542                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3554542                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57685                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              33021                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        24664                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1687                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1687                       # Transaction distribution
+system.cpu2.rob.rob_reads                   428179753                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  557679634                       # The number of ROB writes
+system.cpu2.timesIdled                         117886                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                         984127                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4904701568                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  136342288                       # Number of Instructions Simulated
+system.cpu2.committedOps                    269026601                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.132564                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.132564                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.882952                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.882952                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               366241285                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              219634896                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    72934                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                139741848                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               107405291                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               89464185                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                137179                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3554524                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3554524                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57693                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              10973                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1666                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1666                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
@@ -1141,21 +1138,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7085054                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27782                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27740                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7129206                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3374                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3374                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7227828                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7129192                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95242                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95242                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3332                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3332                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7227766                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
@@ -1165,28 +1162,28 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3542527                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13891                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13870                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3570760                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6748                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6605284                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2693792                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3570795                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027752                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027752                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6605211                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2723904                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4846000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              5226000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1200,379 +1197,377 @@ system.iobus.reqLayer8.occupancy                18000                       # La
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              333000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              355000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            10264000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            10403000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           199614020                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           252354975                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           303080000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           303598000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            27344255                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            31582004                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1127000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1142000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47569                       # number of replacements
-system.iocache.tags.tagsinuse                0.092434                       # Cycle average of tags in use
+system.iocache.tags.replacements                47566                       # number of replacements
+system.iocache.tags.tagsinuse                0.080066                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47582                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         5000571333009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092434                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005777                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005777                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.080066                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005004                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005004                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
-system.iocache.tags.data_accesses              428616                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
-system.iocache.overall_misses::total              904                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    131931527                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    131931527                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    131931527                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    131931527                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    131931527                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    131931527                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses               428589                       # Number of tag accesses
+system.iocache.tags.data_accesses              428589                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          901                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              901                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          901                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               901                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          901                       # number of overall misses
+system.iocache.overall_misses::total              901                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    129757279                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    129757279                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   6940731692                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   6940731692                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    129757279                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    129757279                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    129757279                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    129757279                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          901                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            901                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          901                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             901                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          901                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            901                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 145941.954646                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 145941.954646                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 145941.954646                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 144014.738069                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 148560.181764                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 148560.181764                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 144014.738069                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 144014.738069                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         39427                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 5130                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.685575                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      46720                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          734                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          734                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          734                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          734                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     93740027                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     93740027                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     93740027                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.811947                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.811947                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.811947                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          749                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        26264                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        26264                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          749                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          749                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          749                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          749                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     90783279                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     90783279                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     90783279                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.831299                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.831299                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.831299                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 121205.979973                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212267.579196                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212267.579196                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104648                       # number of replacements
-system.l2c.tags.tagsinuse                64825.327064                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3691316                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168821                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.865266                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104681                       # number of replacements
+system.l2c.tags.tagsinuse                64826.811839                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3703362                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168901                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.926229                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51329.060133                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131449                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1735.761730                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4946.132925                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003182                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      379.214744                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1982.386911                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.162749                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      878.696468                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3562.776774                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.783219                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51337.140952                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134260                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1734.424462                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4936.447431                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      379.153025                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1982.017983                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.155297                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      876.173345                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3570.165084                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.783343                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.026486                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.075472                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.005786                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.030249                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.026465                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075324                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.005785                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.030243                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000170                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.013408                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.054364                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.989156                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64173                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu2.inst       0.013369                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.054476                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.989179                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64220                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3770                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7642                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52446                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.979202                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33857298                       # Number of tag accesses
-system.l2c.tags.data_accesses                33857298                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        21885                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        11413                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             321088                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             497388                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        12632                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6595                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             160077                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             224317                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        53710                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        12539                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             370609                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             592462                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2284715                       # number of ReadReq hits
+system.l2c.tags.age_task_id_blocks_1024::2         3804                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7293                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52804                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.979919                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33932949                       # Number of tag accesses
+system.l2c.tags.data_accesses                33932949                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        20141                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        10481                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             313222                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             496902                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        12246                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6578                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             158014                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             219469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        60958                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        13844                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             383974                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             598300                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2294129                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1547592                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1547592                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             126                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              49                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              89                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 264                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            63533                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            34910                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            62567                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               161010                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         21885                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         11415                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              321088                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              560921                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         12632                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6595                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              160077                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              259227                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         53710                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         12539                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              370609                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              655029                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2445727                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        21885                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        11415                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             321088                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             560921                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        12632                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6595                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             160077                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             259227                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        53710                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        12539                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             370609                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             655029                       # number of overall hits
-system.l2c.overall_hits::total                2445727                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7427                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data            17501                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2032                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4808                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           42                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             5670                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            10484                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                47969                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           766                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           250                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           384                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1400                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          69535                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          28299                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          32603                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130437                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7427                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             87036                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2032                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             33107                       # number of demand (read+write) misses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1581,125 +1576,113 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10002                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               96575                       # number of writebacks
+system.l2c.writebacks::total                    96575                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2364                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4876                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           40                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         5371                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        13291                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25942                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          243                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          469                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          712                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        25348                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        33283                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         58631                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2364                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        30224                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           40                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5371                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        46574                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            84573                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2364                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        30224                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           40                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5371                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        46574                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           84573                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    144701000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    312699250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    355314750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    886085249                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1701694499                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3030731                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4866963                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      7897694                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399676087                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1973869844                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3373545931                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    144701000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1712375337                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    355314750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2859955093                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5075240430                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    144701000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1712375337                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    355314750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2859955093                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5075240430                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27999108000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30259934500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58259042500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    541915000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    672587500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1214502500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28541023000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30932522000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  59473545000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021734                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021732                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.011076                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.886861                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.834520                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.425837                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.428248                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.342428                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.201304                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.106597                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.065709                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.032115                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.106597                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.065709                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.032115                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64130.280968                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66668.064781                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 65596.118225                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12472.144033                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10377.319829                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11092.266854                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55218.403306                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59305.646847                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57538.604680                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56656.145348                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61406.688131                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60010.173814                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56656.145348                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61406.688131                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60010.173814                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1710,70 +1693,70 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5119571                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5119569                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13900                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13900                       # Transaction distribution
-system.membus.trans_dist::Writeback             96569                       # Transaction distribution
+system.membus.trans_dist::ReadReq             5119623                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5119621                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13885                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13885                       # Transaction distribution
+system.membus.trans_dist::Writeback            143242                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1658                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1658                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130179                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130179                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1687                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1687                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1670                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1670                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130030                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130030                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1666                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1666                       # Transaction distribution
 system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129206                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3332                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3332                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129192                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039944                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       455611                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10625377                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10723708                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6748                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079977                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17581760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27232497                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3029312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3029312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30268557                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              291                       # Total snoops (count)
-system.membus.snoop_fanout::samples            323999                       # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::total     10624751                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141603                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141603                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10769686                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570795                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079885                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17550016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27200696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6014848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6014848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33222208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              744                       # Total snoops (count)
+system.membus.snoop_fanout::samples            370602                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  323999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  370602    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              323999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           162958500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              370602                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           163555999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           314938500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           314970500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2254000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2284000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           804193000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1078528499                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                2000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1127000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1142000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1664243698                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1669525375                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           28678745                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           33021996                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -1783,52 +1766,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            7431790                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7431262                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13902                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13902                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1547592                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        22056                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1664                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1664                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           291447                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          291447                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            7445520                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7444981                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13887                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13887                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          1547770                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        26264                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1672                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1672                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           291256                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          291256                       # Transaction distribution
 system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1733856                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14997138                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72735                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       201275                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17005004                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55482624                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213567857                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       271280                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       749120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270070881                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           66934                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4248687                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.011209                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105278                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740744                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14998032                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73579                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       215574                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17027929                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55702976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213603640                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       275304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       788512                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              270370432                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           71210                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4262409                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.011172                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.105107                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                4201063     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  47624      1.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                4214788     98.88%     98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  47621      1.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4248687                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5247340592                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4262409                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5252515580                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           936000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           954000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2425844552                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2476922699                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4872344858                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4880781676                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          24091410                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          25221399                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          80681637                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          92014088                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 477530da6..a4eaa28e3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061144                       # Number of seconds simulated
-sim_ticks                                 61144411500                       # Number of ticks simulated
-final_tick                                61144411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061494                       # Number of seconds simulated
+sim_ticks                                 61493732000                       # Number of ticks simulated
+final_tick                                61493732000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 271316                       # Simulator instruction rate (inst/s)
-host_op_rate                                   272668                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              183101149                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 442968                       # Number of bytes of host memory used
-host_seconds                                   333.94                       # Real time elapsed on the host
+host_inst_rate                                 280016                       # Simulator instruction rate (inst/s)
+host_op_rate                                   281410                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              190051649                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 385752                       # Number of bytes of host memory used
+host_seconds                                   323.56                       # Real time elapsed on the host
 sim_insts                                    90602849                       # Number of instructions simulated
 sim_ops                                      91054080                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            996736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            996800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               996800                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        49600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           49600                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst              15574                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst             16301343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16301343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          811194                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             811194                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            16301343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16301343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15574                       # Number of read requests accepted
+system.physmem.num_reads::cpu.inst              15575                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15575                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst             16209782                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16209782                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          806586                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             806586                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            16209782                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16209782                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15575                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15575                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   996800                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    996800                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 993                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 890                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 950                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 949                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
@@ -49,10 +49,10 @@ system.physmem.perBankRdBursts::8                1024                       # Pe
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                867                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                904                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                905                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61144323500                       # Total gap between requests
+system.physmem.totGap                     61493643500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15575                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -86,9 +86,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     15451                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       114                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     15453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1531                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      649.865447                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     447.084914                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     397.724653                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            242     15.81%     15.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          164     10.71%     26.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           94      6.14%     32.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           77      5.03%     37.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           65      4.25%     41.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          106      6.92%     48.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           51      3.33%     52.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      1.83%     54.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          704     45.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1531                       # Bytes accessed per row activation
-system.physmem.totQLat                       71490500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 363503000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4590.37                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1534                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      648.594524                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     444.741065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     399.329877                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            241     15.71%     15.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          178     11.60%     27.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           90      5.87%     33.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           63      4.11%     37.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           79      5.15%     42.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          102      6.65%     49.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           37      2.41%     51.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           39      2.54%     54.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          705     45.96%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1534                       # Bytes accessed per row activation
+system.physmem.totQLat                       73246500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 365277750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77875000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4702.83                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23340.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          16.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23452.83                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          16.21                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       16.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       16.21                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
@@ -212,68 +212,45 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14033                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14031                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.11                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.09                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3926051.34                       # Average gap between requests
-system.physmem.pageHitRate                      90.11                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      55905599000                       # Time in different power states
-system.physmem.memoryStateTime::REF        2041520000                       # Time in different power states
+system.physmem.avgGap                      3948227.51                       # Average gap between requests
+system.physmem.pageHitRate                      90.09                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      56242943250                       # Time in different power states
+system.physmem.memoryStateTime::REF        2053220000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        3193563500                       # Time in different power states
+system.physmem.memoryStateTime::ACT        3193793750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   6305040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   5254200                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   3440250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2866875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 63671400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 57454800                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                   6320160                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                   5261760                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                   3448500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                   2871000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                 63663600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                 57462600                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            3993213120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            3993213120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            2474179335                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            2524417425                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           34512404250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           34468335750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             41053213395                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             41051542170                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             671.485556                       # Core power per rank (mW)
-system.physmem.averagePower::1             671.458220                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                1030                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  996736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15574                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15574    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21822000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          149565000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                20748984                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17053332                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            764055                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8969348                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8846034                       # Number of BTB hits
+system.physmem.refreshEnergy::0            4016098320                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1            4016098320                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0            2490497865                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1            2514078765                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0           34708310250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1           34687625250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0             41288338695                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1             41283397695                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             671.483256                       # Core power per rank (mW)
+system.physmem.averagePower::1             671.402899                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                20789429                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17091399                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            765966                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8973618                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8867020                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.625162                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   62305                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.812096                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   62716                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -359,69 +336,192 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        122288823                       # number of cpu cycles simulated
+system.cpu.numCycles                        122987464                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602849                       # Number of instructions committed
 system.cpu.committedOps                      91054080                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2027782                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2068195                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.349724                       # CPI: cycles per instruction
-system.cpu.ipc                               0.740892                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109176308                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13112515                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.357435                       # CPI: cycles per instruction
+system.cpu.ipc                               0.736684                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109826570                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13160894                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            946107                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3616.604238                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26267660                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            950203                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.644261                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20617906250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3616.604238                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.882960                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.882960                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          262                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2249                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1585                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          55463255                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55463255                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     21598813                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21598813                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      4661073                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4661073                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      26259886                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26259886                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     26259886                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26259886                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       914958                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        914958                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst        73908                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        73908                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       988866                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         988866                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       988866                       # number of overall misses
+system.cpu.dcache.overall_misses::total        988866                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11910311744                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11910311744                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2345697500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2345697500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  14256009244                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14256009244                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  14256009244                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14256009244                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     22513771                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22513771                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     27248752                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27248752                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     27248752                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27248752                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.040640                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040640                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.015609                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015609                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.036290                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036290                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.036290                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036290                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14416.522809                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14416.522809                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       943286                       # number of writebacks
+system.cpu.dcache.writebacks::total            943286                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        11523                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11523                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        27140                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27140                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        38663                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        38663                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        38663                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        38663                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       903435                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903435                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        46768                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46768                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       950203                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       950203                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       950203                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       950203                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958869756                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958869756                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1333434750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1333434750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11292304506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11292304506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11292304506                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11292304506                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.040128                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040128                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034871                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034871                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034871                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034871                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           690.927522                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27773574                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           690.411179                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27857009                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               803                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34587.265255                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34691.169365                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   690.927522                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.337367                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.337367                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   690.411179                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.337115                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.337115                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55549557                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55549557                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27773574                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27773574                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27773574                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27773574                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27773574                       # number of overall hits
-system.cpu.icache.overall_hits::total        27773574                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          55716427                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55716427                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27857009                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27857009                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27857009                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27857009                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27857009                       # number of overall hits
+system.cpu.icache.overall_hits::total        27857009                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          803                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           803                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          803                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            803                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          803                       # number of overall misses
 system.cpu.icache.overall_misses::total           803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     55313498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     55313498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     55313498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     55313498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     55313498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     55313498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27774377                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27774377                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27774377                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27774377                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27774377                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27774377                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     55346748                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     55346748                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     55346748                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     55346748                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     55346748                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     55346748                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27857812                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27857812                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27857812                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27857812                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27857812                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27857812                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68883.559153                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68883.559153                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68924.966376                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68924.966376                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -436,130 +536,97 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          803
 system.cpu.icache.demand_mshr_misses::total          803                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          803                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          803                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53373502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     53373502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53373502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     53373502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53373502                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     53373502                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53408252                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     53408252                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53408252                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     53408252                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53408252                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     53408252                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         904183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        904183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       943269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46761                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843551                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2845157                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121178240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121229632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1894213                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            1894213    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1894213                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1890375500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1371498                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1428579494                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10264.635477                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831263                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.713119                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10247.121792                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1831334                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15558                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.710117                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9373.658869                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.976609                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.286061                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027190                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.313252                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  9356.236502                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.885290                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.285530                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027188                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.312717                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15558                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1094                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13878                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15216022                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15216022                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       903145                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903145                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       943269                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       943269                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        32217                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32217                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       935362                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          935362                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       935362                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         935362                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1038                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1038                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474792                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15216662                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15216662                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       903199                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         903199                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       943286                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       943286                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst        32224                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32224                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadReq_misses::cpu.inst         1039                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1039                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.inst        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15582                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15582                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71732750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     71732750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    959611500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    959611500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1031344250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1031344250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1031344250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1031344250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       904183                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       904183                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       943269                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       943269                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        46761                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46761                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       950944                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       950944                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::total       950944                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.001148                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001148                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.311028                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.311028                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_misses::cpu.inst        15583                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15583                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15583                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15583                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71718500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     71718500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    958069250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    958069250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1029787750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1029787750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1029787750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1029787750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       904238                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       904238                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       943286                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       943286                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        46768                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46768                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       951006                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       951006                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       951006                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       951006                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.001149                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001149                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.310982                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.310982                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016386                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016386                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016386                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -574,161 +641,94 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst            8
 system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1030                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1030                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1031                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1031                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        14544                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15574                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15574                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58370500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58370500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    772672000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    772672000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    831042500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    831042500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    831042500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    831042500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001139                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001139                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.311028                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311028                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15575                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15575                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58344750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58344750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    774500250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    774500250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    832845000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    832845000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    832845000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    832845000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001140                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001140                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.310982                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.310982                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            946045                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3618.157159                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26265609                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            950141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.643907                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20427116250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3618.157159                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.883339                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883339                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2250                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1585                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55458945                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55458945                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     21596750                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21596750                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst      4661085                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4661085                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst         3887                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      26257835                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26257835                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     26257835                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26257835                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       914897                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        914897                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst        73896                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        73896                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       988793                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         988793                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       988793                       # number of overall misses
-system.cpu.dcache.overall_misses::total        988793                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11909486494                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11909486494                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2342568500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2342568500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  14252054994                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14252054994                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  14252054994                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14252054994                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     22511647                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22511647                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     27246628                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27246628                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     27246628                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27246628                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.040641                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040641                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.015606                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015606                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.036290                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036290                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.036290                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036290                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14413.588076                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14413.588076                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       943269                       # number of writebacks
-system.cpu.dcache.writebacks::total            943269                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        11517                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11517                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        27135                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27135                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst        38652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        38652                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst        38652                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        38652                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       903380                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903380                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        46761                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46761                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       950141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       950141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       950141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       950141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958325256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958325256                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1334896250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1334896250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11293221506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11293221506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11293221506                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11293221506                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.040129                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040129                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009876                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034872                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq         904238                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904238                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       943286                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        46768                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46768                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843692                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2845298                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121183296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121234688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1894292                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            1894292    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        1894292                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1890432000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1370748                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1428672494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                1031                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1031                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  996800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples             15575                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   15575    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total               15575                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            17956500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          146202000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index d4eaaecb0..f1692fa7b 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.409380                       # Number of seconds simulated
-sim_ticks                                409379703500                       # Number of ticks simulated
-final_tick                               409379703500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.411003                       # Number of seconds simulated
+sim_ticks                                411003011000                       # Number of ticks simulated
+final_tick                               411003011000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 295886                       # Simulator instruction rate (inst/s)
-host_op_rate                                   295886                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              197956312                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239696                       # Number of bytes of host memory used
-host_seconds                                  2068.03                       # Real time elapsed on the host
+host_inst_rate                                 279515                       # Simulator instruction rate (inst/s)
+host_op_rate                                   279515                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              187744969                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239248                       # Number of bytes of host memory used
+host_seconds                                  2189.16                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          24321024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24321024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       170880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          170880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18723904                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18723904                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             380016                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                380016                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292561                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292561                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             59409452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59409452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          417412                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             417412                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45737255                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45737255                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45737255                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            59409452                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              105146708                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        380016                       # Number of read requests accepted
-system.physmem.writeReqs                       292561                       # Number of write requests accepted
-system.physmem.readBursts                      380016                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292561                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24297984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     23040                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18722304                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24321024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18723904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      360                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst          24320320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24320320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       170944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          170944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18724480                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18724480                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             380005                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380005                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292570                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292570                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             59173094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                59173094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          415919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             415919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45558012                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45558012                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45558012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            59173094                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104731106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        380005                       # Number of read requests accepted
+system.physmem.writeReqs                       292570                       # Number of write requests accepted
+system.physmem.readBursts                      380005                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292570                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24297088                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     23232                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18722944                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24320320                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18724480                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      363                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23733                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23212                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23513                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24527                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25463                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23584                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23682                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23974                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23187                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23951                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24675                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22741                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23717                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24415                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22809                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22473                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               17752                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               17434                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23737                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23219                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23515                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24536                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25458                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23589                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23674                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23973                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23176                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23944                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24674                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22747                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23719                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24413                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22804                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22464                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               17754                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               17431                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               17902                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18771                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18773                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               19442                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18539                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18683                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18574                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18353                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18543                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18682                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18577                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18349                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18833                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19130                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17961                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18219                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19127                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17965                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18224                       # Per bank write bursts
 system.physmem.perBankWrBursts::13              18693                       # Per bank write bursts
 system.physmem.perBankWrBursts::14              17148                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17102                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17103                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    409379622500                       # Total gap between requests
+system.physmem.totGap                    411002929500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  380016                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  380005                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292561                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    378259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1382                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292570                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    378255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1372                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17338                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17397                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17404                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17430                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17507                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
@@ -189,150 +189,123 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       141528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.959754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.049332                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.018132                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50528     35.70%     35.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38641     27.30%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        12939      9.14%     72.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7964      5.63%     77.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5792      4.09%     81.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3807      2.69%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3019      2.13%     86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2550      1.80%     88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16288     11.51%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         141528                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17267                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.986332                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      228.214102                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17257     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            7      0.04%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       141657                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.679790                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.908631                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.510648                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50805     35.86%     35.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38362     27.08%     62.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        12861      9.08%     72.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8208      5.79%     77.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5905      4.17%     81.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3832      2.71%     84.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2875      2.03%     86.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2523      1.78%     88.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16286     11.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         141657                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17265                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.988184                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      229.046433                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17255     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17267                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17267                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.941912                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.866733                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.774183                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17056     98.78%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             152      0.88%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.18%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              11      0.06%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               2      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17265                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17265                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.944454                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.865388                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.133478                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17065     98.84%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             148      0.86%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              28      0.16%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               9      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               3      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::236-239             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17267                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4096707750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11215257750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1898280000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10790.58                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17265                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4080991250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11199278750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1898210000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10749.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29540.58                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          59.35                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       59.41                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.74                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29499.58                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          59.12                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.55                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       59.17                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.14                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314853                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215803                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                       608673.24                       # Average gap between requests
-system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     275372649250                       # Time in different power states
-system.physmem.memoryStateTime::REF       13670020000                       # Time in different power states
+system.physmem.avgWrQLen                        20.64                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314689                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215833                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.77                       # Row buffer hit rate for writes
+system.physmem.avgGap                       611088.62                       # Average gap between requests
+system.physmem.pageHitRate                      78.92                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     276203849000                       # Time in different power states
+system.physmem.memoryStateTime::REF       13724100000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      120335301000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      121069531000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 544939920                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 524943720                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 297338250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 286427625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1495143000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1465986600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               953104320                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               942425280                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           26738559120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           26738559120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           61488174015                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           58208465835                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          191689779750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          194566716750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            283207038375                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            282733524930                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             691.798455                       # Core power per rank (mW)
-system.physmem.averagePower::1             690.641789                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              173391                       # Transaction distribution
-system.membus.trans_dist::ReadResp             173391                       # Transaction distribution
-system.membus.trans_dist::Writeback            292561                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206625                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206625                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052593                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1052593                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43044928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43044928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            672577                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  672577    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              672577                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          3204370000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3607409500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               123709339                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87626566                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6391113                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71478402                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67228425                       # Number of BTB hits
+system.physmem.actEnergy::0                 545847120                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 524837880                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 297833250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 286369875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1495111800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1465471800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               953117280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               942373440                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           26844339600                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           26844339600                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           61600136265                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           58531832820                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          192563272500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          195254766750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            284299657815                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            283849992165                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             691.730926                       # Core power per rank (mW)
+system.physmem.averagePower::1             690.636842                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               124266527                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87927203                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6406168                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71920312                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67440384                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.054180                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                14930713                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1120398                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.770984                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15061672                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126459                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149300115                       # DTB read hits
-system.cpu.dtb.read_misses                     537223                       # DTB read misses
+system.cpu.dtb.read_hits                    149394307                       # DTB read hits
+system.cpu.dtb.read_misses                     568771                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                149837338                       # DTB read accesses
-system.cpu.dtb.write_hits                    57314034                       # DTB write hits
-system.cpu.dtb.write_misses                     66532                       # DTB write misses
+system.cpu.dtb.read_accesses                149963078                       # DTB read accesses
+system.cpu.dtb.write_hits                    57322555                       # DTB write hits
+system.cpu.dtb.write_misses                     67010                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57380566                       # DTB write accesses
-system.cpu.dtb.data_hits                    206614149                       # DTB hits
-system.cpu.dtb.data_misses                     603755                       # DTB misses
+system.cpu.dtb.write_accesses                57389565                       # DTB write accesses
+system.cpu.dtb.data_hits                    206716862                       # DTB hits
+system.cpu.dtb.data_misses                     635781                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207217904                       # DTB accesses
-system.cpu.itb.fetch_hits                   225746689                       # ITB hits
+system.cpu.dtb.data_accesses                207352643                       # DTB accesses
+system.cpu.itb.fetch_hits                   226799477                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               225746737                       # ITB accesses
+system.cpu.itb.fetch_accesses               226799525                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -346,71 +319,187 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        818759407                       # number of cpu cycles simulated
+system.cpu.numCycles                        822006022                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13148655                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12977706                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.338057                       # CPI: cycles per instruction
-system.cpu.ipc                               0.747352                       # IPC: instructions per cycle
-system.cpu.tickCycles                       736857348                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        81902059                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements              3155                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.246910                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           225741705                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4984                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45293.279494                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.343363                       # CPI: cycles per instruction
+system.cpu.ipc                               0.744400                       # IPC: instructions per cycle
+system.cpu.tickCycles                       741717254                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        80288768                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           2535461                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.779511                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202630719                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539557                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.789790                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1608227250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.779511                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.997993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          830                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3144                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         414705281                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414705281                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    146964513                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146964513                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     55666206                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666206                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     202630719                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202630719                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    202630719                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202630719                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1908315                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908315                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      1543828                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543828                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      3452143                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452143                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      3452143                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452143                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36427451000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36427451000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45003472500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  45003472500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  81430923500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  81430923500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  81430923500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81430923500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    148872828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148872828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     57210034                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    206082862                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206082862                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    206082862                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206082862                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.012818                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012818                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.016751                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016751                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.016751                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016751                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23588.514004                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23588.514004                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      2340066                       # number of writebacks
+system.cpu.dcache.writebacks::total           2340066                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143549                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143549                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769037                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769037                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       912586                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       912586                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       912586                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       912586                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764766                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764766                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774791                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       774791                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      2539557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      2539557                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539557                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30235919500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30235919500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21217351500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  21217351500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51453271000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  51453271000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51453271000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  51453271000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.011854                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011854                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.013543                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.012323                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012323                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.012323                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012323                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17133.104049                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17133.104049                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27384.612754                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27384.612754                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20260.726969                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20260.726969                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20260.726969                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20260.726969                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements              3180                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1117.063523                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226794468                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5009                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45277.394290                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.246910                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545042                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545042                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1117.063523                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545441                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545441                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         451498362                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        451498362                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    225741705                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       225741705                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     225741705                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        225741705                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    225741705                       # number of overall hits
-system.cpu.icache.overall_hits::total       225741705                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4984                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4984                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4984                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4984                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4984                       # number of overall misses
-system.cpu.icache.overall_misses::total          4984                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    227159500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    227159500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    227159500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    227159500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    227159500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    227159500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    225746689                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    225746689                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    225746689                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    225746689                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    225746689                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    225746689                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         453603963                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        453603963                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    226794468                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst         5009                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total          5009                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    228135750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    228135750                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total    228135750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    228135750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    228135750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    226799477                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    226799477                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    226799477                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    226799477                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    226799477                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    226799477                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45577.748796                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 45577.748796                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 45577.748796                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 45577.748796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 45577.748796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 45577.748796                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45545.168696                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 45545.168696                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 45545.168696                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 45545.168696                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 45545.168696                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 45545.168696                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,290 +508,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4984                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4984                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216090500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    216090500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216090500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    216090500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216090500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    216090500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5009                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5009                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5009                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5009                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5009                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5009                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    217013250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    217013250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    217013250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    217013250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    217013250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    217013250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43356.841894                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43356.841894                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43356.841894                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 43356.841894                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43356.841894                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 43356.841894                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43324.665602                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43324.665602                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43324.665602                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43324.665602                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43324.665602                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43324.665602                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1766375                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1766375                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2340053                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       778163                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       778163                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9968                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7419161                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7429129                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       318976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312294848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312613824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.l2cache.tags.replacements           347295                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29499.192462                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3711110                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           379718                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.773332                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     188708225000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21419.039362                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8080.153100                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.653657                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246587                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.900244                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32423                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18829                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989471                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         40234911                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40234911                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1593051                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1593051                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2340066                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2340066                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       571510                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571510                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      2164561                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164561                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      2164561                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164561                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       173378                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       173378                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       206627                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206627                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       380005                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        380005                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       380005                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       380005                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12684862500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  12684862500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14767694250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14767694250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  27452556750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27452556750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  27452556750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27452556750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766429                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1766429                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2340066                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2340066                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       778137                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       778137                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      2544566                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544566                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2544566                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544566                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098152                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.098152                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265541                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265541                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149340                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.149340                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149340                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.149340                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73163.045484                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73163.045484                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71470.302768                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71470.302768                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72242.619834                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72242.619834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72242.619834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72242.619834                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks       292570                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292570                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       173378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       173378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       380005                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       380005                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       380005                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       380005                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  10473281000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10473281000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12138501750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12138501750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  22611782750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22611782750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  22611782750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22611782750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098152                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098152                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265541                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265541                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149340                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149340                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149340                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149340                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60407.208527                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60407.208527                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58745.961322                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58745.961322                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59503.908501                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59503.908501                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59503.908501                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59503.908501                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        1766429                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766429                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2340066                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       778137                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       778137                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10018                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7419180                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7429198                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       320576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312295872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312616448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4884591                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      4884632                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4884591    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4884632    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4884591                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4782348500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4884632                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4782382000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8026500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       8065750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3891677000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           347305                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29490.835705                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3711078                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           379729                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.772964                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     188662245000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21414.068024                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8076.767680                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.653505                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246483                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.899989                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32424                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          224                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13174                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18828                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989502                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40234620                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40234620                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1592984                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1592984                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2340053                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2340053                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       571538                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571538                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      2164522                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164522                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      2164522                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164522                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst       173391                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       173391                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       206625                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206625                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       380016                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        380016                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       380016                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       380016                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12672589500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  12672589500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14785830500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14785830500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27458420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27458420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27458420000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27458420000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766375                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1766375                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2340053                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2340053                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       778163                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       778163                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      2544538                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544538                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2544538                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544538                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098162                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.098162                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265529                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265529                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149346                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149346                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149346                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149346                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73086.777860                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73086.777860                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71558.768300                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71558.768300                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72255.957644                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72255.957644                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72255.957644                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72255.957644                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292561                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292561                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       173391                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       173391                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206625                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206625                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       380016                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       380016                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       380016                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       380016                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  10460652500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10460652500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12167413500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12167413500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  22628066000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22628066000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  22628066000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22628066000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098162                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098162                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265529                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265529                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149346                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149346                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149346                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149346                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.846993                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.846993                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58886.453721                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58886.453721                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59545.034946                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59545.034946                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59545.034946                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59545.034946                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2535458                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.758418                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202542728                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539554                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.755236                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1608245250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.758418                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.997988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          828                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3146                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414529138                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414529138                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    146876552                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146876552                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     55666176                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666176                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     202542728                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202542728                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    202542728                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202542728                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      1908206                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908206                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      1543858                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543858                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      3452064                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3452064                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      3452064                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3452064                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36392982500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36392982500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45181402750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  45181402750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  81574385250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  81574385250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  81574385250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  81574385250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    148784758                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148784758                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    205994792                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    205994792                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    205994792                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    205994792                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.012825                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026986                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026986                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.016758                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016758                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.016758                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.016758                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19071.831081                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19071.831081                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29265.258042                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29265.258042                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23630.612077                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23630.612077                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23630.612077                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23630.612077                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2340053                       # number of writebacks
-system.cpu.dcache.writebacks::total           2340053                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143482                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143482                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769028                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769028                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       912510                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       912510                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       912510                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       912510                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764724                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764724                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774830                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       774830                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      2539554                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539554                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      2539554                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539554                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30222763750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30222763750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21236491750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  21236491750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51459255500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  51459255500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51459255500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  51459255500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.011861                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011861                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.013544                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.012328                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012328                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.012328                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012328                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.respLayer1.occupancy    3891670500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq              173378                       # Transaction distribution
+system.membus.trans_dist::ReadResp             173378                       # Transaction distribution
+system.membus.trans_dist::Writeback            292570                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206627                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206627                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052580                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1052580                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43044800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43044800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            672575                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  672575    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              672575                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          3222733000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3617871750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index c27afafd9..940b25691 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,101 +1,101 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.361881                       # Number of seconds simulated
-sim_ticks                                361880862500                       # Number of ticks simulated
-final_tick                               361880862500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.365348                       # Number of seconds simulated
+sim_ticks                                365347511000                       # Number of ticks simulated
+final_tick                               365347511000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 214559                       # Simulator instruction rate (inst/s)
-host_op_rate                                   232396                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              153272119                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259716                       # Number of bytes of host memory used
-host_seconds                                  2361.04                       # Real time elapsed on the host
+host_inst_rate                                 224796                       # Simulator instruction rate (inst/s)
+host_op_rate                                   243484                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              162123009                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256924                       # Number of bytes of host memory used
+host_seconds                                  2253.52                       # Real time elapsed on the host
 sim_insts                                   506582155                       # Number of instructions simulated
 sim_ops                                     548695378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           9221824                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9221824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6177344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6177344                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             144091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                144091                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96521                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96521                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             25483039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25483039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          612622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             612622                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          17070104                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               17070104                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          17070104                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            25483039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42553143                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        144091                       # Number of read requests accepted
-system.physmem.writeReqs                        96521                       # Number of write requests accepted
-system.physmem.readBursts                      144091                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      96521                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9215168                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6176128                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9221824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6177344                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst           9224896                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9224896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6179008                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6179008                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             144139                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                144139                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96547                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96547                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             25249648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25249648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          605758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             605758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          16912687                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               16912687                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          16912687                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            25249648                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42162335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        144139                       # Number of read requests accepted
+system.physmem.writeReqs                        96547                       # Number of write requests accepted
+system.physmem.readBursts                      144139                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      96547                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9218048                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6177856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9224896                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6179008                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9338                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8967                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9003                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8705                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9445                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9343                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8943                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8100                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8560                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8672                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8773                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9480                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9371                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9512                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8706                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9069                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6189                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9344                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8969                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8998                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8704                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9453                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9341                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8940                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8571                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8677                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8772                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9476                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9379                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9523                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8710                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9074                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6191                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                6093                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6008                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5816                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6159                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6173                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6014                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6006                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5817                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6161                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6171                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6013                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                5494                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5724                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5818                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5728                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5821                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6447                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6306                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6267                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5992                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6041                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6446                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6308                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6280                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5994                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6045                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    361880833500                       # Total gap between requests
+system.physmem.totGap                    365347483000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  144091                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  144139                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96521                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143620                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       348                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  96547                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       351                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5626                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
@@ -189,123 +189,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64681                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      237.949073                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     157.463319                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     243.404639                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24397     37.72%     37.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18169     28.09%     65.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6808     10.53%     76.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7802     12.06%     88.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2168      3.35%     91.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1166      1.80%     93.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          777      1.20%     94.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          613      0.95%     95.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2781      4.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64681                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5584                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.784921                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      381.788967                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5580     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        64866                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.344433                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     157.101707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     243.291878                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24488     37.75%     37.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18300     28.21%     65.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6859     10.57%     76.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7791     12.01%     88.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2064      3.18%     91.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1161      1.79%     93.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          764      1.18%     94.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          681      1.05%     95.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2758      4.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64866                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5569                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.862992                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      382.285392                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5565     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5584                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5584                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.281877                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.171400                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.885179                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5428     97.21%     97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              84      1.50%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              28      0.50%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              20      0.36%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               9      0.16%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               7      0.13%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               2      0.04%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               2      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5569                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5569                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.333273                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.210704                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.188900                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5418     97.29%     97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              79      1.42%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              23      0.41%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              20      0.36%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               9      0.16%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               7      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               5      0.09%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               5      0.09%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::52-55               1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::160-163             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5584                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1580318000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4280074250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    719935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10975.42                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            5569                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1570268250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4270868250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    720160000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10902.22                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29725.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.46                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          17.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.48                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       17.07                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29652.22                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          16.91                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       16.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     111153                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64649                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1504001.60                       # Average gap between requests
-system.physmem.pageHitRate                      73.10                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     254039828500                       # Time in different power states
-system.physmem.memoryStateTime::REF       12083760000                       # Time in different power states
+system.physmem.avgWrQLen                        19.86                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110988                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64704                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.06                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  67.02                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1517942.39                       # Average gap between requests
+system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     256543365500                       # Time in different power states
+system.physmem.memoryStateTime::REF       12199720000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       95752175500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       96603610750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 246146040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 242562600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 134305875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 132350625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                560164800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                562497000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               310469760                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               314539200                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           23635834560                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           23635834560                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           46793455740                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           46253268450                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          176077509750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          176551358250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            247757886525                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            247692410685                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             684.652353                       # Core power per rank (mW)
-system.physmem.averagePower::1             684.471418                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq               43225                       # Transaction distribution
-system.membus.trans_dist::ReadResp              43225                       # Transaction distribution
-system.membus.trans_dist::Writeback             96521                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100866                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100866                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384703                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 384703                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15399168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15399168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            240612                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  240612    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              240612                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1075136000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1362650250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               132262855                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98270441                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6551317                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68771118                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64694090                       # Number of BTB hits
+system.physmem.actEnergy::0                 246584520                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 243719280                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 134545125                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 132981750                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                560422200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                562972800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               310625280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               314778960                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           23862652320                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           23862652320                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           47112370740                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           46678345380                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          177881368500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          178262092500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            250108568685                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            250057542990                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             684.578732                       # Core power per rank (mW)
+system.physmem.averagePower::1             684.439068                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               132580026                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98506360                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6554090                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             69003825                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64853184                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.071598                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9992883                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              17801                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.984912                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                10016062                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              17737                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -391,71 +366,195 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        723761725                       # number of cpu cycles simulated
+system.cpu.numCycles                        730695022                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506582155                       # Number of instructions committed
 system.cpu.committedOps                     548695378                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      14127209                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13461717                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.428715                       # CPI: cycles per instruction
-system.cpu.ipc                               0.699929                       # IPC: instructions per cycle
-system.cpu.tickCycles                       687792337                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        35969388                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             17682                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1187.679119                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           200328523                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19553                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10245.411088                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.442402                       # CPI: cycles per instruction
+system.cpu.ipc                               0.693288                       # IPC: instructions per cycle
+system.cpu.tickCycles                       695775254                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        34919768                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1139848                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.076883                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171283127                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1143944                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.730343                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4867376000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.076883                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.993915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3502                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         346820764                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346820764                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    114767369                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114767369                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     53538676                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538676                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     168306045                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168306045                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168306045                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168306045                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       854653                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854653                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       700630                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700630                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1555283                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1555283                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1555283                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1555283                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  13708895232                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13708895232                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20586763000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20586763000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  34295658232                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34295658232                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  34295658232                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34295658232                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    115622022                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115622022                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    169861328                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169861328                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    169861328                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169861328                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007392                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.009156                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009156                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.009156                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009156                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22051.072526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22051.072526                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      1068569                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068569                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        66869                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66869                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344470                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344470                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       411339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       411339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       411339                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411339                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       787784                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       787784                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356160                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356160                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1143944                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1143944                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1143944                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1143944                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11256226015                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11256226015                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10106063500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10106063500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21362289515                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21362289515                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21362289515                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  21362289515                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006735                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006735                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14288.467416                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14288.467416                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28375.065982                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28375.065982                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18674.244119                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18674.244119                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements             17642                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1190.521713                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           200940130                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             19514                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10297.229169                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1187.679119                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.579921                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.579921                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1871                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1190.521713                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.581309                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.581309                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           64                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          304                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1402                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.913574                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         400715705                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        400715705                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    200328523                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       200328523                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     200328523                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        200328523                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    200328523                       # number of overall hits
-system.cpu.icache.overall_hits::total       200328523                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19553                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19553                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19553                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19553                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19553                       # number of overall misses
-system.cpu.icache.overall_misses::total         19553                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    468017498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    468017498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    468017498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    468017498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    468017498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    468017498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    200348076                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    200348076                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    200348076                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    200348076                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    200348076                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    200348076                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23935.840945                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23935.840945                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          301                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1411                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         401938802                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        401938802                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    200940130                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       200940130                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     200940130                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        200940130                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    200940130                       # number of overall hits
+system.cpu.icache.overall_hits::total       200940130                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19514                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19514                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19514                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19514                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19514                       # number of overall misses
+system.cpu.icache.overall_misses::total         19514                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    467407495                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    467407495                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    467407495                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    467407495                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    467407495                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    467407495                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    200959644                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    200959644                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    200959644                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    200959644                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    200959644                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    200959644                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23952.418520                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23952.418520                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23952.418520                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23952.418520                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23952.418520                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23952.418520                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -464,44 +563,164 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19553                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        19553                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        19553                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        19553                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        19553                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        19553                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    427542502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    427542502                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    427542502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    427542502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    427542502                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    427542502                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21865.826318                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19514                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        19514                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::total        19514                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    426999505                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    426999505                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    426999505                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    426999505                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    426999505                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    426999505                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         806891                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        806891                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1068421                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356400                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356400                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39106                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3355897                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3395003                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1251392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141578176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          142829568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.l2cache.tags.replacements           111385                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27648.726753                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1684688                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           142574                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            11.816236                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     163201810500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4124.641306                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.717898                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125874                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.843772                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31189                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4940                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25859                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951813                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18355203                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18355203                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       763758                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         763758                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1068569                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1068569                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       255544                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.inst      1019302                       # number of demand (read+write) hits
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3231564500                       # number of ReadReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst  10428398500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.inst       807045                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::writebacks      1068569                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356413                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total      1163458                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053636                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.053636                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283012                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.283012                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123903                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123903                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123903                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123903                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        96547                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96547                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43270                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        43270                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100869                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100869                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       144139                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       144139                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total       144139                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2682518500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2682518500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5916082000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5916082000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8598600500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8598600500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8598600500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8598600500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053615                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053615                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283012                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283012                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123888                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123888                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq         807045                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        807045                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1068569                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356413                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356413                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39028                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356457                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3395485                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1248896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141600832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          142849728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2231712                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      2232027                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
@@ -510,262 +729,41 @@ system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Re
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            2231712    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            2232027    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2231712                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2184277000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2232027                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2184582500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      30013998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      29960995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1744433986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1744681985                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           111337                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27632.941712                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1684357                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           142526                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            11.817893                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     162521333500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4108.167019                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.717919                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125371                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.843290                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31189                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4930                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25866                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951813                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18352622                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18352622                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       763650                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         763650                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1068421                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1068421                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       255534                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255534                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1019184                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1019184                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1019184                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1019184                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        43241                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        43241                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       100866                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100866                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       144107                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        144107                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       144107                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       144107                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3220591000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3220591000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7211196000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7211196000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  10431787000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10431787000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  10431787000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10431787000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       806891                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       806891                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1068421                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1068421                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356400                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       356400                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1163291                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1163291                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1163291                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1163291                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053590                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.053590                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283013                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.283013                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123879                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123879                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123879                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123879                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96521                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96521                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43225                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        43225                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100866                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100866                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       144091                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       144091                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       144091                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       144091                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2672436250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2672436250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5933940000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5933940000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8606376250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8606376250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8606376250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8606376250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053570                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053570                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283013                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283013                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123865                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123865                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123865                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123865                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1139642                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4071.128930                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169306917                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1143738                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            148.029459                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4807181250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.128930                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.993928                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993928                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3499                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         342867294                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        342867294                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    112791129                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       112791129                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     53538706                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538706                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     166329835                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166329835                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    166329835                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166329835                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       854261                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        854261                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       700600                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700600                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1554861                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1554861                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1554861                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1554861                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  13692452733                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13692452733                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20709081750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20709081750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  34401534483                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34401534483                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  34401534483                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34401534483                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    113645390                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    113645390                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    167884696                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167884696                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    167884696                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167884696                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007517                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007517                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012917                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.009261                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009261                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.009261                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009261                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22125.151048                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22125.151048                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1068421                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068421                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        66670                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66670                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344453                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344453                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       411123                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411123                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       411123                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411123                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       787591                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       787591                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356147                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356147                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1143738                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1143738                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1143738                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1143738                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11243518014                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11243518014                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10120311000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10120311000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21363829014                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21363829014                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21363829014                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21363829014                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006930                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006930                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006566                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006813                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006813                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq               43270                       # Transaction distribution
+system.membus.trans_dist::ReadResp              43270                       # Transaction distribution
+system.membus.trans_dist::Writeback             96547                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100869                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100869                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384825                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 384825                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15403904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15403904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            240686                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  240686    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              240686                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1081853000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1366563500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index fb931db93..ca5c08420 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,58 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.220941                       # Number of seconds simulated
-sim_ticks                                220941341500                       # Number of ticks simulated
-final_tick                               220941341500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.226819                       # Number of seconds simulated
+sim_ticks                                226818771000                       # Number of ticks simulated
+final_tick                               226818771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 295257                       # Simulator instruction rate (inst/s)
-host_op_rate                                   295257                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              163632311                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243348                       # Number of bytes of host memory used
-host_seconds                                  1350.23                       # Real time elapsed on the host
+host_inst_rate                                 285609                       # Simulator instruction rate (inst/s)
+host_op_rate                                   285609                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              162496290                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242892                       # Number of bytes of host memory used
+host_seconds                                  1395.84                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            504000                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               504000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       249408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          249408                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               7875                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7875                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2281148                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2281148                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1128843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1128843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2281148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2281148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7875                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            503872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               503872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       249280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          249280                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               7873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7873                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2221474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2221474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1099027                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1099027                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2221474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2221474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7873                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7875                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7873                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   504000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   503872                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    504000                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    503872                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 551                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 675                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 676                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 633                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 475                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 478                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 564                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 563                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 560                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 471                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 469                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 437                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                324                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                430                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                556                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                473                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                423                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                424                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    220941260000                       # Total gap between requests
+system.physmem.totGap                    226818689500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7875                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7873                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -86,9 +86,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6821                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       971                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6808                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       980                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1518                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      330.160738                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     197.894458                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.998951                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            519     34.19%     34.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          336     22.13%     56.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          186     12.25%     68.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          110      7.25%     75.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           56      3.69%     79.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           56      3.69%     83.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           37      2.44%     85.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      1.84%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          190     12.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1518                       # Bytes accessed per row activation
-system.physmem.totQLat                       53358500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 201014750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     39375000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6775.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1523                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      329.076822                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     197.330219                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.077184                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            516     33.88%     33.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          348     22.85%     56.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          193     12.67%     69.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          104      6.83%     76.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           58      3.81%     80.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           41      2.69%     82.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           32      2.10%     84.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           40      2.63%     87.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          191     12.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1523                       # Bytes accessed per row activation
+system.physmem.totQLat                       50615750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 198234500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     39365000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6429.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25525.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.28                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25179.03                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.22                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.22                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -212,88 +212,65 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6348                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6341                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.61                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.54                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28056033.02                       # Average gap between requests
-system.physmem.pageHitRate                      80.61                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     211835989750                       # Time in different power states
-system.physmem.memoryStateTime::REF        7377500000                       # Time in different power states
+system.physmem.avgGap                     28809690.02                       # Average gap between requests
+system.physmem.pageHitRate                      80.54                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     217525128250                       # Time in different power states
+system.physmem.memoryStateTime::REF        7573800000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1721627750                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1714919250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   6743520                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   4717440                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   3679500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2574000                       # Energy for precharge commands per rank (pJ)
+system.physmem.actEnergy::0                   6698160                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                   4808160                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                   3654750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                   2623500                       # Energy for precharge commands per rank (pJ)
 system.physmem.readEnergy::0                 34164000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 26902200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                 26910000                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           14430390000                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           14430390000                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            5688842535                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            5444083395                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          127570849500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          127785550500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            147734669055                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            147694217535                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.679022                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.495929                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                4737                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3138                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3138                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       504000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  504000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7875                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7875    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7875                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9512000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           74011500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                46221231                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26710053                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1012987                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25408308                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21330923                       # Number of BTB hits
+system.physmem.refreshEnergy::0           14814352800                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           14814352800                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0            5823022815                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1            5572463355                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          130980318750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          131200107750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            151662211275                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            151621265565                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.664178                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.483652                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                46273762                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26730646                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1017469                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25595417                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21359944                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.952552                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8326726                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             83.452221                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8341649                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95595776                       # DTB read hits
-system.cpu.dtb.read_misses                        118                       # DTB read misses
+system.cpu.dtb.read_hits                     95585470                       # DTB read hits
+system.cpu.dtb.read_misses                        115                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95595894                       # DTB read accesses
-system.cpu.dtb.write_hits                    73604420                       # DTB write hits
-system.cpu.dtb.write_misses                       858                       # DTB write misses
+system.cpu.dtb.read_accesses                 95585585                       # DTB read accesses
+system.cpu.dtb.write_hits                    73606436                       # DTB write hits
+system.cpu.dtb.write_misses                       857                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73605278                       # DTB write accesses
-system.cpu.dtb.data_hits                    169200196                       # DTB hits
-system.cpu.dtb.data_misses                        976                       # DTB misses
+system.cpu.dtb.write_accesses                73607293                       # DTB write accesses
+system.cpu.dtb.data_hits                    169191906                       # DTB hits
+system.cpu.dtb.data_misses                        972                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                169201172                       # DTB accesses
-system.cpu.itb.fetch_hits                    98242303                       # ITB hits
-system.cpu.itb.fetch_misses                      1225                       # ITB misses
+system.cpu.dtb.data_accesses                169192878                       # DTB accesses
+system.cpu.itb.fetch_hits                    98781228                       # ITB hits
+system.cpu.itb.fetch_misses                      1237                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98243528                       # ITB accesses
+system.cpu.itb.fetch_accesses                98782465                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,253 +284,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        441882683                       # number of cpu cycles simulated
+system.cpu.numCycles                        453637542                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4446127                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4467797                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.108407                       # CPI: cycles per instruction
-system.cpu.ipc                               0.902196                       # IPC: instructions per cycle
-system.cpu.tickCycles                       437732110                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         4150573                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements              3195                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1919.708570                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98237130                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5173                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18990.359559                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.708570                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937358                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937358                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          198                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          398                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         196489779                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        196489779                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98237130                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98237130                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98237130                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98237130                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98237130                       # number of overall hits
-system.cpu.icache.overall_hits::total        98237130                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5173                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5173                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5173                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5173                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5173                       # number of overall misses
-system.cpu.icache.overall_misses::total          5173                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    293560000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    293560000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    293560000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    293560000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    293560000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    293560000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98242303                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98242303                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98242303                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98242303                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98242303                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98242303                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56748.501836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56748.501836                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5173                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5173                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5173                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5173                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281592000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281592000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281592000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281592000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           6139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          6139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3199                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3199                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19330                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             639488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9992                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               9992    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9992                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5650000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8570500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6975500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4427.627399                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               1491                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5274                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.282708                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   373.083919                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4054.543479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011386                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123735                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.135120                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4444                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160950                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            88409                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           88409                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         1402                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           1402                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1463                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1463                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4737                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4737                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         3138                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3138                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7875                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7875                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7875                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7875                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    325756750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    325756750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    212895750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    212895750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    538652500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    538652500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    538652500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    538652500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6139                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         6139                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         3199                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3199                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         9338                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9338                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         9338                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9338                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.771624                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.771624                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.980932                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.980932                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843328                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.843328                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843328                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843328                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4737                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4737                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         3138                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3138                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7875                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7875                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7875                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7875                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266376250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266376250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    173100750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    173100750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    439477000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    439477000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    439477000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    439477000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771624                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771624                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980932                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980932                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843328                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.cpi                               1.137893                       # CPI: cycles per instruction
+system.cpu.ipc                               0.878818                       # IPC: instructions per cycle
+system.cpu.tickCycles                       450174331                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3463211                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.748199                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168007181                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.955317                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168028615                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40337.858583                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40343.004802                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.748199                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.803649                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803649                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.955317                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.803700                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803700                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
@@ -561,40 +311,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          216
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336032765                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336032765                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     94492394                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94492394                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     73514787                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514787                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     168007181                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168007181                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    168007181                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168007181                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst         1176                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1176                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst         5943                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5943                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses         336075633                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336075633                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     94513823                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94513823                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     73514792                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514792                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     168028615                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168028615                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168028615                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168028615                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst         1181                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1181                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         5938                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5938                       # number of WriteReq misses
 system.cpu.dcache.demand_misses::cpu.inst         7119                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total           7119                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst         7119                       # number of overall misses
 system.cpu.dcache.overall_misses::total          7119                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     81019000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     81019000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    393760000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    393760000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    474779000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    474779000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    474779000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    474779000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     94493570                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94493570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     81052500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     81052500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    391543250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    391543250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    472595750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    472595750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    472595750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    472595750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     94515004                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94515004                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    168014300                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168014300                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    168014300                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168014300                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst    168035734                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168035734                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    168035734                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168035734                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000081                       # miss rate for WriteReq accesses
@@ -603,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66691.810648                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66691.810648                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66385.131339                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66385.131339                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -621,30 +371,30 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2746                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2746                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          211                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2743                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2743                       # number of WriteReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.inst         2954                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total         2954                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.inst         2954                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total         2954                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3197                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3197                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          970                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          970                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3195                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3195                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.inst         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64462750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     64462750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    216604250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    216604250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    281067000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    281067000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    281067000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    281067000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64327500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     64327500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    214316000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    214316000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    278643500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    278643500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    278643500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    278643500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for WriteReq accesses
@@ -653,14 +403,264 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67752.345949                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67752.345949                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67483.073229                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67483.073229                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67483.073229                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67483.073229                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements              3196                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1918.781810                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            98776054                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5174                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          19090.849246                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1918.781810                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.936905                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.936905                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1281                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         197567630                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        197567630                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     98776054                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        98776054                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      98776054                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         98776054                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     98776054                       # number of overall hits
+system.cpu.icache.overall_hits::total        98776054                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5174                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5174                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5174                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5174                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5174                       # number of overall misses
+system.cpu.icache.overall_misses::total          5174                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    293010500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    293010500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    293010500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    293010500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    293010500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    293010500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     98781228                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     98781228                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     98781228                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     98781228                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     98781228                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     98781228                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56631.329726                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56631.329726                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5174                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5174                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5174                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5174                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5174                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5174                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281053500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281053500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281053500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281053500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281053500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281053500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         4426.924710                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               1494                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5273                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.283330                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   373.138333                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4053.786377                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011387                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123712                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.135099                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5273                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          611                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4443                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160919                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            88415                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           88415                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1405                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1405                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           61                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1466                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1466                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1466                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1466                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4736                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4736                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         3137                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7873                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7873                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7873                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7873                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    324986750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    324986750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    210671750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    210671750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    535658500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    535658500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    535658500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    535658500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6141                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         6141                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         3198                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         9339                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9339                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         9339                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9339                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.771210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.771210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.980926                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843024                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.843024                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843024                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.843024                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4736                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4736                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         3137                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3137                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7873                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7873                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7873                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7873                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    265636250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    265636250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    170998250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    170998250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    436634500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    436634500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    436634500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    436634500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980926                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843024                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843024                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843024                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843024                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq           6141                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          6141                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10348                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8984                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19332                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             639552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples         9993                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               9993    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total           9993                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        5650500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       8565500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       6972500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                4736                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4736                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3137                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3137                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15746                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15746                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       503872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  503872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              7873                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7873    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                7873                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9387500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           73875500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 3f279951b..a544f3c3c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,38 +1,38 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.212377                       # Number of seconds simulated
-sim_ticks                                212377413000                       # Number of ticks simulated
-final_tick                               212377413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.216828                       # Number of seconds simulated
+sim_ticks                                216828260500                       # Number of ticks simulated
+final_tick                               216828260500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 195363                       # Simulator instruction rate (inst/s)
-host_op_rate                                   234555                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              151959329                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264884                       # Number of bytes of host memory used
-host_seconds                                  1397.59                       # Real time elapsed on the host
+host_inst_rate                                 172164                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206702                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              136721287                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262128                       # Number of bytes of host memory used
+host_seconds                                  1585.91                       # Real time elapsed on the host
 sim_insts                                   273037856                       # Number of instructions simulated
 sim_ops                                     327812213                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            485312                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219008                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               7583                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2285139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2285139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1031221                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1031221                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2285139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2285139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7583                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            485440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               485440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219072                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               7585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7585                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2238823                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2238823                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1010348                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1010348                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2238823                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2238823                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7585                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7583                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7585                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485312                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485440                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485312                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485440                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -43,16 +43,16 @@ system.physmem.perBankRdBursts::2                 628                       # Pe
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 173                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 172                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 311                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                554                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                705                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                637                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                541                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    212377186000                       # Total gap between requests
+system.physmem.totGap                    216828031000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7583                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7585                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -86,8 +86,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6625                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6628                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       896                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      322.691589                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.527839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.553355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            554     36.98%     36.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          333     22.23%     59.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          160     10.68%     69.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           67      4.47%     74.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           72      4.81%     79.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           61      4.07%     83.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           43      2.87%     86.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           33      2.20%     88.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          175     11.68%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1498                       # Bytes accessed per row activation
-system.physmem.totQLat                       52768250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 194949500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37915000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6958.76                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1505                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      321.360797                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.317321                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.826076                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            548     36.41%     36.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          349     23.19%     59.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          163     10.83%     70.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           68      4.52%     74.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           69      4.58%     79.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           60      3.99%     83.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      2.19%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           33      2.19%     87.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          182     12.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1505                       # Bytes accessed per row activation
+system.physmem.totQLat                       50683250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 192902000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37925000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6682.04                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25708.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25432.04                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -212,68 +212,45 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6077                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6073                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.14                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.07                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28007013.85                       # Average gap between requests
-system.physmem.pageHitRate                      80.14                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     202838268250                       # Time in different power states
-system.physmem.memoryStateTime::REF        7091500000                       # Time in different power states
+system.physmem.avgGap                     28586424.65                       # Average gap between requests
+system.physmem.pageHitRate                      80.07                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     207228229000                       # Time in different power states
+system.physmem.memoryStateTime::REF        7240220000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        2441586750                       # Time in different power states
+system.physmem.memoryStateTime::ACT        2356912000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   4921560                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   6380640                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   2685375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   3481500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 29897400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 28977000                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                   5012280                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                   6342840                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                   2734875                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                   3460875                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                 29905200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                 29000400                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           13870974000                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           13870974000                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            5549858010                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            5731608780                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          122553840750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          122394410250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            142012177095                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            142035832170                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.700966                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.812352                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                4730                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4730                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2853                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2853                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7583                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7583    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7583                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8812500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           70869750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                33146132                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17115100                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1582628                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18038080                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15622031                       # Number of BTB hits
+system.physmem.refreshEnergy::0           14161870320                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           14161870320                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0            5651949285                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1            5745162240                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          125136528000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          125054762250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            144987999960                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            145000598925                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.689925                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.748031                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                33221230                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17174007                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1583983                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17995686                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15666979                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             86.605842                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6627212                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             87.059638                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6611215                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -359,314 +336,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        424754826                       # number of cpu cycles simulated
+system.cpu.numCycles                        433656521                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037856                       # Number of instructions committed
 system.cpu.committedOps                     327812213                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4318159                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4064410                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.555663                       # CPI: cycles per instruction
-system.cpu.ipc                               0.642813                       # IPC: instructions per cycle
-system.cpu.tickCycles                       420995875                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3758951                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             36952                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.941243                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            73208046                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38889                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1882.487233                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.941243                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939913                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939913                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1488                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146532761                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146532761                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     73208046                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        73208046                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      73208046                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         73208046                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     73208046                       # number of overall hits
-system.cpu.icache.overall_hits::total        73208046                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38890                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38890                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38890                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38890                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38890                       # number of overall misses
-system.cpu.icache.overall_misses::total         38890                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    705005996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    705005996                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    705005996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    705005996                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    705005996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    705005996                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     73246936                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     73246936                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     73246936                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     73246936                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     73246936                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     73246936                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000531                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000531                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000531                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000531                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000531                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000531                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18128.207663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18128.207663                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38890                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38890                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        38890                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        38890                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        38890                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        38890                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    625833004                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    625833004                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    625833004                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    625833004                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    625833004                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    625833004                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000531                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000531                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000531                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          40531                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         40530                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1009                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         2869                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         2869                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77779                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10029                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             87808                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2488896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2842112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        44409                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5              44409    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          44409                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       23213500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      59030996                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7495960                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4198.136942                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              35837                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.349575                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.492030                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3844.644913                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010788                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.117329                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.128117                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5644                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           363785                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          363785                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        35758                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          35758                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks         1009                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1009                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        35774                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           35774                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        35774                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          35774                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4773                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4773                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         2853                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2853                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7626                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7626                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7626                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7626                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    328394750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    328394750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    194183750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    194183750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    522578500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    522578500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    522578500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    522578500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        40531                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        40531                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks         1009                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1009                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         2869                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         2869                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        43400                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        43400                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        43400                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        43400                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.117762                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.117762                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.994423                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994423                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.175714                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.175714                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.175714                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.175714                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           43                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           43                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           43                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           43                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           43                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           43                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4730                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4730                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         2853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7583                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7583                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7583                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7583                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266721500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266721500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    158370750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158370750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    425092250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    425092250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    425092250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    425092250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.116701                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116701                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994423                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994423                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174724                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.174724                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174724                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.174724                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements              1353                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.890938                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168774540                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4510                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37422.292683                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.588265                       # CPI: cycles per instruction
+system.cpu.ipc                               0.629618                       # IPC: instructions per cycle
+system.cpu.tickCycles                       430211091                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3445430                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements              1354                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3086.009332                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168783807                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37416.051208                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3085.890938                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.753391                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753391                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3086.009332                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.753420                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753420                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          671                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2433                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337568172                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337568172                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     86705299                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86705299                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     82047451                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047451                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         337586705                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337586705                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     86714567                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86714567                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     82047450                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047450                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.inst        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     168752750                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168752750                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    168752750                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168752750                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst         2065                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          2065                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst         5226                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5226                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst         7291                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7291                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst         7291                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7291                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst    127168958                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    127168958                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    358839500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    358839500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    486008458                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    486008458                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    486008458                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    486008458                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     86707364                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86707364                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.inst     168762017                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168762017                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168762017                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168762017                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst         2063                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          2063                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         5227                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5227                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         7290                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7290                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         7290                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst    126122956                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    126122956                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    360338500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    360338500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    486461456                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    486461456                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    486461456                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    486461456                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     86716630                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86716630                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    168760041                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168760041                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    168760041                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168760041                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst    168769307                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168769307                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    168769307                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168769307                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000064                       # miss rate for WriteReq accesses
@@ -675,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66658.683034                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66658.683034                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66729.966529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66729.966529                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -691,32 +429,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1009                       # number of writebacks
-system.cpu.dcache.writebacks::total              1009                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks         1010                       # number of writebacks
+system.cpu.dcache.writebacks::total              1010                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          422                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          422                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2357                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total         2357                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst         2781                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2781                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst         2781                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2781                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst         2779                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2779                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst         2779                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2779                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.inst         1641                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total         1641                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         2869                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2869                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         4510                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4510                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         4510                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4510                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst    100686290                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    100686290                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    197251750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    197251750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    297938040                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    297938040                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    297938040                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    297938040                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         2870                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst         4511                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4511                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         4511                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     99847542                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     99847542                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    197786250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    197786250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    297633792                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    297633792                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    297633792                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    297633792                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for WriteReq accesses
@@ -725,14 +463,276 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements             36927                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1924.993605                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            73270396                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38864                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1885.302491                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.993605                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939938                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939938                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         146657386                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146657386                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     73270396                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        73270396                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      73270396                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         73270396                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     73270396                       # number of overall hits
+system.cpu.icache.overall_hits::total        73270396                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38865                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38865                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38865                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38865                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38865                       # number of overall misses
+system.cpu.icache.overall_misses::total         38865                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    703294747                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    703294747                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    703294747                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    703294747                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    703294747                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    703294747                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     73309261                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     73309261                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     73309261                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     73309261                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     73309261                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     73309261                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000530                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000530                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000530                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000530                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000530                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000530                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18095.838081                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18095.838081                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38865                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        38865                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        38865                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        38865                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        38865                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        38865                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    624165253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    624165253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    624165253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    624165253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    624165253                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    624165253                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000530                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000530                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000530                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         4198.559652                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              35809                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5647                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.341243                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.760812                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3844.798840                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010796                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.117334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.128130                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5647                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1252                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172333                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           363605                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          363605                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        35730                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          35730                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           16                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        35746                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           35746                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        35746                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          35746                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4776                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4776                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         2854                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7630                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7630                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7630                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    326194750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    326194750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    194720750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    194720750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    520915500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    520915500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    520915500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    520915500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        40506                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        40506                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1010                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         2870                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        43376                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        43376                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        43376                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        43376                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.117908                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.117908                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.994425                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.175904                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.175904                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.175904                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.175904                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           45                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           45                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           45                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           45                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4731                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4731                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         2854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7585                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7585                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7585                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7585                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    264387500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    264387500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    158755250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158755250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    423142750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    423142750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    423142750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    423142750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.116798                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116798                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994425                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174866                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.174866                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174866                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.174866                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq          40506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40505                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77729                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10032                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             87761                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2487296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2840640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        44386                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5              44386    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total          44386                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       23203000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      58996747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       7500208                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                4731                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4731                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15170                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15170                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              7585                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7585    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                7585                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8963500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           71030250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index ba9298aae..3373b2092 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,65 +1,65 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.555533                       # Number of seconds simulated
-sim_ticks                                555532734000                       # Number of ticks simulated
-final_tick                               555532734000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.559967                       # Number of seconds simulated
+sim_ticks                                559966999500                       # Number of ticks simulated
+final_tick                               559966999500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 316770                       # Simulator instruction rate (inst/s)
-host_op_rate                                   316770                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              189468265                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247360                       # Number of bytes of host memory used
-host_seconds                                  2932.06                       # Real time elapsed on the host
+host_inst_rate                                 393705                       # Simulator instruction rate (inst/s)
+host_op_rate                                   393705                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              237364888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245892                       # Number of bytes of host memory used
+host_seconds                                  2359.10                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          18657152                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18657152                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       186688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst          18657216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18657216                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       186816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          186816                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             291518                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291518                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             291519                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291519                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             33584253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33584253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          336052                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             336052                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7682197                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7682197                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7682197                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            33584253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41266450                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291518                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst             33318421                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33318421                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          333620                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             333620                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7621363                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7621363                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7621363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            33318421                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40939784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291519                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      291518                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291519                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18640064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     17088                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18657152                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18639936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     17280                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266560                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18657216                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      267                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      270                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               17939                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18284                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18304                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18254                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               17935                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18289                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18306                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18248                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18163                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18248                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18324                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18239                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18320                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               18299                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               18226                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18216                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18389                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18256                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18039                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              17980                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18104                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18219                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18391                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18259                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18042                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              17977                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18106                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4190                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4189                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    555532658500                       # Total gap between requests
+system.physmem.totGap                    559966923500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291518                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291519                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -93,9 +93,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290760                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       465                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290734                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4043                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     4045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4042                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -189,137 +189,113 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       105079                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      217.968119                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     139.907625                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     270.030152                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          40113     38.17%     38.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        44071     41.94%     80.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8455      8.05%     88.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          717      0.68%     88.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          543      0.52%     89.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          672      0.64%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1241      1.18%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1153      1.10%     92.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8114      7.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         105079                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4044                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.423096                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.196398                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      785.521839                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4037     99.83%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            2      0.05%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383            3      0.07%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       104630                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      218.912664                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     140.833166                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     269.609760                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          39535     37.79%     37.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43904     41.96%     79.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8672      8.29%     88.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          695      0.66%     88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          728      0.70%     89.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          763      0.73%     90.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1332      1.27%     91.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          808      0.77%     92.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8193      7.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         104630                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4042                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.196437                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.192949                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      784.958027                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4035     99.83%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383            4      0.10%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-18431            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4044                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4044                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.485163                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.463667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.859123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3065     75.79%     75.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                975     24.11%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  4      0.10%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4044                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2419619750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                7880576000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1456255000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8307.68                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4042                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4042                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.493073                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.471357                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.863386                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3047     75.38%     75.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                992     24.54%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4042                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2990654250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8451573000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1456245000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10268.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27057.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          33.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       33.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.68                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29018.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          33.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       33.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202343                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50484                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1550896.45                       # Average gap between requests
-system.physmem.pageHitRate                      70.64                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     275459224750                       # Time in different power states
-system.physmem.memoryStateTime::REF       18550220000                       # Time in different power states
+system.physmem.avgWrQLen                        24.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202814                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50461                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.64                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1563271.35                       # Average gap between requests
+system.physmem.pageHitRate                      70.76                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     275670988500                       # Time in different power states
+system.physmem.memoryStateTime::REF       18698420000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      261516412250                       # Time in different power states
+system.physmem.memoryStateTime::ACT      265594606500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 396060840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 398223000                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 216104625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 217284375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1136803200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1134198000                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                 393989400                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 396952920                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 214974375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 216591375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1136974800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1134400800                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0               216438480                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               215557200                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           36284230320                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           36284230320                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          106733795895                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          107171521695                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          239689369500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          239305399500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            384672802860                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            384726414090                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             692.448078                       # Core power per rank (mW)
-system.physmem.averagePower::1             692.544584                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              224874                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224874                       # Transaction distribution
-system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66644                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66644                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649719                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 649719                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22924864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22924864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            358201                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  358201    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              358201                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           954482500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2723745500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               125108663                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          80505376                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12157226                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103330871                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                82874854                       # Number of BTB hits
+system.physmem.writeEnergy::1               215550720                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           36574109520                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           36574109520                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          108415975050                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          108760602465                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          240876668250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          240574363500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            387829129875                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            387872571300                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             692.596540                       # Core power per rank (mW)
+system.physmem.averagePower::1             692.674119                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               125749069                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          81144276                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12157130                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            103970439                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83513487                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.203383                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18690215                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               9442                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.324261                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691097                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9450                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237537573                       # DTB read hits
-system.cpu.dtb.read_misses                     198412                       # DTB read misses
+system.cpu.dtb.read_hits                    237537681                       # DTB read hits
+system.cpu.dtb.read_misses                     198468                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237735985                       # DTB read accesses
-system.cpu.dtb.write_hits                    98305055                       # DTB write hits
-system.cpu.dtb.write_misses                      7206                       # DTB write misses
+system.cpu.dtb.read_accesses                237736149                       # DTB read accesses
+system.cpu.dtb.write_hits                    98305023                       # DTB write hits
+system.cpu.dtb.write_misses                      7212                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312261                       # DTB write accesses
-system.cpu.dtb.data_hits                    335842628                       # DTB hits
-system.cpu.dtb.data_misses                     205618                       # DTB misses
+system.cpu.dtb.write_accesses                98312235                       # DTB write accesses
+system.cpu.dtb.data_hits                    335842704                       # DTB hits
+system.cpu.dtb.data_misses                     205680                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336048246                       # DTB accesses
-system.cpu.itb.fetch_hits                   315070347                       # ITB hits
+system.cpu.dtb.data_accesses                336048384                       # DTB accesses
+system.cpu.itb.fetch_hits                   317138761                       # ITB hits
 system.cpu.itb.fetch_misses                       120                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               315070467                       # ITB accesses
+system.cpu.itb.fetch_accesses               317138881                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -333,71 +309,188 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1111065468                       # number of cpu cycles simulated
+system.cpu.numCycles                       1119933999                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      23870771                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      27043480                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.196252                       # CPI: cycles per instruction
-system.cpu.ipc                               0.835945                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1052548202                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        58517266                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             10608                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1686.446779                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           315057996                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12350                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25510.768907                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.205800                       # CPI: cycles per instruction
+system.cpu.ipc                               0.829325                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1060170405                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        59763594                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            776532                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.890193                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           323503178                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780628                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            414.414008                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         845912250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.890193                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999241                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999241                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          949                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1244                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1640                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         649485148                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        649485148                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    225339131                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       225339131                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     98164047                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164047                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     323503178                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        323503178                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    323503178                       # number of overall hits
+system.cpu.dcache.overall_hits::total       323503178                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       711929                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       137153                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137153                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       849082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       849082                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23415653250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  23415653250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9042894000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9042894000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  32458547250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32458547250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  32458547250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32458547250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    226051060                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    226051060                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    324352260                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    324352260                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    324352260                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    324352260                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.003149                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003149                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.001395                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001395                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.002618                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002618                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.002618                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002618                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38227.812214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38227.812214                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        91489                       # number of writebacks
+system.cpu.dcache.writebacks::total             91489                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          312                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          312                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        68454                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68454                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        68454                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68454                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       711617                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       711617                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69011                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69011                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       780628                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780628                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       780628                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780628                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21914188000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21914188000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4452805750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4452805750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26366993750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26366993750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26366993750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26366993750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003148                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003148                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002407                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002407                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002407                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002407                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements             10606                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1687.447542                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           317126411                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12349                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25680.331282                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1686.446779                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.823460                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.823460                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1687.447542                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.823949                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.823949                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1743                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         630153044                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        630153044                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    315057996                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       315057996                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     315057996                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        315057996                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    315057996                       # number of overall hits
-system.cpu.icache.overall_hits::total       315057996                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12351                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12351                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12351                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12351                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12351                       # number of overall misses
-system.cpu.icache.overall_misses::total         12351                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    334498250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    334498250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    334498250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    334498250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    334498250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    334498250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    315070347                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    315070347                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    315070347                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    315070347                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    315070347                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    315070347                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1574                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.851074                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         634289871                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        634289871                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    317126411                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       317126411                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     317126411                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        317126411                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    317126411                       # number of overall hits
+system.cpu.icache.overall_hits::total       317126411                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12350                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12350                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12350                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12350                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12350                       # number of overall misses
+system.cpu.icache.overall_misses::total         12350                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    333735500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    333735500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    333735500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    333735500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    333735500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    333735500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    317138761                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    317138761                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    317138761                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    317138761                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    317138761                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    317138761                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27082.685613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27082.685613                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27023.117409                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27023.117409                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -406,132 +499,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12351                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12351                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12351                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12351                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    308545750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    308545750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    308545750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    308545750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    308545750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    308545750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12350                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12350                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12350                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12350                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12350                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12350                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    307779500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    307779500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    307779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    307779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    307779500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    307779500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         723971                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        723970                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91489                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        69010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        69010                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24701                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652749                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1677450                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55815616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56606016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       884470                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             884470    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         884470                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      533724000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      19151250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1221989250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           258739                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32601.629306                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             523854                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291475                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.797252                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258740                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32601.453126                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             523849                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291476                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.797229                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2865.774027                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.087456                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907466                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994923                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2865.906217                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.087461                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907457                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994917                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          275                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2681                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29449                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2658                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29474                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          7436245                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7436245                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       499096                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         499096                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses          7436223                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         7436223                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       499092                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         499092                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks        91489                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total        91489                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.inst         2366                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       501462                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          501462                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       501462                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         501462                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst       501458                       # number of demand (read+write) hits
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 system.cpu.l2cache.ReadReq_misses::cpu.inst       224875                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total       224875                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst        66644                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66644                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       291519                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        291519                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       291519                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       291519                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  15924584250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  15924584250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4349858250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4349858250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  20274442500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  20274442500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  20274442500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20274442500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       723971                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       723971                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.inst        66645                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66645                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       291520                       # number of demand (read+write) misses
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+system.cpu.l2cache.overall_misses::total       291520                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16507068000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  16507068000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4360106750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4360106750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  20867174750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20867174750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  20867174750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20867174750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       723967                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       723967                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks        91489                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total        91489                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69010                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        69010                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       792981                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       792981                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       792981                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       792981                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.310613                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.310613                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.965715                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.965715                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.367624                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.367624                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.367624                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.367624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       792978                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792978                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       792978                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792978                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.310615                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.310615                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.965716                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.965716                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.367627                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.367627                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.367627                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.367627                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -544,153 +608,89 @@ system.cpu.l2cache.writebacks::writebacks        66683                       # n
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       224875                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total       224875                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66644                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66644                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       291519                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291519                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       291519                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291519                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13108086750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13108086750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3516385750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3516385750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  16624472500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  16624472500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  16624472500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  16624472500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.310613                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.310613                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.965715                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965715                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.367624                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.367624                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.367624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.367624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66645                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       291520                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291520                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       291520                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291520                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13668599500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13668599500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3526847250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3526847250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  17195446750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  17195446750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  17195446750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  17195446750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.310615                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.310615                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.965716                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.367627                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.367627                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.367627                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.367627                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            776534                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.879782                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322859767                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            780630                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.588726                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         839965250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.879782                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999238                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999238                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          950                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1254                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1629                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648198336                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648198336                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    224695720                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224695720                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     98164047                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164047                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     322859767                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322859767                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    322859767                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322859767                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       711933                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        711933                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       137153                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137153                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       849086                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849086                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       849086                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849086                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  22831828750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  22831828750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9022635000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9022635000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  31854463750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  31854463750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  31854463750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  31854463750                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    225407653                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225407653                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    323708853                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323708853                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    323708853                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323708853                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.003158                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.001395                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001395                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37516.180634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37516.180634                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91489                       # number of writebacks
-system.cpu.dcache.writebacks::total             91489                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          313                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          313                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst        68456                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68456                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst        68456                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68456                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       711620                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       711620                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69010                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        69010                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       780630                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       780630                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       780630                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       780630                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21330988000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21330988000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4442556750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4442556750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  25773544750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25773544750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  25773544750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  25773544750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002412                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002412                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002412                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002412                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq         723967                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723966                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24699                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1652745                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1677444                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55815488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56605824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       884467                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             884467    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         884467                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      533722500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      19152500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1222199250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq              224874                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224874                       # Transaction distribution
+system.membus.trans_dist::Writeback             66683                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       649721                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 649721                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22924928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22924928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            358202                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  358202    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              358202                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           975509000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2745284750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 12718eef7..531c5ebad 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.537826                       # Number of seconds simulated
-sim_ticks                                537826498500                       # Number of ticks simulated
-final_tick                               537826498500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.541781                       # Number of seconds simulated
+sim_ticks                                541781076000                       # Number of ticks simulated
+final_tick                               541781076000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 182992                       # Simulator instruction rate (inst/s)
-host_op_rate                                   225287                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              153620567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318916                       # Number of bytes of host memory used
-host_seconds                                  3501.01                       # Real time elapsed on the host
+host_inst_rate                                 140173                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172571                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              118539448                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261676                       # Number of bytes of host memory used
+host_seconds                                  4570.47                       # Real time elapsed on the host
 sim_insts                                   640655084                       # Number of instructions simulated
 sim_ops                                     788730743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          18593984                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18593984                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       165056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          165056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst          18593856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18593856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       164672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          164672                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             290531                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                290531                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             290529                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290529                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             34572458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34572458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          306895                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             306895                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7865496                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7865496                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7865496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            34572458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42437954                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        290531                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst             34319870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34319870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          303946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7808084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7808084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7808084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            34319870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42127954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        290529                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      290531                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      290529                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18574784                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19200                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18593984                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18573248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20608                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228480                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18593856                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      300                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      322                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18291                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18140                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18223                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18183                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18268                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18288                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18139                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18224                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18182                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18264                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               18315                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18099                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17920                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               17939                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               17964                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18020                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18098                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17914                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               17936                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               17963                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18015                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              18110                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18148                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18270                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18079                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18262                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18146                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18075                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18267                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4101                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
@@ -70,22 +70,22 @@ system.physmem.perBankWrBursts::6                4171                       # Pe
 system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4091                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4090                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4094                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    537826410500                       # Total gap between requests
+system.physmem.totGap                    541780987500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  290531                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  290529                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -93,8 +93,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    289832                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    289809                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       381                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -141,7 +141,7 @@ system.physmem.wrQLenPdf::12                        1                       # Wh
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::15                      980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      980                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4008                       # What write queue length does an incoming req see
@@ -149,9 +149,9 @@ system.physmem.wrQLenPdf::20                     4008                       # Wh
 system.physmem.wrQLenPdf::21                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     4008                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     4007                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                     4007                       # What write queue length does an incoming req see
@@ -189,117 +189,91 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       111650                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      204.222194                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     132.352958                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     255.940958                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          47308     42.37%     42.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43452     38.92%     81.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8609      7.71%     89.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          837      0.75%     89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1286      1.15%     90.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1285      1.15%     92.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          530      0.47%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          473      0.42%     92.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7870      7.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         111650                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       111520                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      204.445337                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     132.546078                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.289579                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46919     42.07%     42.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43694     39.18%     81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8696      7.80%     89.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          722      0.65%     89.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1258      1.13%     90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1255      1.13%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          576      0.52%     92.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          502      0.45%     92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7898      7.08%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         111520                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.550786                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.062915                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      507.683026                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.543798                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.072613                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      507.664819                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.489643                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.468091                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.860070                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3025     75.49%     75.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  3      0.07%     75.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                978     24.41%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.488645                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.467122                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.859477                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3028     75.57%     75.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                979     24.43%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3341982750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8783814000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1451155000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11514.91                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2702187250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8143568500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1451035000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9311.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30264.91                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          34.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       34.57                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.87                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28061.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          34.28                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       34.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.81                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194589                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50052                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   67.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.72                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1508083.78                       # Average gap between requests
-system.physmem.pageHitRate                      68.66                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     253474796750                       # Time in different power states
-system.physmem.memoryStateTime::REF       17958980000                       # Time in different power states
+system.physmem.avgWrQLen                        26.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     194639                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50105                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   67.07                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1519181.07                       # Average gap between requests
+system.physmem.pageHitRate                      68.69                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     263887343000                       # Time in different power states
+system.physmem.memoryStateTime::REF       18091060000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      266386143250                       # Time in different power states
+system.physmem.memoryStateTime::ACT      259796939500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 422248680                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 421734600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 230393625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 230113125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1134268200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1129057800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               215634960                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               212524560                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           35127764880                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           35127764880                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          108230961600                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          107988304905                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          227752503750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          227965360500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            373113775695                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            373074860370                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             693.752260                       # Core power per rank (mW)
-system.physmem.averagePower::1             693.679903                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              224439                       # Transaction distribution
-system.membus.trans_dist::ReadResp             224439                       # Transaction distribution
-system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66092                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66092                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 647160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22824256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            356629                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  356629    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              356629                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           974401000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2738560500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               154837020                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         104970668                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12892448                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            106220966                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                82647169                       # Number of BTB hits
+system.physmem.actEnergy::0                 421530480                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 421462440                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 230001750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 229964625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1134174600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1128987600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               215628480                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               212505120                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           35386113360                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           35386113360                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          105979651695                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          105556941405                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          232100586000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          232471384500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            375467686365                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            375407359050                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             693.032096                       # Core power per rank (mW)
+system.physmem.averagePower::1             692.920745                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               156937341                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         106680042                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12891228                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             97536058                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                81874318                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             77.806832                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19441660                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1323                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.942615                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19487919                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1320                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -385,69 +359,194 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1075652997                       # number of cpu cycles simulated
+system.cpu.numCycles                       1083562152                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655084                       # Number of instructions committed
 system.cpu.committedOps                     788730743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      25219021                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      22655429                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.678989                       # CPI: cycles per instruction
-system.cpu.ipc                               0.595596                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1020176456                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        55476541                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             23597                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1711.183580                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           289999264                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25347                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11441.167160                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.691335                       # CPI: cycles per instruction
+system.cpu.ipc                               0.591249                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1029140125                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        54422027                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778221                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.644165                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378457747                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782317                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.765209                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         752182250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.644165                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999181                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999181                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          962                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1341                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1589                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         759400731                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759400731                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    249632505                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249632505                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    128813764                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128813764                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst         5739                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     378446269                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378446269                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    378446269                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378446269                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       713747                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713747                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       137713                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137713                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       851460                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851460                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       851460                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851460                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23050728217                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  23050728217                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9196889000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9196889000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  32247617217                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32247617217                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  32247617217                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32247617217                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    250346252                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250346252                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    379297729                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379297729                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    379297729                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379297729                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002851                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.001068                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.002245                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.002245                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37873.320199                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37873.320199                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
+system.cpu.dcache.writebacks::total             91420                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          752                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          752                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68391                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68391                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        69143                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69143                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        69143                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69143                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       712995                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712995                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69322                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       782317                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782317                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       782317                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782317                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21540338778                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21540338778                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4529678750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4529678750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26070017528                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26070017528                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26070017528                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26070017528                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002848                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements             23590                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1712.180354                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           289921724                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             25341                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11440.816227                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1711.183580                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835539                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835539                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1750                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1598                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.854492                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         580074571                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        580074571                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    289999264                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       289999264                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     289999264                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        289999264                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    289999264                       # number of overall hits
-system.cpu.icache.overall_hits::total       289999264                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25348                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25348                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        25348                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          25348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25348                       # number of overall misses
-system.cpu.icache.overall_misses::total         25348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    480691746                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    480691746                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    480691746                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    480691746                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    480691746                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    480691746                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    290024612                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    290024612                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    290024612                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    290024612                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    290024612                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    290024612                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst  1712.180354                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836026                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836026                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1602                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         579919473                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        579919473                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    289921724                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst        25342                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst        25342                       # number of overall misses
+system.cpu.icache.overall_misses::total         25342                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    481750746                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    481750746                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total    481750746                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    481750746                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    481750746                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    289947066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    289947066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    289947066                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    289947066                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    289947066                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    289947066                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18963.695203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18963.695203                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19009.973404                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19009.973404                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -456,136 +555,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25348                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25348                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        25348                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        25348                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        25348                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        25348                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    428895254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    428895254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    428895254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    428895254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    428895254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    428895254                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25342                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        25342                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        25342                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        25342                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        25342                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        25342                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429966254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    429966254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429966254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    429966254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429966254                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    429966254                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         738445                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        738444                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        69323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        69323                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50695                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1656260                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1706955                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55925760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57547968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       899188                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5             899188    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         899188                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      541014000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38571746                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1224928725                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           257750                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32583.011088                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             539180                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           290494                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.856080                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257749                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32583.074549                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             539070                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290493                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.855707                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2866.114553                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.087467                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.906888                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2860.585859                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.087298                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2831                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29389                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2800                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29426                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          7553321                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         7553321                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       513976                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         513976                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses          7552447                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         7552447                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       513866                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         513866                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks        91420                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total        91420                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.inst         3231                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       517207                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          517207                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       517207                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         517207                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst       224469                       # number of ReadReq misses
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-system.cpu.l2cache.ReadExReq_misses::cpu.inst        66092                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66092                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       290561                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        290561                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       290561                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       290561                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16739408750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  16739408750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4422117750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4422117750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  21161526500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  21161526500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  21161526500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  21161526500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       738445                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       738445                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.demand_misses::cpu.inst       290562                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        290562                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       290562                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       290562                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16093224000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  16093224000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4428044750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4428044750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  20521268750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20521268750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  20521268750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20521268750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       738337                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       738337                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks        91420                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total        91420                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        69323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       807768                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       807768                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       807768                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       807768                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.303975                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.303975                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.953392                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.953392                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.359708                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.359708                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.359708                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.359708                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        69322                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       807659                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       807659                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       807659                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       807659                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.304022                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.304022                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.953391                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.359758                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.359758                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.359758                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.359758                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -596,169 +662,101 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           29                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           29                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           29                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           29                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       224440                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       224440                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       290532                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       290532                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       290532                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       290532                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13904175250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13904175250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3593710250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3593710250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  17497885500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  17497885500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  17497885500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  17497885500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.303936                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.303936                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.953392                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953392                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.359673                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.359673                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.359673                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.359673                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           32                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           32                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           32                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           32                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           32                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       224439                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       224439                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66091                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       290530                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290530                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       290530                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290530                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13281416250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13281416250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3575940250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3575940250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  16857356500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  16857356500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  16857356500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  16857356500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.303979                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.303979                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.953391                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.359719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.359719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.359719                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.359719                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            778324                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.650508                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378453595                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782420                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.696218                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         745524250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.650508                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999182                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999182                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          963                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1354                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1577                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759392478                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759392478                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    249628224                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249628224                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    128813893                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128813893                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst         5739                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     378442117                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378442117                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    378442117                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378442117                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       713850                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713850                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       137584                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137584                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       851434                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851434                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       851434                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851434                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23700601220                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  23700601220                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9183787250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9183787250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  32884388470                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  32884388470                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  32884388470                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  32884388470                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    250342074                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250342074                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    379293551                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379293551                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    379293551                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379293551                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002851                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.001067                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001067                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.002245                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38622.357658                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38622.357658                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
-system.cpu.dcache.writebacks::total             91420                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          753                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          753                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        68261                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68261                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst        69014                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69014                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst        69014                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69014                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       713097                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       713097                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        69323                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        69323                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       782420                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782420                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       782420                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782420                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  22188801525                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  22188801525                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4523752250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4523752250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26712553775                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26712553775                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26712553775                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26712553775                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002848                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq         738337                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        738336                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50683                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1656054                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1706737                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1621824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55919168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57540992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       899079                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5             899079    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         899079                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      540959500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      38562746                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    1224341972                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq              224438                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224438                       # Transaction distribution
+system.membus.trans_dist::Writeback             66098                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 647156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22824128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            356627                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  356627    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              356627                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           983533000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2738969000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 2a99c07ac..a69375a69 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058385                       # Number of seconds simulated
-sim_ticks                                 58384546000                       # Number of ticks simulated
-final_tick                                58384546000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058648                       # Number of seconds simulated
+sim_ticks                                 58648243500                       # Number of ticks simulated
+final_tick                                58648243500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 341117                       # Simulator instruction rate (inst/s)
-host_op_rate                                   341117                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              225196692                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245432                       # Number of bytes of host memory used
-host_seconds                                   259.26                       # Real time elapsed on the host
+host_inst_rate                                 296946                       # Simulator instruction rate (inst/s)
+host_op_rate                                   296946                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              196921777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246040                       # Number of bytes of host memory used
+host_seconds                                   297.83                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          10663104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10663104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       515328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          515328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7299072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7299072                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             166611                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166611                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114048                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114048                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            182635727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               182635727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8826445                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8826445                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         125017192                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              125017192                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         125017192                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           182635727                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              307652919                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166611                       # Number of read requests accepted
-system.physmem.writeReqs                       114048                       # Number of write requests accepted
-system.physmem.readBursts                      166611                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114048                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10662592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       512                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7297152                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10663104                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7299072                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst          10664704                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10664704                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       516672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          516672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7299136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7299136                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             166636                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166636                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114049                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114049                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            181841831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               181841831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8809676                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8809676                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         124456174                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              124456174                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         124456174                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           181841831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              306298005                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166636                       # Number of read requests accepted
+system.physmem.writeReqs                       114049                       # Number of write requests accepted
+system.physmem.readBursts                      166636                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114049                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10664320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7297536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10664704                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7299136                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10468                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10467                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               10513                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10311                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10090                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10431                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10426                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9846                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10593                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10643                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10595                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10255                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10315                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10094                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10429                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10431                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9849                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10303                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10595                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10644                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10600                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10258                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10651                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10528                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10649                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10653                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10529                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10648                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7087                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7261                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6999                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7178                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7079                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7222                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6940                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7097                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7220                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7094                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6967                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6965                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7289                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7282                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58384519500                       # Total gap between requests
+system.physmem.totGap                     58648216500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166611                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166636                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114048                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1618                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114049                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    165019                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1583                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7026                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7039                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -189,140 +189,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54365                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      330.333707                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.729973                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.976327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19356     35.60%     35.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11696     21.51%     57.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5632     10.36%     67.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3623      6.66%     74.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2688      4.94%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2044      3.76%     82.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1686      3.10%     85.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1497      2.75%     88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6143     11.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54365                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7019                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.733295                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      348.126500                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7017     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        54349                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.476881                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.680943                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.305827                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19373     35.65%     35.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11674     21.48%     57.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5602     10.31%     67.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3597      6.62%     74.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2712      4.99%     79.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2058      3.79%     82.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1657      3.05%     85.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1528      2.81%     88.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6148     11.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54349                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7016                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.748575                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      348.190330                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7015     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7019                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7019                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.244194                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.228515                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.751123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6265     89.26%     89.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 18      0.26%     89.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                572      8.15%     97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                131      1.87%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 24      0.34%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.06%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7019                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2006026500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5129832750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    833015000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12040.76                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7016                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7016                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.251995                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.236052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.756108                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6236     88.88%     88.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.21%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                602      8.58%     97.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                126      1.80%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 27      0.38%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  6      0.09%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7016                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2009240500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5133553000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    833150000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12058.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30790.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         182.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         124.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      182.64                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      125.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30808.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         181.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         124.43                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      181.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      124.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.40                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.98                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           2.39                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.42                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.97                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.87                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144815                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81433                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144828                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81470                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   86.92                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.40                       # Row buffer hit rate for writes
-system.physmem.avgGap                       208026.54                       # Average gap between requests
-system.physmem.pageHitRate                      80.62                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      31935315750                       # Time in different power states
-system.physmem.memoryStateTime::REF        1949480000                       # Time in different power states
+system.physmem.writeRowHitRate                  71.43                       # Row buffer hit rate for writes
+system.physmem.avgGap                       208946.74                       # Average gap between requests
+system.physmem.pageHitRate                      80.63                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      32158270750                       # Time in different power states
+system.physmem.memoryStateTime::REF        1958320000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       24496780500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       24529718750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 198434880                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 212398200                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 108273000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 115891875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                642478200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                656705400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               367733520                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               370876320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            3813182880                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            3813182880                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           12240327915                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           12673025460                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           24291807750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           23912248500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             41662238145                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             41754328635                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             713.619786                       # Core power per rank (mW)
-system.physmem.averagePower::1             715.197176                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq               35730                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35730                       # Transaction distribution
-system.membus.trans_dist::Writeback            114048                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130881                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130881                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447270                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 447270                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17962176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17962176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            280659                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  280659    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              280659                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1302108500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1600532000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14593516                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9448617                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            379109                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10302575                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6369350                       # Number of BTB hits
+system.physmem.actEnergy::0                 198298800                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 212481360                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 108198750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 115937250                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                642673200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                656838000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               367811280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               370960560                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0            3830473920                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1            3830473920                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           12291718545                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           12736700730                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0           24405568500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1           24015233250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0             41844742995                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1             41938625070                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             713.510412                       # Core power per rank (mW)
+system.physmem.averagePower::1             715.111230                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                14678284                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9497966                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            389718                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9980180                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6390464                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.822894                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1700742                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              73233                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             64.031551                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1709614                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              85893                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20554145                       # DTB read hits
-system.cpu.dtb.read_misses                      96857                       # DTB read misses
-system.cpu.dtb.read_acv                             9                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20651002                       # DTB read accesses
-system.cpu.dtb.write_hits                    14666071                       # DTB write hits
-system.cpu.dtb.write_misses                      9396                       # DTB write misses
+system.cpu.dtb.read_hits                     20567325                       # DTB read hits
+system.cpu.dtb.read_misses                      96876                       # DTB read misses
+system.cpu.dtb.read_acv                            11                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20664201                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665780                       # DTB write hits
+system.cpu.dtb.write_misses                      9406                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14675467                       # DTB write accesses
-system.cpu.dtb.data_hits                     35220216                       # DTB hits
-system.cpu.dtb.data_misses                     106253                       # DTB misses
-system.cpu.dtb.data_acv                             9                       # DTB access violations
-system.cpu.dtb.data_accesses                 35326469                       # DTB accesses
-system.cpu.itb.fetch_hits                    25540027                       # ITB hits
-system.cpu.itb.fetch_misses                      5176                       # ITB misses
+system.cpu.dtb.write_accesses                14675186                       # DTB write accesses
+system.cpu.dtb.data_hits                     35233105                       # DTB hits
+system.cpu.dtb.data_misses                     106282                       # DTB misses
+system.cpu.dtb.data_acv                            11                       # DTB access violations
+system.cpu.dtb.data_accesses                 35339387                       # DTB accesses
+system.cpu.itb.fetch_hits                    25627874                       # ITB hits
+system.cpu.itb.fetch_misses                      5262                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25545203                       # ITB accesses
+system.cpu.itb.fetch_accesses                25633136                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -336,70 +311,185 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        116769092                       # number of cpu cycles simulated
+system.cpu.numCycles                        117296487                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1185538                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1098513                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.320349                       # CPI: cycles per instruction
-system.cpu.ipc                               0.757376                       # IPC: instructions per cycle
-system.cpu.tickCycles                        90792552                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        25976540                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements            153164                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1933.730829                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25384814                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            155212                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            163.549300                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       41528149250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1933.730829                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.944205                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.944205                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.326312                       # CPI: cycles per instruction
+system.cpu.ipc                               0.753970                       # IPC: instructions per cycle
+system.cpu.tickCycles                        91572461                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        25724026                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            200783                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.549742                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34616444                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204879                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.960430                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         644809250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.549742                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.994031                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.994031                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          740                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3305                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          70176773                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70176773                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20283132                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20283132                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     14333312                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333312                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst      34616444                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34616444                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     34616444                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34616444                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst        89438                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89438                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       280065                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280065                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       369503                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369503                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       369503                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369503                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4420798500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4420798500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20106086500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20106086500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  24526885000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24526885000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  24526885000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24526885000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20372570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20372570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     34985947                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34985947                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     34985947                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34985947                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019165                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019165                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.010561                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010561                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.010561                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010561                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49428.637716                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49428.637716                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71790.786068                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71790.786068                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66378.040232                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66378.040232                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66378.040232                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66378.040232                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       168546                       # number of writebacks
+system.cpu.dcache.writebacks::total            168546                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28119                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28119                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136505                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136505                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       164624                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164624                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       164624                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164624                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61319                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61319                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143560                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143560                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       204879                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204879                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       204879                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204879                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2428683000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2428683000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9985116500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9985116500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12413799500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12413799500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12413799500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12413799500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005856                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005856                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39607.348456                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39607.348456                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69553.611730                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69553.611730                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60590.882911                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60590.882911                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60590.882911                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60590.882911                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements            153802                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1934.163244                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25472023                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            155850                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            163.439352                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       41695201250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1934.163244                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.944416                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.944416                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1044                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1050                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          791                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51235266                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51235266                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25384814                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25384814                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25384814                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25384814                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25384814                       # number of overall hits
-system.cpu.icache.overall_hits::total        25384814                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       155213                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        155213                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       155213                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         155213                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       155213                       # number of overall misses
-system.cpu.icache.overall_misses::total        155213                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2516319497                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2516319497                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2516319497                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2516319497                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2516319497                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2516319497                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25540027                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25540027                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25540027                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25540027                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25540027                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25540027                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006077                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006077                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006077                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006077                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006077                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006077                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16212.040854                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16212.040854                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16212.040854                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16212.040854                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16212.040854                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16212.040854                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51411598                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51411598                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25472023                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25472023                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total         25472023                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25472023                       # number of overall hits
+system.cpu.icache.overall_hits::total        25472023                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       155851                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        155851                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       155851                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         155851                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       155851                       # number of overall misses
+system.cpu.icache.overall_misses::total        155851                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2529071491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2529071491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2529071491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2529071491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2529071491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2529071491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25627874                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25627874                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25627874                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25627874                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25627874                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25627874                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006081                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006081                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006081                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006081                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006081                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006081                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16227.496076                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16227.496076                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16227.496076                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16227.496076                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16227.496076                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16227.496076                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -408,289 +498,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155213                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       155213                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       155213                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       155213                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       155213                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       155213                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2202806503                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2202806503                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2202806503                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2202806503                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2202806503                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2202806503                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006077                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006077                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006077                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006077                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14192.152094                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14192.152094                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14192.152094                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14192.152094                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14192.152094                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14192.152094                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155851                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       155851                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       155851                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       155851                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       155851                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       155851                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2214263509                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2214263509                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2214263509                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2214263509                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2214263509                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2214263509                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006081                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006081                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006081                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006081                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14207.566900                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14207.566900                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14207.566900                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14207.566900                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14207.566900                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14207.566900                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         216522                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        216521                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168531                       # Transaction distribution
+system.cpu.l2cache.tags.replacements           132709                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30478.426101                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             220667                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164786                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.339113                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 26240.805315                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4237.620786                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.800806                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.129322                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.930128                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32077                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1016                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11992                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18835                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978912                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          4542555                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4542555                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       181414                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         181414                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168546                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168546                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst        12679                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12679                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       194093                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          194093                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       194093                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         194093                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        35755                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        35755                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       130882                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130882                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       166637                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166637                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       166637                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166637                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2611093000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2611093000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9714729250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9714729250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  12325822250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12325822250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  12325822250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12325822250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       217169                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       217169                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168546                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168546                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143561                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143561                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       360730                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       360730                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       360730                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       360730                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.164641                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.164641                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911682                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911682                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461944                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.461944                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461944                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.461944                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73027.352818                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73027.352818                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74225.097798                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74225.097798                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73968.099822                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73968.099822                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73968.099822                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73968.099822                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks       114049                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114049                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35755                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        35755                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130882                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130882                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       166637                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166637                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       166637                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166637                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2156394000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2156394000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   8029638750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8029638750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10186032750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10186032750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10186032750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10186032750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.164641                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.164641                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911682                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911682                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461944                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.461944                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461944                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.461944                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60310.278283                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60310.278283                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61350.214315                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61350.214315                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61127.077120                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61127.077120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61127.077120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61127.077120                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq         217169                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        217168                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143561                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143561                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       310425                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578271                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            888696                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9933568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23897664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           33831232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       311701                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578304                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            890005                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9974400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23899200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           33873600                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       528614                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       529276                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             528614    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             529276    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         528614                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      432838000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         529276                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      433184000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     234362497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     235328991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     343210750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     343237000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements           132688                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30473.454944                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             220028                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164763                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.335421                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26247.246790                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4226.208154                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.801002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.128974                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.929976                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32075                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1029                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11968                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18838                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          112                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978851                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4537236                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4537236                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       180791                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         180791                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168531                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168531                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        12680                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12680                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       193471                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          193471                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       193471                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         193471                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        35731                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35731                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       130881                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130881                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       166612                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166612                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       166612                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166612                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2608794250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2608794250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9709899750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9709899750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  12318694000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12318694000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  12318694000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12318694000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       216522                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       216522                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168531                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168531                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143561                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143561                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       360083                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       360083                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       360083                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       360083                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.165022                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.165022                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911675                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911675                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.462704                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.462704                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.462704                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.462704                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73012.069352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73012.069352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74188.764985                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74188.764985                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73936.415144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73936.415144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73936.415144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73936.415144                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114048                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114048                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35731                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35731                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       166612                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166612                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       166612                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166612                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2155637750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2155637750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   8025242250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8025242250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10180880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10180880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10180880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10180880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.165022                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165022                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911675                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911675                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.462704                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.462704                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.462704                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.462704                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.622737                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.622737                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61317.091480                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61317.091480                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61105.322546                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61105.322546                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61105.322546                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61105.322546                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            200774                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4071.445438                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34597334                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204870                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.874574                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         644670250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.445438                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.994005                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994005                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          755                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3288                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70138572                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70138572                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     20264067                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20264067                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     14333267                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333267                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst      34597334                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34597334                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     34597334                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34597334                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst        89407                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89407                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       280110                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280110                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       369517                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369517                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       369517                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369517                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4423552750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4423552750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20095524250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20095524250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  24519077000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24519077000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  24519077000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24519077000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20353474                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20353474                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     34966851                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34966851                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     34966851                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34966851                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004393                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004393                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.010568                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010568                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.010568                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010568                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49476.581811                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49476.581811                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71741.545286                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71741.545286                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66354.395062                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66354.395062                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66354.395062                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66354.395062                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168531                       # number of writebacks
-system.cpu.dcache.writebacks::total            168531                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28097                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28097                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136550                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       164647                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164647                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       164647                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164647                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61310                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61310                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143560                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143560                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       204870                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204870                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       204870                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204870                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2430963250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2430963250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9980296000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9980296000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12411259250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12411259250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12411259250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12411259250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003012                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003012                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005859                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005859                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005859                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005859                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq               35754                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35754                       # Transaction distribution
+system.membus.trans_dist::Writeback            114049                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130882                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130882                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447321                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 447321                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17963840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17963840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            280685                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  280685    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              280685                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1304586000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1602413250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 92998cd4b..c949b9a6e 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,91 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.056374                       # Number of seconds simulated
-sim_ticks                                 56374399500                       # Number of ticks simulated
-final_tick                                56374399500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.057847                       # Number of seconds simulated
+sim_ticks                                 57847312000                       # Number of ticks simulated
+final_tick                                57847312000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200830                       # Simulator instruction rate (inst/s)
-host_op_rate                                   256832                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              159651052                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319716                       # Number of bytes of host memory used
-host_seconds                                   353.11                       # Real time elapsed on the host
+host_inst_rate                                 186854                       # Simulator instruction rate (inst/s)
+host_op_rate                                   238959                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152421830                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261476                       # Number of bytes of host memory used
+host_seconds                                   379.52                       # Real time elapsed on the host
 sim_insts                                    70915127                       # Number of instructions simulated
 sim_ops                                      90690083                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           8247168                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8247168                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       323904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          323904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst           8247680                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8247680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       324352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          324352                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      5372864                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           5372864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             128862                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128862                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             128870                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128870                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           83951                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                83951                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            146292787                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               146292787                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5745587                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5745587                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          95306807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               95306807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          95306807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           146292787                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              241599593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128862                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst            142576720                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               142576720                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5607037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5607037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          92880098                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               92880098                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          92880098                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           142576720                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              235456818                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128870                       # Number of read requests accepted
 system.physmem.writeReqs                        83951                       # Number of write requests accepted
-system.physmem.readBursts                      128862                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      128870                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      83951                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8246784                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8247168                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                  8247360                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5370944                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8247680                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                5372864                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8164                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8373                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8238                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8169                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8316                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8449                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8158                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8375                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8229                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8171                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8319                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8450                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8089                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7969                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7970                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                8071                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7635                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7816                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7641                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7819                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7830                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7876                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8004                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5186                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7879                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5181                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5285                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5196                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5198                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5047                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5033                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5086                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5252                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5143                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5224                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     56374368000                       # Total gap between requests
+system.physmem.totGap                     57847280000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128862                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128870                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -93,8 +93,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  83951                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    126558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    126560                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2283                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5165                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -189,120 +189,97 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38259                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      355.901827                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.943020                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     337.187447                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12097     31.62%     31.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8058     21.06%     52.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4075     10.65%     63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2806      7.33%     70.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2532      6.62%     77.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1601      4.18%     81.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1324      3.46%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1160      3.03%     87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4606     12.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38259                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5153                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.995537                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      361.849882                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5150     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38379                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      354.780687                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.561409                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.824723                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12139     31.63%     31.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8088     21.07%     52.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4086     10.65%     63.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2872      7.48%     70.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2530      6.59%     77.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1664      4.34%     81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1273      3.32%     85.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1227      3.20%     88.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4500     11.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38379                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.981187                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      361.178240                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5153                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5153                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.286435                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.268739                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.792681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4505     87.42%     87.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  6      0.12%     87.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                503      9.76%     97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                112      2.17%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 16      0.31%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.08%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  5      0.10%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5153                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1533288750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3949338750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    644280000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11899.24                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5156                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.276377                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.259366                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.777117                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4528     87.82%     87.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  7      0.14%     87.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                480      9.31%     97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                121      2.35%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 14      0.27%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  2      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5156                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1539171500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3955390250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    644325000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11944.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30649.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         146.29                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          95.28                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      146.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       95.31                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30694.06                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         142.57                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          92.85                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      142.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       92.88                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.14                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.74                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.84                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.73                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112227                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     62289                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                       264900.96                       # Average gap between requests
-system.physmem.pageHitRate                      82.01                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      30998356250                       # Time in different power states
-system.physmem.memoryStateTime::REF        1882400000                       # Time in different power states
+system.physmem.avgWrQLen                        23.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112176                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62224                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                       271811.90                       # Average gap between requests
+system.physmem.pageHitRate                      81.95                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      32236826000                       # Time in different power states
+system.physmem.memoryStateTime::REF        1931540000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       23491967500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       23675959000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 150716160                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 138521880                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  82236000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  75582375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                512857800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                492039600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               272347920                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               271479600                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            3681974400                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            3681974400                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           11715197175                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           11107328085                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           23547137250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           24080355750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             39962466705                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             39847281690                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             708.897385                       # Core power per rank (mW)
-system.physmem.averagePower::1             706.854109                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq               26583                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26583                       # Transaction distribution
-system.membus.trans_dist::Writeback             83951                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102279                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102279                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341675                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 341675                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13620032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            212813                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  212813    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              212813                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           942245500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1221409750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14808790                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9910130                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            393084                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9534894                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6736290                       # Number of BTB hits
+system.physmem.actEnergy::0                 151237800                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 138899880                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                  82520625                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                  75788625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                512678400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                492078600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               272322000                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               271486080                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0            3778092240                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1            3778092240                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           11712850200                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           11277598770                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0           24432156750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1           24813956250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0             40941858015                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1             40847900445                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             707.794027                       # Core power per rank (mW)
+system.physmem.averagePower::1             706.169709                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                14825675                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9917897                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            395023                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9456669                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6745546                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.648819                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1716012                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             71.331100                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1719567                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -388,329 +365,89 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        112748799                       # number of cpu cycles simulated
+system.cpu.numCycles                        115694624                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915127                       # Number of instructions committed
 system.cpu.committedOps                      90690083                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1227279                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1146301                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.589912                       # CPI: cycles per instruction
-system.cpu.ipc                               0.628966                       # IPC: instructions per cycle
-system.cpu.tickCycles                        93715149                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        19033650                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             42434                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1857.503994                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24948244                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44476                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            560.937225                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1857.503994                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.906984                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.906984                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          846                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1075                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50029918                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50029918                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24948244                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24948244                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24948244                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24948244                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24948244                       # number of overall hits
-system.cpu.icache.overall_hits::total        24948244                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44477                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44477                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        44477                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          44477                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44477                       # number of overall misses
-system.cpu.icache.overall_misses::total         44477                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    894634739                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    894634739                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    894634739                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    894634739                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    894634739                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    894634739                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24992721                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24992721                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24992721                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24992721                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24992721                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24992721                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001780                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001780                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001780                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001780                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001780                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001780                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20114.547721                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20114.547721                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44477                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        44477                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        44477                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        44477                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        44477                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        44477                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    803759261                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    803759261                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    803759261                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    803759261                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    803759261                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    803759261                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001780                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001780                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001780                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001780                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          97959                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         97958                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128423                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107038                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107038                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        88953                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            538416                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2846464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18492352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           21338816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       333420                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5             333420    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         333420                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      295133000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      67675739                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     268453439                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            95725                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29925.727358                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              99436                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126843                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.783930                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3239.392599                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.814402                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.098858                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.913261                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31118                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1141                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9850                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19418                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          583                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2901241                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2901241                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        71304                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          71304                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       128423                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128423                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         4759                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4759                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        76063                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           76063                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        76063                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          76063                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        26655                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26655                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       102279                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102279                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       128934                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128934                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       128934                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128934                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1985312250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1985312250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7483113000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7483113000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   9468425250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   9468425250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   9468425250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   9468425250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        97959                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        97959                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       128423                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       128423                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107038                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107038                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       204997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       204997                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       204997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       204997                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.272104                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.272104                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955539                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955539                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.628956                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.628956                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.628956                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.628956                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83951                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83951                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           71                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26584                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total       128863                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1642872250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1642872250                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6184053500                       # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total   7826925750                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total   7826925750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.271379                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.271379                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.955539                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955539                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.628609                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.628609                       # mshr miss rate for demand accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            156424                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.200974                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42664255                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160520                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.787783                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         770315250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4068.200974                       # Average occupied blocks per requestor
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+system.cpu.cpi                               1.631452                       # CPI: cycles per instruction
+system.cpu.ipc                               0.612951                       # IPC: instructions per cycle
+system.cpu.tickCycles                        96938261                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18756363                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156422                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.596798                       # Cycle average of tags in use
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+system.cpu.dcache.tags.sampled_refs            160518                       # Sample count of references to valid blocks.
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+system.cpu.dcache.tags.warmup_cycle         784159000                       # Cycle when the warmup percentage was hit.
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 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
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 system.cpu.dcache.tags.age_task_id_blocks_1024::2         3296                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86013136                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86013136                       # Number of data accesses
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+system.cpu.dcache.tags.tag_accesses          86015580                       # Number of tag accesses
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 system.cpu.dcache.LoadLockedReq_hits::cpu.inst        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
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 system.cpu.dcache.WriteReq_accesses::cpu.inst     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002431                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002431                       # miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891                       # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 66402.699794                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66402.699794                       # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395                       # average ReadReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 66383.888710                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66383.888710                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -719,32 +456,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.dcache.writebacks::total            128423                       # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_hits::total         2533                       # number of ReadReq MSHR hits
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+system.cpu.dcache.demand_mshr_misses::cpu.inst       160518                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       160518                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       160518                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160518                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   1995361313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1995361313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7633992250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7633992250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9629353563                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9629353563                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9629353563                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9629353563                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002321                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002321                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.005392                       # mshr miss rate for WriteReq accesses
@@ -753,14 +490,278 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003742
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003742                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
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+system.cpu.icache.tags.total_refs            25082437                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             44745                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            560.564018                       # Average number of references to valid blocks.
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+system.cpu.icache.tags.tag_accesses          50299111                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         50299111                       # Number of data accesses
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+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
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+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq          98230                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         98229                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       128433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        89491                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       449469                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            538960                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2863680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18492864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           21356544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       333697                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5             333697    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         333697                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      295281500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      68080238                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     268447937                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq               26589                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26589                       # Transaction distribution
+system.membus.trans_dist::Writeback             83951                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102281                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102281                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       341691                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 341691                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13620544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13620544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            212821                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  212821    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              212821                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           929388500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1213397000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 3052ca460..38d19f012 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.182263                       # Number of seconds simulated
-sim_ticks                                1182263011500                       # Number of ticks simulated
-final_tick                               1182263011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.200149                       # Number of seconds simulated
+sim_ticks                                1200148658000                       # Number of ticks simulated
+final_tick                               1200148658000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 317111                       # Simulator instruction rate (inst/s)
-host_op_rate                                   317111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              205274325                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237352                       # Number of bytes of host memory used
-host_seconds                                  5759.43                       # Real time elapsed on the host
+host_inst_rate                                 401299                       # Simulator instruction rate (inst/s)
+host_op_rate                                   401299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              263701147                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236908                       # Number of bytes of host memory used
+host_seconds                                  4551.17                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         125507520                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125507520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65168128                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65168128                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst            1961055                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961055                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018252                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018252                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            106158713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               106158713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           51752                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              51752                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          55121515                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               55121515                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          55121515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           106158713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              161280228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961055                       # Number of read requests accepted
-system.physmem.writeReqs                      1018252                       # Number of write requests accepted
-system.physmem.readBursts                     1961055                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1018252                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125426368                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65166528                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125507520                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65168128                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1268                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst         125506304                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125506304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65167488                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65167488                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst            1961036                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961036                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1018242                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1018242                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            104575632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               104575632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           51087                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              51087                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54299513                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54299513                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54299513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           104575632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              158875145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961036                       # Number of read requests accepted
+system.physmem.writeReqs                      1018242                       # Number of write requests accepted
+system.physmem.readBursts                     1961036                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1018242                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125423936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     82368                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65165888                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125506304                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65167488                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1287                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118756                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114094                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116231                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117777                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117824                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117524                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119883                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118759                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114099                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116224                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117761                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117826                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117519                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119878                       # Per bank write bursts
 system.physmem.perBankRdBursts::7              124524                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126980                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130091                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128645                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130349                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126066                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125260                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122596                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123187                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61220                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126972                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130092                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128660                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130342                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126055                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125250                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122599                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123189                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61222                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               61486                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60567                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61241                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61658                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63102                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64150                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65615                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65332                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60565                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61239                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61662                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63103                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64148                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65614                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65330                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               65779                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65299                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65643                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64166                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64211                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64571                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64187                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65300                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65644                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64162                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64212                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64570                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64181                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1182262901500                       # Total gap between requests
+system.physmem.totGap                    1200148547500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961055                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961036                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1018252                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1833329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    126440                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1018242                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1833978                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    125753                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    29905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    29968                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60000                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                    60083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    60024                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    60785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    59975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    60789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -189,149 +189,128 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1836557                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.775367                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.104101                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.072591                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1457072     79.34%     79.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       262826     14.31%     93.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49283      2.68%     96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20722      1.13%     97.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12908      0.70%     98.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7083      0.39%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5369      0.29%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4081      0.22%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        17213      0.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1836557                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59478                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.947897                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      162.231607                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59437     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           16      0.03%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            8      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1837714                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.708116                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.073776                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     129.879385                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1458610     79.37%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       262385     14.28%     93.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49383      2.69%     96.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20628      1.12%     97.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12966      0.71%     98.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7221      0.39%     98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5354      0.29%     98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4357      0.24%     99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16810      0.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1837714                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59460                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.957232                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      160.327917                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59419     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           13      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59478                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59478                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.119389                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.083537                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.112675                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              28008     47.09%     47.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1262      2.12%     49.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              25918     43.58%     92.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3789      6.37%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                422      0.71%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 60      0.10%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59460                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59460                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.124403                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.088362                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.116973                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27861     46.86%     46.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1344      2.26%     49.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              25901     43.56%     92.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3838      6.45%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                438      0.74%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 56      0.09%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                 14      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59478                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36992521000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73738527250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9798935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18875.79                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::36                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59460                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    37078229500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73823523250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9798745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18919.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37625.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         106.09                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          55.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      106.16                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       55.12                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37669.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         104.51                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          54.30                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      104.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       54.30                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.26                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.43                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.24                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.82                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     727653                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    413795                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.13                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                       396824.80                       # Average gap between requests
-system.physmem.pageHitRate                      38.33                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     385836572500                       # Time in different power states
-system.physmem.memoryStateTime::REF       39478140000                       # Time in different power states
+system.physmem.readRowHits                     726316                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    413927                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.06                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.65                       # Row buffer hit rate for writes
+system.physmem.avgGap                       402832.01                       # Average gap between requests
+system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     393584177750                       # Time in different power states
+system.physmem.memoryStateTime::REF       40075360000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      756941975000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      766482185250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                6738530400                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                7145810280                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                3676777500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                3899003625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               7383534600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               7902102000                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                6742219680                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                7150867920                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                3678790500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                3901763250                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               7383355200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               7901907000                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0              3233772720                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              3364338240                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           77219241840                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           77219241840                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          405130664925                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          418464065025                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          353976228000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          342280263000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            857358749985                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            860274824010                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             725.188336                       # Core power per rank (mW)
-system.physmem.averagePower::1             727.654868                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq             1181608                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1181608                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018252                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            779447                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           779447                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940362                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4940362                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190675648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190675648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2979307                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2979307    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2979307                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         11933178500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18493465250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               244422779                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         184893031                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15656805                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            166159806                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               163963467                       # Number of BTB hits
+system.physmem.writeEnergy::1              3364273440                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           78387404160                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           78387404160                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          410122352430                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          423496116225                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          360328576500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          348597204750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            869876471190                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            872799536745                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             724.811465                       # Core power per rank (mW)
+system.physmem.averagePower::1             727.247065                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               246247636                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186450048                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15699340                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            168260719                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165258168                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.678177                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18313255                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             100190                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.215537                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18428845                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104881                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452570621                       # DTB read hits
-system.cpu.dtb.read_misses                    4982980                       # DTB read misses
+system.cpu.dtb.read_hits                    452532318                       # DTB read hits
+system.cpu.dtb.read_misses                    4979776                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457553601                       # DTB read accesses
-system.cpu.dtb.write_hits                   161352620                       # DTB write hits
-system.cpu.dtb.write_misses                   1708824                       # DTB write misses
+system.cpu.dtb.read_accesses                457512094                       # DTB read accesses
+system.cpu.dtb.write_hits                   161379130                       # DTB write hits
+system.cpu.dtb.write_misses                   1710165                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163061444                       # DTB write accesses
-system.cpu.dtb.data_hits                    613923241                       # DTB hits
-system.cpu.dtb.data_misses                    6691804                       # DTB misses
+system.cpu.dtb.write_accesses               163089295                       # DTB write accesses
+system.cpu.dtb.data_hits                    613911448                       # DTB hits
+system.cpu.dtb.data_misses                    6689941                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620615045                       # DTB accesses
-system.cpu.itb.fetch_hits                   591467838                       # ITB hits
+system.cpu.dtb.data_accesses                620601389                       # DTB accesses
+system.cpu.itb.fetch_hits                   598579568                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               591467857                       # ITB accesses
+system.cpu.itb.fetch_accesses               598579587                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -345,68 +324,184 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2364526023                       # number of cpu cycles simulated
+system.cpu.numCycles                       2400297316                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      49659953                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      52410829                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.294653                       # CPI: cycles per instruction
-system.cpu.ipc                               0.772408                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2043503290                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       321022733                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.314239                       # CPI: cycles per instruction
+system.cpu.ipc                               0.760897                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2077436531                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       322860785                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121980                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.680046                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601827690                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126076                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.945943                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       16791074000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.680046                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.996260                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996260                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26118.650776                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           749.760915                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           591466882                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               956                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          618689.207113                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           751.335570                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           598578610                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624821.096033                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   749.760915                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.366094                       # Average percentage of cache occupancy
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-system.cpu.icache.tags.occ_task_id_blocks::1024          953                       # Occupied blocks per task id
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 system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          872                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.465332                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1182936632                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1182936632                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    591466882                       # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::cpu.inst          956                       # number of ReadReq misses
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-system.cpu.icache.overall_misses::total           956                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     70103250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     70103250                       # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst    591467838                       # number of ReadReq accesses(hits+misses)
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73329.759414                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73329.759414                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73329.759414                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73329.759414                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73329.759414                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73329.759414                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73021.659708                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73021.659708                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73021.659708                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73021.659708                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73021.659708                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73021.659708                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -415,132 +510,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          956                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          956                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          956                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          956                       # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total          956                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     67802750                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total     67802750                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total     67802750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70923.378661                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70923.378661                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70923.378661                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70923.378661                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70923.378661                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70923.378661                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70615.083507                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70615.083507                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70615.083507                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70615.083507                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70615.083507                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7239710                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7239710                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887318                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887318                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1912                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952762                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21954674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61184                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820908160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820969344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12827646                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           12827646    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total       12827646                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10114441000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1628250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14012098750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements          1928319                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30739.860026                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8981676                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958124                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.586878                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      88667634250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14931.531261                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.328765                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455674                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.avg_refs             4.586924                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      89010017750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14951.432619                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1232                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15516                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106466610                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.163212                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79941.142494                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80934.630899                       # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 80336.017475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80336.017475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80336.017475                       # average overall miss latency
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.214860                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214860                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79992.461019                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79992.461019                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80901.396380                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80901.396380                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80353.731395                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80353.731395                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80353.731395                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80353.731395                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -549,156 +615,93 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1018252                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018252                       # number of writebacks
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163212                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163212                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412992                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214862                       # mshr miss rate for demand accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214862                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.472934                       # average ReadExReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67740.291450                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67740.291450                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132924254000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 132924254000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.412991                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412991                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.214860                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214860                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.214860                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214860                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68314.655062                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67782.668957                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67782.668957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67782.668957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67782.668957                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9121976                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.554959                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           599879563                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126072                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.732504                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       16715078000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.554959                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.996229                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996229                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1616                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2312                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           64                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1227940890                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1227940890                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    441389342                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       441389342                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    158490221                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158490221                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst     599879563                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        599879563                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    599879563                       # number of overall hits
-system.cpu.dcache.overall_hits::total       599879563                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      7289565                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289565                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      2238281                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2238281                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      9527846                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9527846                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      9527846                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9527846                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178191720750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 178191720750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101139344750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 101139344750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 279331065500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 279331065500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 279331065500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 279331065500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    448678907                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    448678907                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    609407409                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    609407409                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    609407409                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    609407409                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.016247                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016247                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.013926                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013926                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.015635                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015635                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.015635                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015635                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24444.767383                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24444.767383                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45186.169543                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45186.169543                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29317.336311                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29317.336311                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29317.336311                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29317.336311                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3700618                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700618                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        50811                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50811                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       401774                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       401774                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       401774                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       401774                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7238754                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238754                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1887318                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887318                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9126072                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126072                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9126072                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126072                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162228644750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 162228644750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  76111394500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  76111394500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238340039250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 238340039250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238340039250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 238340039250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.016133                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016133                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.011742                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011742                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014975                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014975                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014975                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014975                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22411.128317                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22411.128317                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40327.806178                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40327.806178                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26116.388217                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26116.388217                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26116.388217                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26116.388217                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        7239718                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239718                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700593                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887316                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887316                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1916                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952745                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21954661                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820906816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820968128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     12827627                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           12827627    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       12827627                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10114406500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1631750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   14010883500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq             1181592                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1181592                       # Transaction distribution
+system.membus.trans_dist::Writeback           1018242                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            779444                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           779444                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940314                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4940314                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190673792                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190673792                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2979278                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2979278    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total             2979278                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         11833253000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        18446066000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 9172e88dd..b905eb22a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,100 +1,100 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.096187                       # Number of seconds simulated
-sim_ticks                                1096186990500                       # Number of ticks simulated
-final_tick                               1096186990500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.108945                       # Number of seconds simulated
+sim_ticks                                1108944740000                       # Number of ticks simulated
+final_tick                               1108944740000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 245276                       # Simulator instruction rate (inst/s)
-host_op_rate                                   264248                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              174074375                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310916                       # Number of bytes of host memory used
-host_seconds                                  6297.23                       # Real time elapsed on the host
+host_inst_rate                                 239014                       # Simulator instruction rate (inst/s)
+host_op_rate                                   257501                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              171603826                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253696                       # Number of bytes of host memory used
+host_seconds                                  6462.24                       # Real time elapsed on the host
 sim_insts                                  1544563087                       # Number of instructions simulated
 sim_ops                                    1664032480                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst         131551936                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131551936                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     66968384                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          66968384                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst            2055499                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2055499                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1046381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1046381                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            120008664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               120008664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           46007                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              46007                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          61092117                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               61092117                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          61092117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           120008664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              181100781                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2055499                       # Number of read requests accepted
-system.physmem.writeReqs                      1046381                       # Number of write requests accepted
-system.physmem.readBursts                     2055499                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1046381                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                131465088                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     86848                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  66966784                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131551936                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               66968384                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1357                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst         131625408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131625408                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     66989632                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          66989632                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst            2056647                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2056647                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1046713                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1046713                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            118694289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               118694289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           45420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              45420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60408449                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60408449                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60408449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           118694289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              179102739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2056647                       # Number of read requests accepted
+system.physmem.writeReqs                      1046713                       # Number of write requests accepted
+system.physmem.readBursts                     2056647                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1046713                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                131542016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83392                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  66988032                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131625408                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               66989632                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1303                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              127914                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125107                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              122280                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              124254                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              123262                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              128036                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              125234                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              122300                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              124230                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              123415                       # Per bank write bursts
 system.physmem.perBankRdBursts::5              123345                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123865                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124190                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131999                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              134064                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132428                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133673                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133725                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133862                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129895                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             130279                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               65789                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64087                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62403                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               62885                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               62820                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               62979                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64285                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65232                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67082                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67588                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67303                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67613                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67020                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67468                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66169                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65633                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123964                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124409                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131872                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              134140                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132473                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133756                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133901                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             134102                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129958                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             130209                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               65849                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               64131                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62381                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               62840                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               62871                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               62990                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64312                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65310                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67027                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67624                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67292                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67645                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67063                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67560                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66200                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65593                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1096186902500                       # Total gap between requests
+system.physmem.totGap                    1108944651500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2055499                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2056647                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1046381                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1922421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    131703                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1046713                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1923205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    132121                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    31796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    57030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    60853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61519                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    61936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    61675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    31987                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    57104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    60908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62038                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    61631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -189,126 +189,104 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1916158                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.556187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.764224                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.552714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1491113     77.82%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305811     15.96%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52727      2.75%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21051      1.10%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13077      0.68%     98.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6875      0.36%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5570      0.29%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4107      0.21%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        15827      0.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1916158                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61021                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.615247                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      160.737468                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60978     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           19      0.03%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            9      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1918209                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.496643                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.775288                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.095886                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1492147     77.79%     77.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       306422     15.97%     93.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52965      2.76%     96.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21185      1.10%     97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13242      0.69%     98.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7471      0.39%     98.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5204      0.27%     98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3914      0.20%     99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        15659      0.82%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1918209                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61025                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.632724                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      160.189303                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          60982     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61021                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61021                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.147474                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.112394                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.099372                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27727     45.44%     45.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1223      2.00%     47.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              27936     45.78%     93.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3708      6.08%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                355      0.58%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 59      0.10%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 10      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61021                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38533876500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77049039000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10270710000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18759.11                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           61025                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61025                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.151790                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.116821                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.097688                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27581     45.20%     45.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1180      1.93%     47.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28172     46.16%     93.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3706      6.07%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                317      0.52%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 54      0.09%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61025                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38537340500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77075040500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10276720000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18749.83                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37509.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         119.93                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          61.09                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      120.01                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       61.09                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37499.83                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         118.62                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          60.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      118.69                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       60.41                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.41                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.94                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.48                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           1.40                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.93                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     777772                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    406558                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.86                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                       353394.36                       # Average gap between requests
-system.physmem.pageHitRate                      38.20                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     306608104500                       # Time in different power states
-system.physmem.memoryStateTime::REF       36603840000                       # Time in different power states
+system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     777039                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    406774                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.81                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.86                       # Row buffer hit rate for writes
+system.physmem.avgGap                       357336.77                       # Average gap between requests
+system.physmem.pageHitRate                      38.16                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     313164826000                       # Time in different power states
+system.physmem.memoryStateTime::REF       37029980000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      752971887000                       # Time in different power states
+system.physmem.memoryStateTime::ACT      758746776000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                7068978000                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                7417161360                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                3857081250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                4047062250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               7754580600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               8267360400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              3307910400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              3472476480                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           71597111040                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           71597111040                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          413628192720                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          422690389875                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          294876051750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          286926756000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            802089905760                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            804418317405                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             731.713906                       # Core power per rank (mW)
-system.physmem.averagePower::1             733.838021                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq             1255486                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1255486                       # Transaction distribution
-system.membus.trans_dist::Writeback           1046381                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            800013                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           800013                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5157379                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5157379                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198520320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198520320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3101880                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3101880    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3101880                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         12229457500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        19361348500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               239650352                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186306880                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14598405                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131764254                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               121991524                       # Number of BTB hits
+system.physmem.actEnergy::0                7075638360                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                7426006560                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                3860715375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                4051888500                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               7760165400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               8271151200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              3309232320                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              3473305920                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0           72430640880                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1           72430640880                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          416866648005                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          425333204280                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          299692308000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          292265504250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            810995348340                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            813251701590                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             731.323936                       # Core power per rank (mW)
+system.physmem.averagePower::1             733.358627                       # Core power per rank (mW)
+system.cpu.branchPred.lookups               240152510                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186756179                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14598640                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            131763268                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122287171                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.583171                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15654227                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             92.808241                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15660181                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -394,69 +372,193 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2192373981                       # number of cpu cycles simulated
+system.cpu.numCycles                       2217889480                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563087                       # Number of instructions committed
 system.cpu.committedOps                    1664032480                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      42081657                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      40077128                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.419414                       # CPI: cycles per instruction
-system.cpu.ipc                               0.704516                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1808241834                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       384132147                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.435933                       # CPI: cycles per instruction
+system.cpu.ipc                               0.696411                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1838736315                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       379153165                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9224311                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.608602                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624084220                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9228407                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.626430                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        9776044000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4085.608602                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.997463                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997463                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          259                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1292                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2484                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1276551305                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276551305                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    453737568                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453737568                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    170346530                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170346530                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst           61                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst           61                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     624084098                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624084098                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    624084098                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624084098                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      7337712                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7337712                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      2239517                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2239517                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      9577229                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9577229                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      9577229                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9577229                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 183598363496                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 101566510500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 285164873996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 285164873996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    461075280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461075280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    633661327                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633661327                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    633661327                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633661327                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.015914                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015914                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012976                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012976                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.015114                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015114                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.015114                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015114                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29775.300768                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29775.300768                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      3700618                       # number of writebacks
+system.cpu.dcache.writebacks::total           3700618                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          213                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          213                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       348609                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       348609                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       348822                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       348822                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       348822                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       348822                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7337499                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7337499                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1890908                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890908                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9228407                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9228407                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9228407                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9228407                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  77457723500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77457723500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 245963549754                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 245963549754                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.015914                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015914                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.010956                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014564                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014564                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014564                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014564                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.tagsinuse           661.144399                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           464861353                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           661.026879                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           466133968                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          566904.089024                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          568456.058537                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   661.144399                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322824                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322824                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   661.026879                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322767                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322767                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          753                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         929725166                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        929725166                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    464861353                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       464861353                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     464861353                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        464861353                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    464861353                       # number of overall hits
-system.cpu.icache.overall_hits::total       464861353                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         932270396                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        932270396                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    466133968                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       466133968                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     466133968                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        466133968                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    466133968                       # number of overall hits
+system.cpu.icache.overall_hits::total       466133968                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
 system.cpu.icache.overall_misses::total           820                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     59141749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     59141749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     59141749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     59141749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     59141749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     59141749                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    464862173                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    464862173                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    464862173                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    464862173                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    464862173                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    464862173                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     58416499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     58416499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     58416499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     58416499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     58416499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     58416499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    466134788                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    466134788                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    466134788                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    466134788                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    466134788                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    466134788                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72124.084146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72124.084146                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71239.632927                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71239.632927                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71239.632927                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71239.632927                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71239.632927                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71239.632927                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -471,38 +573,159 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          820
 system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     57178251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     57178251                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     57178251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     57178251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     57178251                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     57178251                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56453501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     56453501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56453501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     56453501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56453501                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     56453501                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68845.732927                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68845.732927                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68845.732927                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68845.732927                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68845.732927                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68845.732927                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        7336783                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7336783                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890869                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890869                       # Transaction distribution
+system.cpu.l2cache.tags.replacements          2023942                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31254.337993                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8984488                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2053718                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.374743                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      59502848750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14996.949277                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 16257.388715                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.457671                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.496136                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.953807                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29776                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1248                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107383386                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107383386                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      6081991                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6081991                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3700618                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3700618                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst      1090584                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1090584                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100398878250                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  64605165750                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst 165004044000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::total 165004044000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      7338319                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7338319                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3700618                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1890908                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total      9229227                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171201                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.171201                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.423249                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.423249                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.222841                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.222841                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.222841                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.222841                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79914.543216                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79914.543216                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80723.764063                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80723.764063                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80229.442803                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80229.442803                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80229.442803                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80229.442803                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks      1046713                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1046713                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1256323                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1256323                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       800324                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       800324                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      2056647                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2056647                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      2056647                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2056647                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  84521118250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84521118250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  54527231750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54527231750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171200                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171200                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.423249                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423249                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.222841                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.222841                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.222841                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.222841                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        7338319                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7338319                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890908                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890908                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22154304                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22155944                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22157432                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22159072                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827358208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          827410688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    827457600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          827510080                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     12928292                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples     12929845                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
@@ -511,262 +734,41 @@ system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Re
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           12928292    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           12929845    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       12928292                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10164786000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       12929845                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10165540500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1391749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1391499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14185031745                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14187091746                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements          2022796                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31252.383158                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8984119                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2052571                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.377008                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      58953869250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.456767                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.496980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.953747                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        107369776                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       107369776                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      6081291                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6081291                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3700640                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3700640                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst      1090856                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1090856                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      7172147                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7172147                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      7172147                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7172147                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst      1255492                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1255492                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       800013                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       800013                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst      2055505                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2055505                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst      2055505                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2055505                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 100333400500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  64526294750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  64526294750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 164859695250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 164859695250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      7336783                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7336783                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3700640                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3700640                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1890869                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1890869                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      9227652                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9227652                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      9227652                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9227652                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171123                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.171123                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.423093                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.423093                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.222755                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.222755                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.222755                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.222755                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1046381                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1046381                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1255486                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1255486                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       800013                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       800013                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      2055499                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2055499                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      2055499                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2055499                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  84544683250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  84544683250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  54440940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  54440940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171122                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.171122                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.423093                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423093                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.222754                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.222754                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.222754                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.222754                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9222736                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.561884                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624006676                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9226832                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.629569                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        9704965000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4085.561884                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.997452                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997452                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          280                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1316                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2439                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276393554                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276393554                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    453661018                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453661018                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    170345536                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170345536                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst           61                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst           61                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     624006554                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624006554                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    624006554                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624006554                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      7336174                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7336174                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      2240511                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2240511                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst      9576685                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9576685                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      9576685                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9576685                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 183520141245                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 101423015250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 284943156495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 284943156495                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    460997192                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    460997192                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    633583239                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633583239                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    633583239                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633583239                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.015914                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015914                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012982                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012982                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.015115                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015115                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.015115                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015115                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29753.840342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29753.840342                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3700640                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700640                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       349642                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       349642                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       349853                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       349853                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       349853                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       349853                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7335963                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7335963                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1890869                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890869                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9226832                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9226832                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9226832                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9226832                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  77354259500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77354259500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 245785449755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 245785449755                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.015913                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015913                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014563                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014563                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014563                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014563                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq             1256323                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1256323                       # Transaction distribution
+system.membus.trans_dist::Writeback           1046713                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            800324                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           800324                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5160007                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5160007                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198615040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198615040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3103360                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3103360    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total             3103360                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         12130659500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        19439818500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index d4fe531fc..38e101aaf 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,46 +1,46 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.051523                       # Number of seconds simulated
-sim_ticks                                 51522973500                       # Number of ticks simulated
-final_tick                                51522973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.052167                       # Number of seconds simulated
+sim_ticks                                 52167245000                       # Number of ticks simulated
+final_tick                                52167245000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 234694                       # Simulator instruction rate (inst/s)
-host_op_rate                                   234694                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              131574801                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241032                       # Number of bytes of host memory used
-host_seconds                                   391.59                       # Real time elapsed on the host
+host_inst_rate                                 231551                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231551                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              131435822                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240584                       # Number of bytes of host memory used
+host_seconds                                   396.90                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            340096                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202432                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               5314                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5314                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              6600861                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6600861                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3928966                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3928966                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             6600861                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6600861                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5314                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            340352                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               340352                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202688                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               5318                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5318                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              6524247                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6524247                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3885350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3885350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             6524247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6524247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5318                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5314                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5318                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   340096                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   340352                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    340096                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    340352                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 468                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 295                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 307                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 524                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 224                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 238                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 222                       # Per bank write bursts
@@ -48,8 +48,8 @@ system.physmem.perBankRdBursts::7                 289                       # Pe
 system.physmem.perBankRdBursts::8                 251                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                255                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                260                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                408                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                261                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                409                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                344                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                500                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                448                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     51522892000                       # Total gap between requests
+system.physmem.totGap                     52167163500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5314                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5318                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -86,8 +86,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4906                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       387                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          963                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      352.232606                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.271932                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.609683                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            308     31.98%     31.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          198     20.56%     52.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           99     10.28%     62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           77      8.00%     70.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           83      8.62%     79.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           29      3.01%     82.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           26      2.70%     85.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      2.91%     88.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          115     11.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            963                       # Bytes accessed per row activation
-system.physmem.totQLat                       35638500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 135276000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26570000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6706.53                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.254620                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     211.254822                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.143137                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            322     33.06%     33.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          190     19.51%     52.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           96      9.86%     62.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          102     10.47%     72.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           61      6.26%     79.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           36      3.70%     82.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           25      2.57%     85.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           25      2.57%     87.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          117     12.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            974                       # Bytes accessed per row activation
+system.physmem.totQLat                       31955000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 131667500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26590000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6008.84                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25456.53                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24758.84                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.60                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
@@ -212,88 +212,65 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4346                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4336                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.78                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.53                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9695689.12                       # Average gap between requests
-system.physmem.pageHitRate                      81.78                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      48467499750                       # Time in different power states
-system.physmem.memoryStateTime::REF        1720420000                       # Time in different power states
+system.physmem.avgGap                      9809545.60                       # Average gap between requests
+system.physmem.pageHitRate                      81.53                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      49062382500                       # Time in different power states
+system.physmem.memoryStateTime::REF        1741740000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1333970250                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1356240000                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   3470040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   3810240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   1893375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2079000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 19999200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 21340800                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                   3530520                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                   3787560                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                   1926375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                   2066625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                 19827600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                 21216000                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            3365141520                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            3365141520                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            1727742960                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            1771093170                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           29397561750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           29359535250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             34515808845                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             34522999980                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.925309                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.064883                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                3595                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3595                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10628                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10628                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  340096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5314                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5314    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5314                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6106500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           49715250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                11407319                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8177175                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            788662                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6672694                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5348459                       # Number of BTB hits
+system.physmem.refreshEnergy::0            3406843440                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1            3406843440                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0            1740241350                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1            1807017705                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0           29769681750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1           29711106000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0             34942051035                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1             34952037330                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.896806                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.088260                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                11476347                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8235349                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            785844                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6672654                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5371509                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.154417                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1172952                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             80.500338                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1176736                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20390003                       # DTB read hits
-system.cpu.dtb.read_misses                      46972                       # DTB read misses
+system.cpu.dtb.read_hits                     20396755                       # DTB read hits
+system.cpu.dtb.read_misses                      47141                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20436975                       # DTB read accesses
-system.cpu.dtb.write_hits                     6579991                       # DTB write hits
-system.cpu.dtb.write_misses                       273                       # DTB write misses
+system.cpu.dtb.read_accesses                 20443896                       # DTB read accesses
+system.cpu.dtb.write_hits                     6580249                       # DTB write hits
+system.cpu.dtb.write_misses                       266                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580264                       # DTB write accesses
-system.cpu.dtb.data_hits                     26969994                       # DTB hits
-system.cpu.dtb.data_misses                      47245                       # DTB misses
+system.cpu.dtb.write_accesses                 6580515                       # DTB write accesses
+system.cpu.dtb.data_hits                     26977004                       # DTB hits
+system.cpu.dtb.data_misses                      47407                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27017239                       # DTB accesses
-system.cpu.itb.fetch_hits                    22956157                       # ITB hits
+system.cpu.dtb.data_accesses                 27024411                       # DTB accesses
+system.cpu.itb.fetch_hits                    23068125                       # ITB hits
 system.cpu.itb.fetch_misses                        88                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                22956245                       # ITB accesses
+system.cpu.itb.fetch_accesses                23068213                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,255 +284,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        103045947                       # number of cpu cycles simulated
+system.cpu.numCycles                        104334490                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2250214                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2153944                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.121246                       # CPI: cycles per instruction
-system.cpu.ipc                               0.891865                       # IPC: instructions per cycle
-system.cpu.tickCycles                       100852672                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         2193275                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements             13697                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.302767                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22940496                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15661                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1464.816806                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.302767                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.800929                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.800929                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          670                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          947                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45927975                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45927975                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22940496                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22940496                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22940496                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22940496                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22940496                       # number of overall hits
-system.cpu.icache.overall_hits::total        22940496                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        15661                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15661                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        15661                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15661                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        15661                       # number of overall misses
-system.cpu.icache.overall_misses::total         15661                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    386976750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    386976750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    386976750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    386976750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    386976750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    386976750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22956157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22956157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22956157                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22956157                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22956157                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22956157                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000682                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000682                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000682                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000682                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000682                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000682                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24709.581125                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24709.581125                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15661                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15661                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15661                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15661                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15661                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15661                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    354287250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    354287250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    354287250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    354287250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    354287250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    354287250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000682                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000682                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000682                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq          16146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         16146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31322                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4567                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             35889                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1002304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1151872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        17998                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              17998    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          17998                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        9106000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24175250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3734000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2477.584038                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              12565                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3661                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             3.432122                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.790277                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2459.793761                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075067                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.075610                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3661                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          768                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          181                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2504                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111725                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           149390                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          149390                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12551                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          12551                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12577                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           12577                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12577                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          12577                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3595                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3595                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         1719                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         5314                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5314                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         5314                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5314                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    246128750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    246128750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    116497000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    116497000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    362625750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    362625750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    362625750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    362625750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        16146                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        16146                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        17891                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        17891                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        17891                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        17891                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.222656                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.222656                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.297021                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.297021                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.297021                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.297021                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3595                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3595                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         5314                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5314                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         5314                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5314                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    200952250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    200952250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     94943500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     94943500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    295895750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    295895750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    295895750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    295895750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.222656                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.222656                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.297021                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.297021                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.297021                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.297021                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.cpi                               1.135266                       # CPI: cycles per instruction
+system.cpu.ipc                               0.880851                       # IPC: instructions per cycle
+system.cpu.tickCycles                       102681426                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1653064                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.555792                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26545428                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1448.700924                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26568138                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11903.779372                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11913.963229                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.555792                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.353651                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353651                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.700924                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.353687                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353687                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
@@ -563,16 +311,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          226
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53099946                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53099946                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     20047236                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20047236                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          53145366                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53145366                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20069946                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20069946                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.inst      6498192                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        6498192                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst      26545428                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26545428                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     26545428                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26545428                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.inst      26568138                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26568138                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     26568138                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26568138                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.inst          519                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           519                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.inst         2911                       # number of WriteReq misses
@@ -581,22 +329,22 @@ system.cpu.dcache.demand_misses::cpu.inst         3430                       # n
 system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst         3430                       # number of overall misses
 system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     37054000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     37054000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    196991000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    196991000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    234045000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    234045000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    234045000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    234045000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20047755                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20047755                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     37712750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     37712750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    194587500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    194587500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    232300250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    232300250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    232300250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    232300250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20070465                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20070465                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     26548858                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26548858                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     26548858                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26548858                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.inst     26571568                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26571568                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     26571568                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26571568                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000448                       # miss rate for WriteReq accesses
@@ -605,14 +353,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000129
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68234.693878                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68234.693878                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67726.020408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67726.020408                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -639,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     33506000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33506000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    118502500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    118502500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    152008500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    152008500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    152008500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    152008500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     34134000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34134000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    117191500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    117191500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    151325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    151325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    151325500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    151325500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000268                       # mshr miss rate for WriteReq accesses
@@ -655,14 +403,266 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements             13871                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1640.666168                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            23052289                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15835                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1455.780802                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.666168                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801107                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801107                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          669                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          148                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          948                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          46152085                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         46152085                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     23052289                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        23052289                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      23052289                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         23052289                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     23052289                       # number of overall hits
+system.cpu.icache.overall_hits::total        23052289                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15836                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15836                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15836                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15836                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15836                       # number of overall misses
+system.cpu.icache.overall_misses::total         15836                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    386603500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    386603500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    386603500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    386603500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    386603500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    386603500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     23068125                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     23068125                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     23068125                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     23068125                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     23068125                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     23068125                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000686                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000686                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000686                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000686                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000686                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000686                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24412.951503                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24412.951503                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15836                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15836                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15836                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15836                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15836                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15836                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353567500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    353567500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    353567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353567500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    353567500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000686                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000686                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2479.834280                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              12735                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3665                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.474761                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.780071                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2462.054210                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075136                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.075679                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3665                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          768                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2506                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111847                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           150786                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          150786                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12721                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          12721                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        12747                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           12747                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12747                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          12747                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3599                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3599                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         1719                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         5318                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5318                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         5318                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5318                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    244164500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    244164500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    115186000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    115186000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    359350500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    359350500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    359350500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    359350500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        16320                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        16320                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        18065                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        18065                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        18065                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        18065                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.220527                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.220527                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.985100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.294381                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.294381                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.294381                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.294381                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3599                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3599                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1719                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5318                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5318                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5318                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5318                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    198927000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    198927000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     93369000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     93369000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    292296000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    292296000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    292296000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    292296000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.220527                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.220527                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.294381                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.294381                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.294381                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.294381                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq          16320                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16320                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31670                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4567                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             36237                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1013440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1163008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        18172                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              18172    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total          18172                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        9193000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      24435500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       3734500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                3599                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3599                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10636                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10636                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  340352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              5318                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5318    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                5318                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6477500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           50028000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 5a483b5e7..be651ff21 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,38 +1,38 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.131652                       # Number of seconds simulated
-sim_ticks                                131652469500                       # Number of ticks simulated
-final_tick                               131652469500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.131746                       # Number of seconds simulated
+sim_ticks                                131745950000                       # Number of ticks simulated
+final_tick                               131745950000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 162179                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170963                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              123906567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259776                       # Number of bytes of host memory used
-host_seconds                                  1062.51                       # Real time elapsed on the host
+host_inst_rate                                 190259                       # Simulator instruction rate (inst/s)
+host_op_rate                                   200564                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              145463120                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256996                       # Number of bytes of host memory used
+host_seconds                                   905.70                       # Real time elapsed on the host
 sim_insts                                   172317809                       # Number of instructions simulated
 sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            247616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               247616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       138304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          138304                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3869                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3869                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1880831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1880831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1050523                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1050523                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1880831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1880831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3869                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            247488                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               247488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       138176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          138176                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3867                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3867                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1878525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1878525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1048806                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1048806                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1878525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1878525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3867                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3869                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3867                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   247616                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   247488                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    247616                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    247488                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -42,14 +42,14 @@ system.physmem.perBankRdBursts::1                 217                       # Pe
 system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 308                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 306                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 305                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                201                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                182                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                199                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                203                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    131652381500                       # Total gap between requests
+system.physmem.totGap                    131745861500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3869                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3867                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -87,8 +87,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                      3616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       238                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          904                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      272.070796                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.793599                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     280.048713                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            264     29.20%     29.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          351     38.83%     68.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           86      9.51%     77.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           48      5.31%     82.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      3.87%     86.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           23      2.54%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      1.88%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           16      1.77%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           64      7.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            904                       # Bytes accessed per row activation
-system.physmem.totQLat                       27698500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100242250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19345000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7159.09                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          912                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      269.543860                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.691365                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     273.658023                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            266     29.17%     29.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          353     38.71%     67.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           82      8.99%     76.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           61      6.69%     83.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           33      3.62%     87.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           27      2.96%     90.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           14      1.54%     91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           19      2.08%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           57      6.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            912                       # Bytes accessed per row activation
+system.physmem.totQLat                       28129500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100635750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19335000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7274.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25909.09                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26024.24                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
@@ -212,68 +212,45 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2960                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2950                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.51                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.29                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34027495.86                       # Average gap between requests
-system.physmem.pageHitRate                      76.51                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     125800686500                       # Time in different power states
-system.physmem.memoryStateTime::REF        4396080000                       # Time in different power states
+system.physmem.avgGap                     34069268.55                       # Average gap between requests
+system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     125856871250                       # Time in different power states
+system.physmem.memoryStateTime::REF        4399200000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1453435500                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1487617250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   3039120                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   3780000                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   1658250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2062500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 16185000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 13774800                       # Energy for read commands per rank (pJ)
+system.physmem.actEnergy::0                   3092040                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                   3787560                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                   1687125                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                   2066625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                 16177200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                 13767000                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            8598732480                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            8598732480                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            3574139400                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            3578406705                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           75854895000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           75851151750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             88048649250                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             88047908235                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.807689                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.802060                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                2779                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2779                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7738                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7738                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  247616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3869                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3869    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3869                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4528000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           36225250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                49915423                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39661220                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5747038                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24423675                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23301282                       # Number of BTB hits
+system.physmem.refreshEnergy::0            8604835200                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1            8604835200                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0            3575888730                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1            3595740120                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0           75909421500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1           75892008000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0             88111101795                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1             88112204505                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.807404                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.815774                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                49935043                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39664695                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5744224                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24405530                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23309445                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.404488                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1905800                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             95.508866                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1908457                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -359,330 +336,91 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        263304939                       # number of cpu cycles simulated
+system.cpu.numCycles                        263491900                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317809                       # Number of instructions committed
 system.cpu.committedOps                     181650742                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11787313                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11758002                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.528019                       # CPI: cycles per instruction
-system.cpu.ipc                               0.654442                       # IPC: instructions per cycle
-system.cpu.tickCycles                       255940225                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         7364714                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements              2881                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1424.983856                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71509873                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4678                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15286.420051                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1424.983856                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.695793                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.695793                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.877441                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         143033782                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        143033782                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71509873                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71509873                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71509873                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71509873                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71509873                       # number of overall hits
-system.cpu.icache.overall_hits::total        71509873                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4679                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4679                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4679                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4679                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4679                       # number of overall misses
-system.cpu.icache.overall_misses::total          4679                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    184816496                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    184816496                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    184816496                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    184816496                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    184816496                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    184816496                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71514552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71514552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71514552                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71514552                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71514552                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71514552                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000065                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000065                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000065                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000065                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000065                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39499.144262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39499.144262                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4679                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4679                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4679                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4679                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4679                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4679                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    174539504                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    174539504                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    174539504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    174539504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    174539504                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    174539504                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000065                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000065                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           5390                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5389                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9357                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3634                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             12991                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             416192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6504                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5               6504    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6504                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        3268000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7477496                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2996735                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2001.642948                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2592                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2787                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.930032                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.028976                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1998.613972                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060993                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.061085                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2787                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          535                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          142                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085052                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            55917                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           55917                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2591                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2591                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2599                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2599                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2599                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2599                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2799                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2799                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         1090                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3889                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3889                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3889                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3889                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    190706250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    190706250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75951500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     75951500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    266657750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    266657750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    266657750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    266657750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         5390                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5390                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6488                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6488                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6488                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6488                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.519295                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.519295                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.599414                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.599414                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.599414                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.599414                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           19                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           19                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2780                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2780                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3870                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3870                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3870                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3870                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    154681250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    154681250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     62286000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     62286000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    216967250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    216967250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    216967250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    216967250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.515770                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.515770                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.596486                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.596486                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.596486                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.596486                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.cpi                               1.529104                       # CPI: cycles per instruction
+system.cpu.ipc                               0.653978                       # IPC: instructions per cycle
+system.cpu.tickCycles                       257145198                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6346702                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1376.810186                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40745471                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1809                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22523.754008                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1377.772721                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40762987                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22520.987293                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1376.810186                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.336135                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336135                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1767                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1377.772721                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.336370                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336370                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          269                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1357                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.431396                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81497573                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81497573                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     28338014                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28338014                       # number of ReadReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          81532656                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81532656                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     28355530                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28355530                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.inst     12362643                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       12362643                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.inst        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      40700657                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40700657                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     40700657                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40700657                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst          767                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           767                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.inst      40718173                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40718173                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     40718173                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40718173                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          792                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           792                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.inst         1644                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         1644                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst         2411                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2411                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst         2411                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2411                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     52005983                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     52005983                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115743750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    115743750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    167749733                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    167749733                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    167749733                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    167749733                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     28338781                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28338781                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.inst         2436                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2436                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         2436                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2436                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     54011984                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     54011984                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115580250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    115580250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    169592234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    169592234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    169592234                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    169592234                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     28356322                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28356322                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     40703068                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40703068                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     40703068                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40703068                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.inst     40720609                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40720609                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     40720609                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40720609                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000028                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000133                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.000059                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000059                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.000059                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000059                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69576.828287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69576.828287                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.000060                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.000060                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69619.143678                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69619.143678                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -693,30 +431,30 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           80                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.inst          546                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          546                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst          602                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          602                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst          602                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          602                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          711                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.inst          626                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          626                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst          626                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          626                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          712                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         1098                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         1809                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1809                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     47475265                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     47475265                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     77131500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     77131500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    124606765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    124606765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    124606765                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    124606765                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.inst         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         1810                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     47293264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     47293264                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     76493500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     76493500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    123786764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    123786764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    123786764                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    123786764                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000089                       # mshr miss rate for WriteReq accesses
@@ -725,14 +463,276 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000044
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements              2909                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1424.880839                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            71614329                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4705                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15220.898831                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1424.880839                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695743                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695743                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          492                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1068                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.876953                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         143242775                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        143242775                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     71614329                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        71614329                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      71614329                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         71614329                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     71614329                       # number of overall hits
+system.cpu.icache.overall_hits::total        71614329                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4706                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4706                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4706                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4706                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4706                       # number of overall misses
+system.cpu.icache.overall_misses::total          4706                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    186392247                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    186392247                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    186392247                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    186392247                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    186392247                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    186392247                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     71619035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     71619035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     71619035                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     71619035                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     71619035                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     71619035                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39607.362303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39607.362303                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4706                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4706                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4706                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4706                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4706                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4706                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    176061753                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    176061753                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    176061753                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    176061753                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    176061753                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    176061753                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2001.520468                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2624                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2785                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.942190                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.029184                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1998.491284                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060989                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.061082                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2785                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          522                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          153                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2005                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084991                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            56139                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           56139                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2623                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2623                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2631                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2631                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2631                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2631                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2795                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2795                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         1090                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3885                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3885                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3885                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3885                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191698500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    191698500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75314000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     75314000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    267012500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    267012500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    267012500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    267012500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         5418                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5418                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1098                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6516                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6516                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6516                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6516                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.515873                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.515873                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.992714                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.596225                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.596225                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.596225                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.596225                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2778                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2778                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3868                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3868                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3868                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3868                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    155803750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    155803750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     61486500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     61486500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    217290250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    217290250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    217290250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    217290250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.512735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.512735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.992714                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.593616                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.593616                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.593616                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.593616                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq           5418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5417                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9411                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3636                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             13047                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       301120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             417984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples         6532                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5               6532    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total           6532                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        3282000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       7517747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       2996736                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                2777                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2777                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7734                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7734                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  247488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              3867                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3867    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                3867                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             4723500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           36361250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 973b187d4..01efe7b2f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,309 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.869358                       # Number of seconds simulated
-sim_ticks                                1869357988000                       # Number of ticks simulated
-final_tick                               1869357988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1869358498000                       # Number of ticks simulated
+final_tick                               1869358498000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2868261                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2868259                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            82489350498                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 370556                       # Number of bytes of host memory used
-host_seconds                                    22.66                       # Real time elapsed on the host
-sim_insts                                    64999904                       # Number of instructions simulated
-sim_ops                                      64999904                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1825215                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1825215                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            52491614317                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318168                       # Number of bytes of host memory used
+host_seconds                                    35.61                       # Real time elapsed on the host
+sim_insts                                    65000470                       # Number of instructions simulated
+sim_ops                                      65000470                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           765760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         66552064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         66539648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           106432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           766208                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           106560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           771648                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68196992                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             68179008                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst       765760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       106560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          872320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5174080                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7833408                       # Number of bytes written to this memory
+system.physmem.bytes_inst_read::cpu1.inst       106432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          872192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7831360                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7831360                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.inst             11965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1039876                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1039682                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1663                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11972                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1665                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             12057                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1065578                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           80845                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122397                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1065297                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122365                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122365                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.inst              409638                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35601562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            35594910                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              409878                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               57004                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              412788                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36481505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36471874                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu0.inst         409638                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          57004                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466641                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2767838                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1422589                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4190427                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2767838                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56935                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4189330                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4189330                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4189330                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.inst             409638                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35601562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1423102                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              57004                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             412788                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40671931                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              948901                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948901                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14588                       # Transaction distribution
-system.membus.trans_dist::Writeback             80845                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            19618                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          14179                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            8160                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            126515                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           124290                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        44074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      2256153                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      2300227                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83462                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83462                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2383689                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73370112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     73456274                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2670784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2670784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                76127058                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1224161                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1224161    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1224161                       # Request fanout histogram
+system.physmem.bw_total::cpu0.data           35594910                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             409878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              514                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40661204                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   999765                       # number of replacements
-system.l2c.tags.tagsinuse                65320.982867                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2387620                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1064815                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.242286                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   56016.884833                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4834.504330                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4176.028554                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      178.991920                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      114.573230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.854750                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073769                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.063721                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002731                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001748                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996719                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65050                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          768                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         3271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6128                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5934                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48949                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.992584                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 31465722                       # Number of tag accesses
-system.l2c.tags.data_accesses                31465722                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             606953                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             626726                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             379523                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             129013                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1742215                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          777631                       # number of Writeback hits
-system.l2c.Writeback_hits::total               777631                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             116                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             577                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 693                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            13                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           111430                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            56603                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               168033                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              606953                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              738156                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              379523                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              185616                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1910248                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             606953                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             738156                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             379523                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             185616                       # number of overall hits
-system.l2c.overall_hits::total                1910248                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11965                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           926610                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1665                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1033                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               941273                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          3006                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2175                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              5181                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         1175                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1110                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2285                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113916                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          11068                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             124984                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11965                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data           1040526                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1665                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             12101                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1066257                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11965                       # number of overall misses
-system.l2c.overall_misses::cpu0.data          1040526                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1665                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            12101                       # number of overall misses
-system.l2c.overall_misses::total              1066257                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst         618918                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1553336                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         381188                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         130046                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2683488                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       777631                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           777631                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3122                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2752                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5874                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1212                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1123                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2335                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       225346                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        67671                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           293017                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          618918                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1778682                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          381188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          197717                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2976505                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         618918                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1778682                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         381188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         197717                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2976505                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.019332                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.596529                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004368                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.007943                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.350765                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962844                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.790334                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.882022                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.969472                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.988424                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.978587                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.505516                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.163556                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.426542                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.019332                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.584998                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004368                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.061204                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.358224                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.019332                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.584998                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004368                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.061204                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.358224                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               80845                       # number of writebacks
-system.l2c.writebacks::total                    80845                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.434096                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1685787163517                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.434096                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.027131                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.027131                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
-system.iocache.tags.data_accesses              375579                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide          179                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               179                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          179                       # number of overall misses
-system.iocache.overall_misses::total              179                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          179                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             179                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          179                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            179                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7758808                       # DTB read hits
+system.cpu0.dtb.read_hits                     7758839                       # DTB read hits
 system.cpu0.dtb.read_misses                      7155                       # DTB read misses
 system.cpu0.dtb.read_acv                          152                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  531148                       # DTB read accesses
-system.cpu0.dtb.write_hits                    4740251                       # DTB write hits
+system.cpu0.dtb.write_hits                    4740268                       # DTB write hits
 system.cpu0.dtb.write_misses                      732                       # DTB write misses
 system.cpu0.dtb.write_acv                         102                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 201714                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12499059                       # DTB hits
+system.cpu0.dtb.data_hits                    12499107                       # DTB hits
 system.cpu0.dtb.data_misses                      7887                       # DTB misses
 system.cpu0.dtb.data_acv                          254                       # DTB access violations
 system.cpu0.dtb.data_accesses                  732862                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3525726                       # ITB hits
+system.cpu0.itb.fetch_hits                    3525737                       # ITB hits
 system.cpu0.itb.fetch_misses                     3572                       # ITB misses
 system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_accesses                3529298                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3529309                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -316,32 +83,32 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3738722771                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3738723791                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   49477745                       # Number of instructions committed
-system.cpu0.committedOps                     49477745                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             46201705                       # Number of integer alu accesses
+system.cpu0.committedInsts                   49478313                       # Number of instructions committed
+system.cpu0.committedOps                     49478313                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             46202260                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                197598                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1124633                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6043603                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    46201705                       # number of integer instructions
+system.cpu0.num_func_calls                    1124639                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6043708                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    46202260                       # number of integer instructions
 system.cpu0.num_fp_insts                       197598                       # number of float instructions
-system.cpu0.num_int_register_reads           64003225                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          34834421                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           64004164                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          34834852                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads               97440                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes              98967                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12536107                       # number of memory refs
-system.cpu0.num_load_insts                    7783754                       # Number of load instructions
-system.cpu0.num_store_insts                   4752353                       # Number of store instructions
-system.cpu0.num_idle_cycles              3689239788.666409                       # Number of idle cycles
-system.cpu0.num_busy_cycles              49482982.333591                       # Number of busy cycles
+system.cpu0.num_mem_refs                     12536155                       # number of memory refs
+system.cpu0.num_load_insts                    7783785                       # Number of load instructions
+system.cpu0.num_store_insts                   4752370                       # Number of store instructions
+system.cpu0.num_idle_cycles              3689240240.665401                       # Number of idle cycles
+system.cpu0.num_busy_cycles              49483550.334599                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.013235                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.986765                       # Percentage of idle cycles
-system.cpu0.Branches                          7530826                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2589816      5.23%      5.23% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 33436017     67.57%     72.80% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50540      0.10%     72.90% # Class of executed instruction
+system.cpu0.Branches                          7530941                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2589824      5.23%      5.23% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 33436514     67.57%     72.80% # Class of executed instruction
+system.cpu0.op_class::IntMult                   50547      0.10%     72.90% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     72.90% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                  27840      0.06%     72.96% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     72.96% # Class of executed instruction
@@ -369,38 +136,38 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.96% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.96% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.96% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7945590     16.06%     89.02% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4758292      9.62%     98.63% # Class of executed instruction
-system.cpu0.op_class::IprAccess                675558      1.37%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7945621     16.06%     89.02% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4758309      9.62%     98.63% # Class of executed instruction
+system.cpu0.op_class::IprAccess                675566      1.37%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  49485886                       # Class of executed instruction
+system.cpu0.op_class::total                  49486454                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6794                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    150435                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    150436                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   51398     40.00%     40.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    243      0.19%     40.19% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    243      0.19%     40.18% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1907      1.48%     41.67% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    514      0.40%     42.07% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  74446     57.93%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              128508                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  74447     57.93%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              128509                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    51050     48.97%     48.97% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     243      0.23%     49.20% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1907      1.83%     51.03% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     514      0.49%     51.52% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   50536     48.48%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               104250                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1853222721000     99.14%     99.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1853222948500     99.14%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::22               82001000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               57621500      0.00%     99.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            15975327000      0.85%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1869357780500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            15975609500      0.85%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1869358290500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.993229                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.678828                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811234                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.678818                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811227                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.63%      2.63% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.77%     11.40% # number of syscalls executed
 system.cpu0.kern.syscall::4                         2      0.88%     12.28% # number of syscalls executed
@@ -440,7 +207,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.46% # nu
 system.cpu0.kern.callpal::swpctx                 2743      2.02%      2.47% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      39      0.03%      2.50% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.01%      2.51% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               121668     89.51%     92.02% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               121669     89.51%     92.02% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6149      4.52%     96.54% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.54% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.54% # number of callpals executed
@@ -449,179 +216,28 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.55% # nu
 system.cpu0.kern.callpal::rti                    4175      3.07%     99.62% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 369      0.27%     99.89% # number of callpals executed
 system.cpu0.kern.callpal::imb                     146      0.11%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                135929                       # number of callpals executed
+system.cpu0.kern.callpal::total                135930                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             6593                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1174                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1172                      
-system.cpu0.kern.mode_good::user                 1173                      
+system.cpu0.kern.mode_good::kernel               1173                      
+system.cpu0.kern.mode_good::user                 1174                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.177764                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.177916                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.301957                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1868349152500     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1008627000      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.302176                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1868349657500     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1008632000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    2744                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2732156                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2732156                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14588                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           777631                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           19617                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         14229                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          33846                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295242                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295242                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1237878                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4301883                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       762376                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       627158                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6929295                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     39612096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155765243                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     24396032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23357911                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              243131282                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           41895                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3873157                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.010774                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.103239                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3831426     98.92%     98.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41731      1.08%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3873157                       # Request fanout histogram
-system.iobus.trans_dist::ReadReq                 7628                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7628                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              14588                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14686                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18036                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        44074                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  127536                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        58744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9018                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2747818                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.icache.tags.replacements           618292                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.240644                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           48866947                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           618804                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            78.969992                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9786048500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.240644                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998517                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998517                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         50104825                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        50104825                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     48866947                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       48866947                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     48866947                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        48866947                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     48866947                       # number of overall hits
-system.cpu0.icache.overall_hits::total       48866947                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       618939                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       618939                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       618939                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        618939                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       618939                       # number of overall misses
-system.cpu0.icache.overall_misses::total       618939                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     49485886                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     49485886                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     49485886                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     49485886                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     49485886                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     49485886                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012507                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.012507                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012507                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.012507                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012507                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.012507                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1781371                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.187328                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10705763                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1781883                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             6.008118                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1781373                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.187448                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10705809                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1781885                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             6.008137                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187328                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187448                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -629,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          446
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51822042                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51822042                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6068881                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6068881                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4360082                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4360082                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       127592                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       127592                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       132846                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       132846                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10428963                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10428963                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10428963                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10428963                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1560069                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1560069                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       236541                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       236541                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12626                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        12626                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         6924                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         6924                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1796610                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1796610                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1796610                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1796610                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7628950                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7628950                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4596623                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4596623                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses         51822236                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51822236                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6068914                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6068914                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4360098                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4360098                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       127591                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       127591                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       132845                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       132845                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10429012                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10429012                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10429012                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10429012                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1560067                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1560067                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       236542                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       236542                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12627                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        12627                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         6925                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         6925                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1796609                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1796609                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1796609                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1796609                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7628981                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7628981                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4596640                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4596640                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       140218                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       140218                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       139770                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       139770                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12225573                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12225573                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12225573                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12225573                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.204493                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.204493                       # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     12225621                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12225621                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12225621                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12225621                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.204492                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.204492                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051460                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.051460                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.090046                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090046                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049539                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.049539                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.146955                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146955                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.146955                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146955                       # miss rate for overall accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.090053                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090053                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049546                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.049546                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.146954                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.146954                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.146954                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.146954                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -687,14 +303,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       633103                       # number of writebacks
-system.cpu0.dcache.writebacks::total           633103                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       632997                       # number of writebacks
+system.cpu0.dcache.writebacks::total           632997                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements           618298                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.240646                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           48867509                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           618810                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            78.970135                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9786048500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.240646                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998517                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998517                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         50105399                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        50105399                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     48867509                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       48867509                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     48867509                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        48867509                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     48867509                       # number of overall hits
+system.cpu0.icache.overall_hits::total       48867509                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       618945                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       618945                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       618945                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        618945                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       618945                       # number of overall misses
+system.cpu0.icache.overall_misses::total       618945                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     49486454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     49486454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     49486454                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     49486454                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     49486454                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     49486454                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012507                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.012507                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012507                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.012507                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012507                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.012507                       # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2831559                       # DTB read hits
+system.cpu1.dtb.read_hits                     2831558                       # DTB read hits
 system.cpu1.dtb.read_misses                      3191                       # DTB read misses
 system.cpu1.dtb.read_acv                           58                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  198160                       # DTB read accesses
@@ -702,7 +367,7 @@ system.cpu1.dtb.write_hits                    2101673                       # DT
 system.cpu1.dtb.write_misses                      412                       # DTB write misses
 system.cpu1.dtb.write_acv                          55                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  90619                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4933232                       # DTB hits
+system.cpu1.dtb.data_hits                     4933231                       # DTB hits
 system.cpu1.dtb.data_misses                      3603                       # DTB misses
 system.cpu1.dtb.data_acv                          113                       # DTB access violations
 system.cpu1.dtb.data_accesses                  288779                       # DTB accesses
@@ -722,31 +387,31 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3738296587                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3738297607                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   15522159                       # Number of instructions committed
-system.cpu1.committedOps                     15522159                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             14295544                       # Number of integer alu accesses
+system.cpu1.committedInsts                   15522157                       # Number of instructions committed
+system.cpu1.committedOps                     15522157                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             14295542                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                198941                       # Number of float alu accesses
 system.cpu1.num_func_calls                     493140                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1540068                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    14295544                       # number of integer instructions
+system.cpu1.num_conditional_control_insts      1540067                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    14295542                       # number of integer instructions
 system.cpu1.num_fp_insts                       198941                       # number of float instructions
-system.cpu1.num_int_register_reads           19514289                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          10457600                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           19514287                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          10457599                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads              101734                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes             104129                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4961786                       # number of memory refs
-system.cpu1.num_load_insts                    2849090                       # Number of load instructions
+system.cpu1.num_mem_refs                      4961785                       # number of memory refs
+system.cpu1.num_load_insts                    2849089                       # Number of load instructions
 system.cpu1.num_store_insts                   2112696                       # Number of store instructions
-system.cpu1.num_idle_cycles              3722773649.474793                       # Number of idle cycles
-system.cpu1.num_busy_cycles              15522937.525207                       # Number of busy cycles
+system.cpu1.num_idle_cycles              3722774671.474094                       # Number of idle cycles
+system.cpu1.num_busy_cycles              15522935.525906                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.004152                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.995848                       # Percentage of idle cycles
-system.cpu1.Branches                          2214163                       # Number of branches fetched
+system.cpu1.Branches                          2214162                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass               856043      5.51%      5.51% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  9156766     58.98%     64.49% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  9156765     58.98%     64.49% # Class of executed instruction
 system.cpu1.op_class::IntMult                   25065      0.16%     64.65% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     64.65% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                  12426      0.08%     64.73% # Class of executed instruction
@@ -775,11 +440,11 @@ system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.74% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.74% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.74% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2937016     18.92%     83.66% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2937015     18.92%     83.66% # Class of executed instruction
 system.cpu1.op_class::MemWrite                2113897     13.62%     97.27% # Class of executed instruction
 system.cpu1.op_class::IprAccess                423253      2.73%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  15525875                       # Class of executed instruction
+system.cpu1.op_class::total                  15525873                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2704                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                     92290                       # number of hwrei instructions executed
@@ -793,11 +458,11 @@ system.cpu1.kern.ipl_good::22                    1906      2.99%     51.49% # nu
 system.cpu1.kern.ipl_good::30                     616      0.97%     52.46% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   30319     47.54%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                63776                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1856123490500     99.30%     99.30% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1856124001500     99.30%     99.30% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::22               81958000      0.00%     99.31% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               70736500      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            12870743500      0.69%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1869146928500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            12870742500      0.69%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1869147438500                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.967808                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -849,115 +514,67 @@ system.cpu1.kern.mode_switch_good::kernel     0.434066                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.177356                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.358625                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        5986368000      0.32%      0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        5986367000      0.32%      0.32% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user           456602000      0.02%      0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1862102404500     99.66%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1862102855500     99.66%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2507                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           380647                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          453.133719                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           15144687                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           381159                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.733253                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1859777157500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133719                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.885027                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         15907063                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        15907063                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     15144687                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       15144687                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     15144687                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        15144687                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     15144687                       # number of overall hits
-system.cpu1.icache.overall_hits::total       15144687                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       381188                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       381188                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       381188                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        381188                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       381188                       # number of overall misses
-system.cpu1.icache.overall_misses::total       381188                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     15525875                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     15525875                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     15525875                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     15525875                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     15525875                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     15525875                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024552                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024552                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024552                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024552                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024552                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024552                       # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           201757                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          497.601960                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4718401                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           202065                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.350907                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.replacements           201756                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          497.613037                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4718402                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           202064                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.351027                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle      15869420000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.601960                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971879                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.971879                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.613037                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971900                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.971900                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.601562                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         20020608                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        20020608                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2632688                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2632688                       # number of ReadReq hits
+system.cpu1.dcache.tags.tag_accesses         20020602                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        20020602                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2632689                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2632689                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      1954642                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total       1954642                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        61098                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        61098                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        61099                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        61099                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        64210                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        64210                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      4587330                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         4587330                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      4587330                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        4587330                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       140885                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       140885                       # number of ReadReq misses
+system.cpu1.dcache.demand_hits::cpu1.data      4587331                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         4587331                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      4587331                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        4587331                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       140883                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       140883                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data        78318                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total        78318                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11000                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11000                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10999                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        10999                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data         7305                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total         7305                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       219203                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        219203                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       219203                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       219203                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2773573                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2773573                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.demand_misses::cpu1.data       219201                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        219201                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       219201                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       219201                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2773572                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2773572                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data      2032960                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      2032960                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72098                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        72098                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        71515                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        71515                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4806533                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4806533                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4806533                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4806533                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data      4806532                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4806532                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4806532                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4806532                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050795                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.050795                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.038524                       # miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::total     0.038524                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152570                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152570                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152556                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152556                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.102146                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.102146                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.045605                       # miss rate for demand accesses
@@ -972,8 +589,392 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       144528                       # number of writebacks
-system.cpu1.dcache.writebacks::total           144528                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       144531                       # number of writebacks
+system.cpu1.dcache.writebacks::total           144531                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements           380671                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          453.133725                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           15144661                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           381183                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.730683                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1859779767500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133725                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885027                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.885027                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         15907085                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        15907085                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     15144661                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       15144661                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     15144661                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        15144661                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     15144661                       # number of overall hits
+system.cpu1.icache.overall_hits::total       15144661                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       381212                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       381212                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       381212                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        381212                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       381212                       # number of overall misses
+system.cpu1.icache.overall_misses::total       381212                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     15525873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     15525873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     15525873                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     15525873                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     15525873                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     15525873                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024553                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024553                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024553                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024553                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024553                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024553                       # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                 7628                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7628                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              14588                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14686                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18036                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        44074                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  127536                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        58744                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9018                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        86162                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2747818                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements                41699                       # number of replacements
+system.iocache.tags.tagsinuse                0.434101                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1685787163517                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.434101                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.027131                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.027131                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
+system.iocache.tags.data_accesses              375579                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          179                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               179                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          179                       # number of overall misses
+system.iocache.overall_misses::total              179                       # number of overall misses
+system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          179                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             179                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          179                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            179                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                   999763                       # number of replacements
+system.l2c.tags.tagsinuse                65320.982513                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2387511                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1064813                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.242188                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   56016.894287                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4834.499535                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4176.023150                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      178.992489                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      114.573052                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.854750                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073769                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.063721                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002731                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.001748                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996719                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65050                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          768                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         3271                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6125                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5943                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        48943                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.992584                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 31464842                       # Number of tag accesses
+system.l2c.tags.data_accesses                31464842                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             606959                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             626686                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             379549                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             129013                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1742207                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          777528                       # number of Writeback hits
+system.l2c.Writeback_hits::total               777528                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             116                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             577                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 693                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            13                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           111433                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            56603                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               168036                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              606959                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              738119                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              379549                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              185616                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1910243                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             606959                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             738119                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             379549                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             185616                       # number of overall hits
+system.l2c.overall_hits::total                1910243                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11965                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           926610                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1663                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1033                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               941271                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          3006                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          2174                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              5180                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         1175                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         1110                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            2285                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113916                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          11069                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124985                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             11965                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data           1040526                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1663                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             12102                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1066256                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11965                       # number of overall misses
+system.l2c.overall_misses::cpu0.data          1040526                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1663                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            12102                       # number of overall misses
+system.l2c.overall_misses::total              1066256                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.inst         618924                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1553296                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         381212                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         130046                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2683478                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       777528                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           777528                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3122                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2751                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5873                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1212                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1123                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2335                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       225349                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        67672                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           293021                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          618924                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1778645                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          381212                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          197718                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2976499                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         618924                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1778645                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         381212                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         197718                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2976499                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.019332                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.596544                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.004362                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.007943                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.350765                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962844                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.790258                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.882002                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.969472                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.988424                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.978587                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.505509                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.163568                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.426539                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.019332                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.585010                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004362                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.061208                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.358225                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.019332                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.585010                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004362                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.061208                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.358225                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               80845                       # number of writebacks
+system.l2c.writebacks::total                    80845                       # number of writebacks
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              948899                       # Transaction distribution
+system.membus.trans_dist::ReadResp             948899                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14588                       # Transaction distribution
+system.membus.trans_dist::Writeback            122365                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            19616                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          14180                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            8160                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            126515                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           124290                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        44074                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      2256148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      2300222                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124982                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124982                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2425204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        86162                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73369984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     73456146                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5328064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5328064                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                78784210                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           1265678                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 1265678    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             1265678                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2732182                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2732182                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14588                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           777528                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           19614                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         14230                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          33844                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295246                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295246                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1237890                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4301779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       762424                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       627155                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6929248                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     39612480                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155758587                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     24397568                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23357975                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              243126610                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           41895                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3873082                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.010775                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.103240                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                3831351     98.92%     98.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  41731      1.08%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            3873082                       # Request fanout histogram
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index d02473de7..608395ba3 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,146 +1,51 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829331993500                       # Number of ticks simulated
-final_tick                               1829331993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1829332273500                       # Number of ticks simulated
+final_tick                               1829332273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2920462                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2920460                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            88984410684                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 366200                       # Number of bytes of host memory used
-host_seconds                                    20.56                       # Real time elapsed on the host
-sim_insts                                    60038469                       # Number of instructions simulated
-sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1690642                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1690641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            51512796649                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313048                       # Number of bytes of host memory used
+host_seconds                                    35.51                       # Real time elapsed on the host
+sim_insts                                    60038341                       # Number of instructions simulated
+sim_ops                                      60038341                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66856000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          66839040                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             67714944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             67697984                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       857984                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4753856                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7413184                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7411008                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7411008                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst              13406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1044360                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1058046                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           74279                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115831                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1057781                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115797                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115797                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               469015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36546674                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36537397                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37016214                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37006937                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          469015                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2598684                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1453715                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4052399                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2598684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4051209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4051209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4051209                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              469015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36546674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1454240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41068613                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              948404                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948404                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
-system.membus.trans_dist::Writeback             74279                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116985                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116985                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2190605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      2224649                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83452                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83452                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2308101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72467840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72513966                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2670464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2670464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                75184430                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1174168                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1174168    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1174168                       # Request fanout histogram
-system.iocache.tags.replacements                41686                       # number of replacements
-system.iocache.tags.tagsinuse                1.225569                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1685780587017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.225569                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
-system.iocache.tags.data_accesses              375534                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
-system.iocache.overall_misses::total              174                       # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.physmem.bw_total::cpu.data            36537397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41058146                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710423                       # DTB read hits
+system.cpu.dtb.read_hits                      9710422                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
@@ -148,14 +53,14 @@ system.cpu.dtb.write_hits                     6352496                       # DT
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062919                       # DTB hits
+system.cpu.dtb.data_hits                     16062918                       # DTB hits
 system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974637                       # ITB hits
+system.cpu.itb.fetch_hits                     4974648                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -168,31 +73,31 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3658670345                       # number of cpu cycles simulated
+system.cpu.numCycles                       3658670905                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60038469                       # Number of instructions committed
-system.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913692                       # Number of integer alu accesses
+system.cpu.committedInsts                    60038341                       # Number of instructions committed
+system.cpu.committedOps                      60038341                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              55913563                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
 system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110791                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913692                       # number of integer instructions
+system.cpu.num_conditional_control_insts      7110761                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     55913563                       # number of integer instructions
 system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76954245                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740352                       # number of times the integer registers were written
+system.cpu.num_int_register_reads            76954014                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41740254                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115703                       # number of memory refs
-system.cpu.num_load_insts                     9747509                       # Number of load instructions
+system.cpu.num_mem_refs                      16115702                       # number of memory refs
+system.cpu.num_load_insts                     9747508                       # Number of load instructions
 system.cpu.num_store_insts                    6368194                       # Number of store instructions
-system.cpu.num_idle_cycles               3598621002.088897                       # Number of idle cycles
-system.cpu.num_busy_cycles               60049342.911103                       # Number of busy cycles
+system.cpu.num_idle_cycles               3598621691.055137                       # Number of idle cycles
+system.cpu.num_busy_cycles               60049213.944863                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
-system.cpu.Branches                           9064428                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3199100      5.33%      5.33% # Class of executed instruction
-system.cpu.op_class::IntAlu                  39448406     65.69%     71.02% # Class of executed instruction
+system.cpu.Branches                           9064400                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3199098      5.33%      5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu                  39448273     65.69%     71.02% # Class of executed instruction
 system.cpu.op_class::IntMult                    60677      0.10%     71.12% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
 system.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
@@ -221,34 +126,34 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::MemRead                  9975077     16.61%     87.80% # Class of executed instruction
+system.cpu.op_class::MemRead                  9975076     16.61%     87.80% # Class of executed instruction
 system.cpu.op_class::MemWrite                 6374115     10.61%     98.42% # Class of executed instruction
-system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                 951217      1.58%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   60050307                       # Class of executed instruction
+system.cpu.op_class::total                   60050179                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105623     57.86%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182562                       # number of times we switched to this ipl
 system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811929127500     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1811929473000     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829331786000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             17302245000      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1829332066000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -287,7 +192,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
@@ -296,96 +201,99 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192179                       # number of callpals executed
+system.cpu.kern.callpal::total                 192180                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1737                      
+system.cpu.kern.mode_good::kernel                1909                      
+system.cpu.kern.mode_good::user                  1738                      
 system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801033399500     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        26833319500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801033671500     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               9838                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.icache.tags.replacements            919603                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            59130077                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            920115                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             64.263790                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2042728                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14038398                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2043240                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.870655                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          66369797                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         66369797                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7807758                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807758                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848202                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848202                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13655960                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655960                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13655960                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655960                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721724                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721724                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304370                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304370                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17163                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17163                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2026094                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026094                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026094                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026094                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15682054                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682054                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682054                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682054                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180673                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180673                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085685                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085685                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129198                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129198                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129198                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129198                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       833501                       # number of writebacks
+system.cpu.dcache.writebacks::total            833501                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements            919605                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.215260                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            59129947                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            920117                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             64.263509                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.215260                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -393,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           63
 system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60970537                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60970537                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     59130077                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59130077                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59130077                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59130077                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59130077                       # number of overall hits
-system.cpu.icache.overall_hits::total        59130077                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920230                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920230                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920230                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920230                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920230                       # number of overall misses
-system.cpu.icache.overall_misses::total        920230                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050307                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050307                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050307                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          60970411                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60970411                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     59129947                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59129947                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59129947                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59129947                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59129947                       # number of overall hits
+system.cpu.icache.overall_hits::total        59129947                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       920232                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920232                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       920232                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920232                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       920232                       # number of overall misses
+system.cpu.icache.overall_misses::total        920232                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     60050179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60050179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60050179                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60050179                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60050179                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60050179                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
@@ -428,15 +336,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           992289                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65424.374569                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2433258                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1057452                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.301058                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           992295                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65424.374284                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2433284                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1057458                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.301069                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4866.106258                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.930478                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4866.099732                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.922318                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.859228                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074251                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
@@ -445,66 +353,66 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          781                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3260                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4024                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3048                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54050                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54043                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         31737481                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        31737481                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       906806                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       811234                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1718040                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       833484                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       833484                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         31737815                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        31737815                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       906808                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       811247                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1718055                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       833501                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       833501                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187241                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187241                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906806                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998475                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905281                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906806                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998475                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905281                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187243                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187243                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       906808                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998490                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1905298                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       906808                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998490                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1905298                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst        13406                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total       941046                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117105                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117105                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       117111                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       117111                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst        13406                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044745                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1058151                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1044751                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1058157                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        13406                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044745                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1058151                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       920212                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1738874                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2659086                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       833484                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       833484                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1044751                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1058157                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       920214                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1738887                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2659101                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       833501                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       833501                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920212                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2963432                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920212                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2963432                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304354                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304354                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       920214                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2043241                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2963455                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       920214                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2043241                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2963455                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014568                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533472                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.353898                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533468                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.353896                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384776                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384776                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384785                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384785                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014568                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511323                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.511320                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.357069                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014568                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511323                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.511320                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.357069                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -514,106 +422,199 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74279                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74279                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74285                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74285                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2042707                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14038420                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2043219                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              6.870737                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          66369780                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         66369780                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7807771                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807771                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848210                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848210                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655981                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655981                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655981                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655981                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721712                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721712                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682055                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682055                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682055                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682055                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833484                       # number of writebacks
-system.cpu.dcache.writebacks::total            833484                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2666288                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2666288                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2666303                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2666303                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       833484                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       833501                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304346                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304346                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1840460                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4954000                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6794460                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     58894720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184155182                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          243049902                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       304354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304354                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1840464                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4954059                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6794523                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     58894848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184157614                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          243052462                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       41883                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3838676                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      3838716                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        1.010870                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103691                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103690                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3796950     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3796990     98.91%     98.91% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2              41726      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3838676                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3838716                       # Request fanout histogram
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               9838                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements                41686                       # number of replacements
+system.iocache.tags.tagsinuse                1.225572                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1685780587017                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.225572                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
+system.iocache.tags.data_accesses              375534                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
+system.iocache.overall_misses::total              174                       # number of overall misses
+system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              948404                       # Transaction distribution
+system.membus.trans_dist::ReadResp             948404                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
+system.membus.trans_dist::Writeback            115797                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116991                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116991                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2190623                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      2224667                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124964                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124964                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2349631                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72468608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72514734                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5327232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5327232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                77841966                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           1215692                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 1215692    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             1215692                       # Request fanout histogram
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index dd52d45d1..9ca2241e2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,121 +1,118 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.961827                       # Number of seconds simulated
-sim_ticks                                1961826628500                       # Number of ticks simulated
-final_tick                               1961826628500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.962845                       # Number of seconds simulated
+sim_ticks                                1962844580000                       # Number of ticks simulated
+final_tick                               1962844580000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1248737                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1248737                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            40231703865                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 312404                       # Number of bytes of host memory used
-host_seconds                                    48.76                       # Real time elapsed on the host
-sim_insts                                    60892387                       # Number of instructions simulated
-sim_ops                                      60892387                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1184099                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1184098                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38148129943                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318172                       # Number of bytes of host memory used
+host_seconds                                    51.45                       # Real time elapsed on the host
+sim_insts                                    60925667                       # Number of instructions simulated
+sim_ops                                      60925667                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           833152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24900864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           823168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24882816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            41728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           386368                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            31872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           336832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26103680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       833152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        31872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5078656                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7737984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13018                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            389076                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26135040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       823168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        41728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          864896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7758336                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7758336                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             12862                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            388794                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               652                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              6037                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               498                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              5263                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                407870                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           79354                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120906                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              424682                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12692693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                408360                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          121224                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121224                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              419375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12676916                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               21259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              196841                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               16246                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              171693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13305804                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         424682                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          16246                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             440928                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2588738                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1355537                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3944275                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2588738                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             424682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12692693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1356026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              16246                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             171693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17250079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        407870                       # Number of read requests accepted
-system.physmem.writeReqs                       120906                       # Number of write requests accepted
-system.physmem.readBursts                      407870                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     120906                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26092032                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7736064                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26103680                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7737984                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      182                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           6995                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25277                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25718                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25598                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25075                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25186                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25258                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25824                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25548                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25573                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25196                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25177                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25610                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25669                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25717                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              26016                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25246                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7929                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7788                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7545                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7026                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7134                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7133                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7657                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7252                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7395                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7119                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7401                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7832                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8315                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8567                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7699                       # Per bank write bursts
+system.physmem.bw_read::total                13314880                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         419375                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          21259                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440634                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3952598                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3952598                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3952598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             419375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12676916                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              21259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             196841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              489                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17267478                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        408360                       # Number of read requests accepted
+system.physmem.writeReqs                       162776                       # Number of write requests accepted
+system.physmem.readBursts                      408360                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     162776                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26127936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10271680                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26135040                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10417664                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2254                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           7048                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25705                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25985                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25732                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25537                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               24847                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24747                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25534                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25495                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25150                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25518                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25462                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25292                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25577                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25454                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              26241                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25973                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10613                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10753                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9796                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9387                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8893                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9110                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9958                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9669                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9689                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9901                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9876                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10215                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10815                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10652                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10531                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10637                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1961819616500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1962839541500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  407870                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  408360                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 120906                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        59                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 162776                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    408168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        68                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -161,632 +158,180 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6804                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        66427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      509.252202                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     306.095148                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     413.238328                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15972     24.04%     24.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12116     18.24%     42.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5140      7.74%     50.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2994      4.51%     54.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3304      4.97%     59.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1746      2.63%     62.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1491      2.24%     64.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1317      1.98%     66.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22347     33.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          66427                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5433                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        75.036996                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2192.886898                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           5428     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     9464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    10119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10932                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11871                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10784                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        69162                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      526.295017                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     318.923666                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.254848                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16035     23.18%     23.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        12178     17.61%     40.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5186      7.50%     48.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3086      4.46%     52.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3308      4.78%     57.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1800      2.60%     60.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1507      2.18%     62.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1316      1.90%     64.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24746     35.78%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          69162                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5880                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        69.428401                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2107.963348                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           5875     99.91%     99.91% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::122880-126975            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5433                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5433                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.248482                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.059784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       19.984616                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4773     87.85%     87.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              17      0.31%     88.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              17      0.31%     88.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             237      4.36%     92.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              33      0.61%     93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               9      0.17%     93.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               6      0.11%     93.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.17%     93.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              24      0.44%     94.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.02%     94.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              10      0.18%     94.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.11%     94.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.06%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.07%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              32      0.59%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              11      0.20%     95.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.06%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               9      0.17%     95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             180      3.31%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.07%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.06%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.07%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.07%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             5      0.09%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             7      0.13%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            13      0.24%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5433                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2198653000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9842803000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2038440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5392.98                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5880                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5880                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.295068                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.802481                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       33.368634                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4837     82.26%     82.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             186      3.16%     85.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             281      4.78%     90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              57      0.97%     91.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              98      1.67%     92.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              42      0.71%     93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              21      0.36%     93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              12      0.20%     94.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              21      0.36%     94.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               6      0.10%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             10      0.17%     94.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             8      0.14%     94.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            13      0.22%     95.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             5      0.09%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            22      0.37%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            44      0.75%     96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            23      0.39%     96.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             6      0.10%     96.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            80      1.36%     98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            40      0.68%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            14      0.24%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            24      0.41%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            14      0.24%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.03%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             5      0.09%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             4      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5880                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2202002500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9856671250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2041245000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5393.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24142.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24143.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.23                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.94                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.31                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     365377                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96760                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.62                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3710114.71                       # Average gap between requests
-system.physmem.pageHitRate                      87.43                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1840052567250                       # Time in different power states
-system.physmem.memoryStateTime::REF       65509600000                       # Time in different power states
+system.physmem.avgWrQLen                        26.11                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     365785                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    133797                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.60                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  83.35                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3436728.80                       # Average gap between requests
+system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1840639787000                       # Time in different power states
+system.physmem.memoryStateTime::REF       65543660000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       56261656500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       56660375500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 248270400                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 253917720                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 135465000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 138546375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1587175200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1592791200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               385326720                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               397949760                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          128136777600                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          128136777600                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           65365947855                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           65768853780                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1119755735250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1119402309000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1315614698025                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1315691145435                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.607978                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.646945                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              292757                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292757                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14067                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14067                       # Transaction distribution
-system.membus.trans_dist::Writeback             79354                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            16159                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11272                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            6995                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            123294                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           122471                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42532                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       930313                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       972845                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83293                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83293                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1056138                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        81954                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31181376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31263330                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33923618                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            21418                       # Total snoops (count)
-system.membus.snoop_fanout::samples            557197                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  557197    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              557197                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40794500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1536995500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3833296255                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43122000                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.physmem.actEnergy::0                 257115600                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 265749120                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 140291250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 145002000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1587939600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1596402600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               506599920                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               533407680                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          128203398960                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          128203398960                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           65563204050                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           65997539775                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1120194702750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1119813706500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1316453252130                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1316555206635                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             670.686708                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.738650                       # Core power per rank (mW)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   342092                       # number of replacements
-system.l2c.tags.tagsinuse                65220.775537                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2444844                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407280                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.002858                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               8652068750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55275.158075                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4808.073812                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4934.415131                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      159.916198                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       43.212322                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu0.data       0.075293                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        65188                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          763                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5265                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7161                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51884                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994690                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 25951455                       # Number of tag accesses
-system.l2c.tags.data_accesses                25951455                       # Number of data accesses
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-system.l2c.Writeback_hits::writebacks          792816                       # number of Writeback hits
-system.l2c.Writeback_hits::total               792816                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data             541                       # number of UpgradeReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.763135                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.866605                       # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::total  2349.802853                       # average UpgradeReq miss latency
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-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
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-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
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-system.l2c.overall_mshr_miss_latency::total  22081159750                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373183500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17608500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1390792000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2147807000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674603500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2822410500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3520990500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692212000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4213202500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.289029                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002278                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.138536                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941964                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.763135                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.866605                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.955914                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.975322                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.965628                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.474650                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.106488                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.415771                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.327842                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.034750                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173343                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018499                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.327842                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001596                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.034750                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173343                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 54073.440389                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 54073.440389                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41694                       # number of replacements
-system.iocache.tags.tagsinuse                0.569739                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1755504878000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.569739                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035609                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035609                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
-system.iocache.tags.data_accesses              375534                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
-system.iocache.overall_misses::total              174                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21248383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21248383                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21248383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21248383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21248383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21248383                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122117.143678                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122117.143678                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122117.143678                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          174                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          174                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12199383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12199383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2501404806                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2501404806                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12199383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12199383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12199383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12199383                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70111.396552                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70111.396552                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7562596                       # DTB read hits
+system.cpu0.dtb.read_hits                     7534386                       # DTB read hits
 system.cpu0.dtb.read_misses                      7765                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5147185                       # DTB write hits
+system.cpu0.dtb.write_hits                    5126601                       # DTB write hits
 system.cpu0.dtb.write_misses                      910                       # DTB write misses
 system.cpu0.dtb.write_acv                         133                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12709781                       # DTB hits
+system.cpu0.dtb.data_hits                    12660987                       # DTB hits
 system.cpu0.dtb.data_misses                      8675                       # DTB misses
 system.cpu0.dtb.data_acv                          343                       # DTB access violations
 system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3660706                       # ITB hits
+system.cpu0.itb.fetch_hits                    3654300                       # ITB hits
 system.cpu0.itb.fetch_misses                     3984                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3664690                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3658284                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -799,91 +344,91 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3923653257                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3925689160                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   48127777                       # Number of instructions committed
-system.cpu0.committedOps                     48127777                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44643925                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                213512                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1209739                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5647172                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44643925                       # number of integer instructions
-system.cpu0.num_fp_insts                       213512                       # number of float instructions
-system.cpu0.num_int_register_reads           61387452                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          33242964                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              104337                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             106136                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12750882                       # number of memory refs
-system.cpu0.num_load_insts                    7590433                       # Number of load instructions
-system.cpu0.num_store_insts                   5160449                       # Number of store instructions
-system.cpu0.num_idle_cycles              3699495012.998114                       # Number of idle cycles
-system.cpu0.num_busy_cycles              224158244.001886                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057130                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942870                       # Percentage of idle cycles
-system.cpu0.Branches                          7246936                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2741568      5.70%      5.70% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 31634980     65.72%     71.41% # Class of executed instruction
-system.cpu0.op_class::IntMult                   52525      0.11%     71.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.52% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  26830      0.06%     71.58% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1883      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.58% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7767201     16.14%     87.72% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5166567     10.73%     98.45% # Class of executed instruction
-system.cpu0.op_class::IprAccess                745241      1.55%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   47974635                       # Number of instructions committed
+system.cpu0.committedOps                     47974635                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             44501266                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                212945                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1202793                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5632199                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    44501266                       # number of integer instructions
+system.cpu0.num_fp_insts                       212945                       # number of float instructions
+system.cpu0.num_int_register_reads           61193579                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          33138119                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              104073                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             105864                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     12702031                       # number of memory refs
+system.cpu0.num_load_insts                    7562183                       # Number of load instructions
+system.cpu0.num_store_insts                   5139848                       # Number of store instructions
+system.cpu0.num_idle_cycles              3702096779.998114                       # Number of idle cycles
+system.cpu0.num_busy_cycles              223592380.001886                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.056956                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.943044                       # Percentage of idle cycles
+system.cpu0.Branches                          7223323                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2734296      5.70%      5.70% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 31541688     65.73%     71.43% # Class of executed instruction
+system.cpu0.op_class::IntMult                   52334      0.11%     71.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.54% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  26783      0.06%     71.60% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1883      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.60% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7738218     16.13%     87.73% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5145965     10.72%     98.45% # Class of executed instruction
+system.cpu0.op_class::IprAccess                742486      1.55%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  48136795                       # Class of executed instruction
+system.cpu0.op_class::total                  47983653                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6805                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    166328                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   57239     40.25%     40.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.34% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1975      1.39%     41.73% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    424      0.30%     42.03% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  82449     57.97%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              142218                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56706     49.09%     49.09% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce                    6794                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    165589                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   56925     40.22%     40.22% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.31% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1976      1.40%     41.70% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    424      0.30%     42.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  82092     58.00%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              141548                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    56392     49.08%     49.08% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1975      1.71%     50.91% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     424      0.37%     51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   56283     48.72%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               115519                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1902225794500     96.96%     96.96% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               94977500      0.00%     96.97% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              767421000      0.04%     97.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              314336500      0.02%     97.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            58423341500      2.98%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1961825871000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.990688                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1976      1.72%     50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     424      0.37%     51.29% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   55969     48.71%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               114892                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1903342573000     96.97%     96.97% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               94358500      0.00%     96.97% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              767882500      0.04%     97.01% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              314406500      0.02%     97.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            58324587500      2.97%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1962843808000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.990637                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682640                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.812267                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.681784                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811682                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
@@ -915,355 +460,125 @@ system.cpu0.kern.syscall::144                       2      0.85%     99.15% # nu
 system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  506      0.34%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  512      0.34%      0.34% # number of callpals executed
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3105      2.06%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.43% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.44% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               135265     89.81%     92.25% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6701      4.45%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.70% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4423      2.94%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3097      2.07%      2.41% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               134593     89.81%     92.26% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6634      4.43%     96.68% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.68% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     96.69% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.69% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.69% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4424      2.95%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 394      0.26%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                150611                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7020                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1371                       # number of protection mode switches
+system.cpu0.kern.callpal::total                149871                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7013                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1370                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1370                      
-system.cpu0.kern.mode_good::user                 1371                      
+system.cpu0.kern.mode_good::kernel               1369                      
+system.cpu0.kern.mode_good::user                 1370                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.195157                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.195209                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.326660                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1958053140500     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3772726000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.326733                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1959059969000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3783834500      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3106                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2102030                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2102015                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14067                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14067                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           792816                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        41560                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           16382                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11336                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          27718                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           297616                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297616                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1407417                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3134555                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       624007                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       452565                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5618544                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     45036672                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    120042720                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19968192                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16553666                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              201601250                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           98838                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3254541                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.012823                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.112512                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3212807     98.72%     98.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41734      1.28%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3254541                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4795402363                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           715500                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3169257997                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5536514081                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1404115991                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         776560164                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55619                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55619                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13922                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42532                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125984                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55688                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        81954                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2743570                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13277000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           374410189                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28465000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42017000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           703089                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.385515                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47433077                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           703601                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.414738                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.385515                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992940                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992940                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48840515                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48840515                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47433077                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47433077                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47433077                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47433077                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47433077                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47433077                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       703719                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       703719                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       703719                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        703719                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       703719                       # number of overall misses
-system.cpu0.icache.overall_misses::total       703719                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10017635497                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10017635497                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10017635497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10017635497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10017635497                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10017635497                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     48136796                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     48136796                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     48136796                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     48136796                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     48136796                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     48136796                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014619                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014619                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014619                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014619                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014619                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014619                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14235.277855                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14235.277855                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       703719                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       703719                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       703719                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       703719                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       703719                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       703719                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8605152503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8605152503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8605152503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8605152503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8605152503                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8605152503                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014619                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014619                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014619                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014619                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1191194                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.224955                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11513307                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1191706                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.661197                       # Average number of references to valid blocks.
+system.cpu0.kern.swap_context                    3098                       # number of times the context was actually changed
+system.cpu0.dcache.tags.replacements          1190018                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.199068                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11465472                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1190530                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.630561                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        108210250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.224955                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986767                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986767                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.199068                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986717                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986717                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         52084143                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        52084143                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6477469                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6477469                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4731394                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4731394                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       141563                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       141563                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149256                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149256                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11208863                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11208863                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11208863                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11208863                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       942620                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       942620                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       258040                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       258040                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13696                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13696                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5452                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5452                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1200660                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1200660                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1200660                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1200660                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27232981250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  27232981250                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10355566942                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10355566942                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    149859500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    149859500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     42011389                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     42011389                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  37588548192                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  37588548192                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  37588548192                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  37588548192                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7420089                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7420089                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4989434                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4989434                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       155259                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       155259                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       154708                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       154708                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12409523                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12409523                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12409523                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12409523                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127036                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127036                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051717                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051717                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088214                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088214                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035241                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035241                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096753                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.096753                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096753                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.096753                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7705.683969                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7705.683969                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546                       # average overall miss latency
+system.cpu0.dcache.tags.tag_accesses         51888213                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51888213                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6450398                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6450398                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4712072                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4712072                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140773                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       140773                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       148356                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       148356                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11162470                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11162470                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11162470                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11162470                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       942246                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       942246                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       257610                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       257610                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13707                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13707                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5575                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         5575                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1199856                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1199856                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1199856                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1199856                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27226306250                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  27226306250                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10348541688                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  10348541688                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    149709000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    149709000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     42660894                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     42660894                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  37574847938                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  37574847938                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  37574847938                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  37574847938                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7392644                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7392644                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4969682                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4969682                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154480                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       154480                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153931                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       153931                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12362326                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12362326                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12362326                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12362326                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127457                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.127457                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051836                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051836                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088730                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088730                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.036218                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.036218                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097057                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.097057                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097057                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097057                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7652.178296                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7652.178296                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1272,62 +587,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       686359                       # number of writebacks
-system.cpu0.dcache.writebacks::total           686359                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       942620                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       942620                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       258040                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       258040                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13696                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13696                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5452                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5452                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1200660                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1200660                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1200660                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1200660                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25222171750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25222171750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9786377058                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9786377058                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    122453500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    122453500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31105611                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31105611                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35008548808                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  35008548808                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35008548808                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  35008548808                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465625500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465625500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2277904000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2277904000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3743529500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3743529500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127036                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127036                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051717                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051717                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088214                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088214                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035241                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035241                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096753                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096753                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096753                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096753                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8940.822138                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8940.822138                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5705.357850                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5705.357850                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       685854                       # number of writebacks
+system.cpu0.dcache.writebacks::total           685854                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       942246                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       942246                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       257610                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       257610                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13707                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13707                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5575                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         5575                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1199856                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1199856                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1199856                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1199856                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25216322750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25216322750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9780175312                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9780175312                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    122281000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    122281000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31509106                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31509106                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34996498062                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  34996498062                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34996498062                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  34996498062                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1461499500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1461499500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2267126500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2267126500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3728626000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3728626000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127457                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127457                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051836                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051836                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088730                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088730                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.036218                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.036218                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097057                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.097057                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097057                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.097057                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8921.062231                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8921.062231                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5651.857578                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5651.857578                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1335,26 +650,112 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements           699671                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.391653                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           47283349                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           700182                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.530084                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      40276505250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.391653                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992952                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992952                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          436                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         48683959                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48683959                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     47283349                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       47283349                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     47283349                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        47283349                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     47283349                       # number of overall hits
+system.cpu0.icache.overall_hits::total       47283349                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       700305                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       700305                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       700305                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        700305                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       700305                       # number of overall misses
+system.cpu0.icache.overall_misses::total       700305                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9967517496                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   9967517496                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   9967517496                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   9967517496                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   9967517496                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   9967517496                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     47983654                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     47983654                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     47983654                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     47983654                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     47983654                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     47983654                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014595                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014595                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014595                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014595                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014595                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014595                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14233.109140                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14233.109140                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       700305                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       700305                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       700305                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       700305                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       700305                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       700305                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8561918504                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   8561918504                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8561918504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   8561918504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8561918504                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   8561918504                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014595                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014595                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014595                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014595                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014595                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014595                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2348280                       # DTB read hits
+system.cpu1.dtb.read_hits                     2382379                       # DTB read hits
 system.cpu1.dtb.read_misses                      2620                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1676993                       # DTB write hits
+system.cpu1.dtb.write_hits                    1702197                       # DTB write hits
 system.cpu1.dtb.write_misses                      235                       # DTB write misses
 system.cpu1.dtb.write_acv                          24                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4025273                       # DTB hits
+system.cpu1.dtb.data_hits                     4084576                       # DTB hits
 system.cpu1.dtb.data_misses                      2855                       # DTB misses
 system.cpu1.dtb.data_acv                           24                       # DTB access violations
 system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1801078                       # ITB hits
+system.cpu1.itb.fetch_hits                    1808740                       # ITB hits
 system.cpu1.itb.fetch_misses                     1064                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1802142                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1809804                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1367,87 +768,87 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3921880878                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3923834014                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   12764610                       # Number of instructions committed
-system.cpu1.committedOps                     12764610                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             11762987                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                170364                       # Number of float alu accesses
-system.cpu1.num_func_calls                     404048                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1265459                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    11762987                       # number of integer instructions
-system.cpu1.num_fp_insts                       170364                       # number of float instructions
-system.cpu1.num_int_register_reads           16177090                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8656212                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               88600                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              90534                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4047820                       # number of memory refs
-system.cpu1.num_load_insts                    2361802                       # Number of load instructions
-system.cpu1.num_store_insts                   1686018                       # Number of store instructions
-system.cpu1.num_idle_cycles              3873240792.459649                       # Number of idle cycles
-system.cpu1.num_busy_cycles              48640085.540351                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012402                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987598                       # Percentage of idle cycles
-system.cpu1.Branches                          1821460                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               690637      5.41%      5.41% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  7566798     59.27%     64.68% # Class of executed instruction
-system.cpu1.op_class::IntMult                   21839      0.17%     64.85% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.85% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  13058      0.10%     64.95% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.95% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.95% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.95% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1759      0.01%     64.96% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.96% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2432293     19.05%     84.01% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1686990     13.21%     97.23% # Class of executed instruction
-system.cpu1.op_class::IprAccess                354115      2.77%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   12951032                       # Number of instructions committed
+system.cpu1.committedOps                     12951032                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             11936898                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                171199                       # Number of float alu accesses
+system.cpu1.num_func_calls                     411532                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1284277                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    11936898                       # number of integer instructions
+system.cpu1.num_fp_insts                       171199                       # number of float instructions
+system.cpu1.num_int_register_reads           16412569                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           8783541                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               88996                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              90942                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      4107226                       # number of memory refs
+system.cpu1.num_load_insts                    2395961                       # Number of load instructions
+system.cpu1.num_store_insts                   1711265                       # Number of store instructions
+system.cpu1.num_idle_cycles              3874307298.691787                       # Number of idle cycles
+system.cpu1.num_busy_cycles              49526715.308213                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.012622                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.987378                       # Percentage of idle cycles
+system.cpu1.Branches                          1849703                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               699491      5.40%      5.40% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  7680347     59.29%     64.69% # Class of executed instruction
+system.cpu1.op_class::IntMult                   22457      0.17%     64.86% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.86% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  13113      0.10%     64.96% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.96% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.96% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.96% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1759      0.01%     64.98% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.98% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2467292     19.05%     84.02% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1712246     13.22%     97.24% # Class of executed instruction
+system.cpu1.op_class::IprAccess                357206      2.76%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  12767489                       # Class of executed instruction
+system.cpu1.op_class::total                  12953911                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     77083                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   26133     38.19%     38.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      2.88%     41.07% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    506      0.74%     41.81% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  39822     58.19%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               68430                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    25289     48.13%     48.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      3.75%     51.87% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     506      0.96%     52.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   24783     47.16%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                52547                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1909614154000     97.38%     97.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              700846000      0.04%     97.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              353816000      0.02%     97.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            50271593000      2.56%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1960940409000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.967704                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2765                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     77892                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   26462     38.26%     38.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1970      2.85%     41.11% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    512      0.74%     41.85% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  40213     58.15%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               69157                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    25618     48.15%     48.15% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1970      3.70%     51.85% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     512      0.96%     52.81% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   25106     47.19%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                53206                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1910435586500     97.38%     97.38% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              701157000      0.04%     97.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              358940000      0.02%     97.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            50421293500      2.57%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1961916977000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.968105                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.622344                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.767894                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.624325                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.769351                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
@@ -1463,207 +864,123 @@ system.cpu1.kern.syscall::74                        9      9.78%     96.74% # nu
 system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  424      0.60%      0.60% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  424      0.59%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.60% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1955      2.77%      3.37% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.38% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.39% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                62269     88.12%     91.51% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2146      3.04%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     94.55% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.55% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3685      5.21%     99.77% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1967      2.75%      3.35% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      3.35% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.36% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                62982     88.13%     91.49% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2216      3.10%     94.59% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.60% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.00%     94.60% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.60% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3692      5.17%     99.77% # number of callpals executed
 system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
 system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 70663                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1918                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 71465                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1923                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                367                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2888                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                797                      
+system.cpu1.kern.mode_switch::idle               2902                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                803                      
 system.cpu1.kern.mode_good::user                  367                      
-system.cpu1.kern.mode_good::idle                  430                      
-system.cpu1.kern.mode_switch_good::kernel     0.415537                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle                  436                      
+system.cpu1.kern.mode_switch_good::kernel     0.417577                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.148892                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.308138                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       17565031500      0.90%      0.90% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1483893000      0.08%      0.97% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1941003590000     99.03%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1956                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           311453                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          446.345950                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12455485                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           311964                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.926033                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1960014862500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.345950                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871769                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.871769                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          440                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13079493                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13079493                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12455485                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12455485                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12455485                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12455485                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12455485                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12455485                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       312004                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       312004                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       312004                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        312004                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       312004                       # number of overall misses
-system.cpu1.icache.overall_misses::total       312004                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4105450991                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4105450991                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4105450991                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4105450991                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4105450991                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4105450991                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     12767489                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     12767489                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     12767489                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     12767489                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     12767489                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     12767489                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024437                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024437                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024437                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024437                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024437                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024437                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13158.328070                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13158.328070                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       312004                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       312004                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       312004                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       312004                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       312004                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       312004                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3481247009                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3481247009                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3481247009                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3481247009                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3481247009                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3481247009                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024437                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024437                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024437                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024437                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           155174                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          486.308424                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3855056                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           155503                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.790879                       # Average number of references to valid blocks.
+system.cpu1.kern.mode_switch_good::idle      0.150241                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.309322                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       17997631500      0.92%      0.92% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1494992000      0.08%      0.99% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1941547962000     99.01%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1968                       # number of times the context was actually changed
+system.cpu1.dcache.tags.replacements           157269                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          486.065602                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3912422                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           157596                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.825643                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     1048852145500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.308424                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949821                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.949821                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.065602                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949347                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.949347                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          327                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16322131                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16322131                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2189503                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2189503                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1567525                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1567525                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        46972                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        46972                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        49481                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        49481                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3757028                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3757028                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3757028                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3757028                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       113756                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       113756                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        55958                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        55958                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8862                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8862                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5884                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5884                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       169714                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        169714                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       169714                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       169714                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1372027750                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1372027750                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1020320505                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1020320505                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80442000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     80442000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     43305909                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     43305909                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2392348255                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2392348255                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2392348255                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2392348255                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2303259                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2303259                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1623483                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1623483                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        55834                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        55834                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        55365                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        55365                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3926742                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3926742                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3926742                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3926742                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049389                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049389                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034468                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.034468                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158720                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158720                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106277                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106277                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043220                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.043220                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043220                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043220                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9077.183480                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9077.183480                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7359.943746                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7359.943746                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833                       # average overall miss latency
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          295                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.638672                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         16561703                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        16561703                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2221454                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2221454                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1590675                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1590675                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        47775                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        47775                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50240                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        50240                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3812129                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3812129                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3812129                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3812129                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       115097                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       115097                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        57126                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        57126                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8902                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8902                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5962                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         5962                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       172223                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        172223                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       172223                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       172223                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1389994499                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1389994499                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1079772299                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1079772299                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80592000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     80592000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     43791416                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     43791416                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   2469766798                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   2469766798                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   2469766798                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   2469766798                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2336551                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2336551                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1647801                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1647801                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        56677                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        56677                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56202                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        56202                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3984352                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3984352                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3984352                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3984352                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049259                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.049259                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034668                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.034668                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.157065                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.157065                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106082                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106082                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043225                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.043225                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043225                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.043225                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9053.246461                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9053.246461                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7345.088225                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7345.088225                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1672,62 +989,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       106457                       # number of writebacks
-system.cpu1.dcache.writebacks::total           106457                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113756                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       113756                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        55958                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        55958                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8862                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8862                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5884                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5884                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       169714                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       169714                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       169714                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       169714                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1144439250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1144439250                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    906162495                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    906162495                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62718000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     62718000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31536091                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31536091                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2050601745                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2050601745                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2050601745                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2050601745                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18765500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18765500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    713325000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    713325000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    732090500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    732090500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049389                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049389                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034468                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034468                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.158720                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.158720                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106277                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106277                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043220                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043220                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043220                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043220                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7077.183480                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7077.183480                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5359.634772                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5359.634772                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       107940                       # number of writebacks
+system.cpu1.dcache.writebacks::total           107940                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       115097                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       115097                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        57126                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        57126                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8902                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8902                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5962                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         5962                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       172223                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       172223                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       172223                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       172223                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1159712501                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1159712501                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    962952701                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    962952701                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62788000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     62788000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31865584                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31865584                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2122665202                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2122665202                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2122665202                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2122665202                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     22446500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     22446500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    726758000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    726758000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    749204500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    749204500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049259                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049259                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034668                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034668                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.157065                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.157065                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106082                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106082                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043225                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.043225                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043225                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.043225                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7053.246461                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7053.246461                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5344.780946                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5344.780946                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1735,5 +1052,696 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements           318302                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          446.541764                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           12635057                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           318814                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.631437                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1956986830500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.541764                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.872152                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.872152                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          439                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         13272765                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        13272765                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     12635057                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       12635057                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     12635057                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        12635057                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     12635057                       # number of overall hits
+system.cpu1.icache.overall_hits::total       12635057                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       318854                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       318854                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       318854                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        318854                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       318854                       # number of overall misses
+system.cpu1.icache.overall_misses::total       318854                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4204550742                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4204550742                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4204550742                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4204550742                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4204550742                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4204550742                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     12953911                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     12953911                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     12953911                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     12953911                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     12953911                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     12953911                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024614                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024614                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024614                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024614                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024614                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024614                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13186.445025                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13186.445025                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       318854                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       318854                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       318854                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       318854                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       318854                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       318854                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3566590258                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3566590258                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3566590258                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3566590258                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3566590258                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3566590258                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024614                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024614                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024614                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024614                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024614                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024614                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177                       # average overall mshr miss latency
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               55631                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              14079                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13950                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2474                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42552                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  126008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        55800                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9876                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        82034                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2743666                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13305000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy             2453000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer29.occupancy           406206788                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            28473000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy            42016500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements                41696                       # number of replacements
+system.iocache.tags.tagsinuse                0.577792                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41712                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1755504938000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.577792                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.036112                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.036112                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
+system.iocache.tags.data_accesses              375552                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          176                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               176                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          176                       # number of overall misses
+system.iocache.overall_misses::total              176                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21474383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21474383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13634244905                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13634244905                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21474383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21474383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21474383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21474383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          176                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             176                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          176                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            176                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122013.539773                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122013.539773                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122013.539773                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        206283                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23550                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.759363                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          176                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          176                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          176                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12321383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12321383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11473540905                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11473540905                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12321383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12321383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12321383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12321383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70007.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70007.857955                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                   342754                       # number of replacements
+system.l2c.tags.tagsinuse                65220.433043                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2449371                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407927                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.004435                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               8652068750                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   55272.994922                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4808.176589                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4932.064474                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      162.933205                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       44.263854                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.843399                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073367                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075257                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000675                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995185                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65173                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          764                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5225                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7223                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51853                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994461                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 25998619                       # Number of tag accesses
+system.l2c.tags.data_accesses                25998619                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             687419                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             668122                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             318193                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             105248                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1778982                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          793794                       # number of Writeback hits
+system.l2c.Writeback_hits::total               793794                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             182                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             544                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 726                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            43                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            23                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                66                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           129870                       # number of ReadExReq hits
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+system.l2c.ReadExReq_hits::total               172379                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              687419                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              797992                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data              147757                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                1951361                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            12865                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           271552                       # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::cpu1.data          1779                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4738                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          894                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total            1810                       # number of SCUpgradeReq misses
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+system.l2c.overall_misses::total               409122                       # number of overall misses
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+system.l2c.ReadReq_miss_latency::cpu1.data     20711500                       # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu0.data      1125461                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     10172561                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     11298022                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       873463                       # number of SCUpgradeReq miss cycles
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+system.l2c.SCUpgradeReq_miss_latency::total      1129452                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8144387768                       # number of ReadExReq miss cycles
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+system.l2c.overall_miss_latency::cpu0.inst    945742500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total    27252773747                       # number of overall miss cycles
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+system.l2c.ReadReq_accesses::total            2064352                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       793794                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           793794                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3141                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2323                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5464                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          937                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          939                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1876                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu0.inst      0.018371                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.288985                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.002070                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.002776                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.138237                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942057                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.765820                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.867130                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.954109                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu1.data 70687.713311                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5718.134345                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2384.555087                       # average UpgradeReq miss latency
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+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   279.463974                       # average SCUpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 69262.619974                       # average ReadExReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 66263.268129                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 73733.774539                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 66263.268129                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 73733.774539                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 66612.828807                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               79704                       # number of writebacks
+system.l2c.writebacks::total                    79704                       # number of writebacks
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+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1779                       # number of UpgradeReq MSHR misses
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+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6662563232                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    354144021                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7016707253                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    781932250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  20934306482                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     39270500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    371209021                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  22126718253                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    781932250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  20934306482                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     39270500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    371209021                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  22126718253                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1369396000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     20977500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1390373500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2137906500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    687013500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2824920000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3507302500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    707991000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4215293500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018367                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.288985                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.002045                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002776                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.138232                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942057                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.765820                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.867130                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.954109                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.975506                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.964819                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.475999                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.119678                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.417896                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018367                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.328016                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002045                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.039472                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173317                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018367                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.328016                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002045                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.039472                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173317                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 54084.877339                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 54084.877339                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              292732                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292732                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14079                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14079                       # Transaction distribution
+system.membus.trans_dist::Writeback            121224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            16421                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          11471                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            7051                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            124094                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           123249                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42552                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       932442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       974994                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1099809                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82034                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31235136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31317170                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36634738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            22113                       # Total snoops (count)
+system.membus.snoop_fanout::samples            600297                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  600297    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              600297                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40801500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy          1914880000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3840416202                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy           43136500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq            2106484                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2106469                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14079                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14079                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           793794                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           16644                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11537                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28181                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           298092                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          298092                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1400589                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3132441                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       637707                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       458977                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5629714                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44818176                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119962112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20406592                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16779186                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              201966066                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           99450                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3260906                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.012796                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.112395                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                3219178     98.72%     98.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  41728      1.28%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            3260906                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4802513358                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy        3153866996                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        5532423832                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy        1434969242                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         787756714                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 04dd39221..166d29f48 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,110 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.919439                       # Number of seconds simulated
-sim_ticks                                1919439025000                       # Number of ticks simulated
-final_tick                               1919439025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.920428                       # Number of seconds simulated
+sim_ticks                                1920427877000                       # Number of ticks simulated
+final_tick                               1920427877000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1406989                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1406988                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            48137648137                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309300                       # Number of bytes of host memory used
-host_seconds                                    39.87                       # Real time elapsed on the host
-sim_insts                                    56102180                       # Number of instructions simulated
-sim_ops                                      56102180                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 694902                       # Simulator instruction rate (inst/s)
+host_op_rate                                   694902                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23785763794                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317148                       # Number of bytes of host memory used
+host_seconds                                    80.74                       # Real time elapsed on the host
+sim_insts                                    56105324                       # Number of instructions simulated
+sim_ops                                      56105324                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            850816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24875904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24858304                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25727680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4747520                       # Number of bytes written to this memory
-system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7406848                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13294                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388686                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25710016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7404096                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7404096                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388411                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                401995                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           74180                       # Number of write requests responded to by this memory
-system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115732                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               443263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12959987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                401719                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115689                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115689                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               443001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12944149                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               500                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13403750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          443263                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             443263                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2473389                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::tsunami.ide          1385471                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3858861                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2473389                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              443263                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12959987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1385972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17262610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        401995                       # Number of read requests accepted
-system.physmem.writeReqs                       115732                       # Number of write requests accepted
-system.physmem.readBursts                      401995                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115732                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25715968                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11712                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7405120                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25727680                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7406848                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      183                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            132                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25161                       # Per bank write bursts
+system.physmem.bw_read::total                13387650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          443001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             443001                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3855441                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3855441                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3855441                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              443001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12944149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              500                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17243091                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        401719                       # Number of read requests accepted
+system.physmem.writeReqs                       157241                       # Number of write requests accepted
+system.physmem.readBursts                      401719                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     157241                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25703424                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9932992                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25710016                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10063424                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2011                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25160                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               25539                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25618                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25536                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24982                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24977                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24228                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24506                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25158                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24823                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25363                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24839                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24418                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25388                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25481                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7550                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7529                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7880                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7553                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7115                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6983                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6321                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6315                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7293                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6555                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7205                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6861                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7980                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7780                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25602                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25522                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               24974                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24970                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24210                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24489                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25140                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               24800                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25361                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24836                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24395                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25368                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25772                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25478                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10040                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9905                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10447                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9982                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9551                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9392                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8805                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8555                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9942                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8777                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9524                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9288                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9847                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10608                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10278                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10262                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1919427104000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1920415956000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  401995                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  401719                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115732                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    401798                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 157241                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    401602                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
@@ -151,327 +148,180 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5623                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63991                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      517.589786                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     312.394273                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     414.375602                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15074     23.56%     23.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11584     18.10%     41.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4587      7.17%     48.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3091      4.83%     53.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3045      4.76%     58.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1807      2.82%     61.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1323      2.07%     63.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1474      2.30%     65.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22006     34.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63991                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5109                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        78.644353                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2952.702952                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5106     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     9080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5950                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5885                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34                      334                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::40                      251                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      205                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        66429                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      536.458715                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     326.725513                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.454187                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15065     22.68%     22.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11458     17.25%     39.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4677      7.04%     46.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3146      4.74%     51.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3014      4.54%     56.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1853      2.79%     59.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1319      1.99%     61.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1472      2.22%     63.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24425     36.77%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          66429                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5535                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        72.556098                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2836.858046                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5532     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5109                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5109                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.647289                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.199358                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.195525                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4460     87.30%     87.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              21      0.41%     87.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              12      0.23%     87.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             224      4.38%     92.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              41      0.80%     93.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.39%     93.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               7      0.14%     93.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.12%     93.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              14      0.27%     94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.08%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.06%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.02%     94.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               9      0.18%     94.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.10%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.08%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              25      0.49%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               9      0.18%     95.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              15      0.29%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             168      3.29%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.04%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.04%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.02%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.04%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.16%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             5      0.10%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             5      0.10%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             9      0.18%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            13      0.25%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             5      0.10%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             3      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5109                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2129492750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9663467750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2009060000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5299.72                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5535                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        28.040289                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       21.079799                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       34.913440                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4499     81.28%     81.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             176      3.18%     84.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             297      5.37%     89.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              50      0.90%     90.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              97      1.75%     92.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              48      0.87%     93.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              11      0.20%     93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               7      0.13%     93.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              21      0.38%     94.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               7      0.13%     94.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             14      0.25%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             6      0.11%     94.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            14      0.25%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             3      0.05%     94.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            11      0.20%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            48      0.87%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            16      0.29%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            19      0.34%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            91      1.64%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            36      0.65%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             6      0.11%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            14      0.25%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            14      0.25%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.09%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             9      0.16%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.05%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             5      0.09%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5535                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2119831750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9650131750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2008080000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5278.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24049.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.40                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24028.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.39                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.24                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     359991                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93535                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.59                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.82                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3707411.64                       # Average gap between requests
-system.physmem.pageHitRate                      87.63                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1800186005000                       # Time in different power states
-system.physmem.memoryStateTime::REF       64094160000                       # Time in different power states
+system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     359880                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    130510                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.08                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3435694.78                       # Average gap between requests
+system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1801057353000                       # Time in different power states
+system.physmem.memoryStateTime::REF       64127180000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       55155300000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       55239785750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 236499480                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 247272480                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 129042375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 134920500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1564266600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1569867000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               370954080                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               378814320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          125368176960                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          125368176960                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           63948324510                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           64460493450                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1095566249250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1095116978250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1287183513255                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1287276522960                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.605262                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.653719                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              292357                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292357                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
-system.membus.trans_dist::Writeback             74180                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116726                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116726                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878404                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911562                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 994854                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30474240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30518796                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33179084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              158                       # Total snoops (count)
-system.membus.snoop_fanout::samples            518029                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  518029    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              518029                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30371000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1451093000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3752017868                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43114250                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.344808                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1753524972000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.344808                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.084051                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.084051                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375557                       # Number of tag accesses
-system.iocache.tags.data_accesses              375557                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::tsunami.ide            4                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total            4                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     24523133                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     24523133                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     24523133                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     24523133                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     24523133                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     24523133                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41556                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        41556                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide     0.000096                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000096                       # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 141752.213873                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 141752.213873                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 141752.213873                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      41552                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     15526633                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     15526633                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2512178304                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2512178304                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     15526633                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     15526633                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     15526633                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     15526633                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 89749.323699                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 89749.323699                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.physmem.actEnergy::0                 245964600                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 256238640                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 134206875                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 139812750                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               1563634800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               1568970000                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               496866960                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               508848480                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          125432764080                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          125432764080                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           64118860245                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           64485707400                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1096009968750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1095688173000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1288002266310                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1288080514350                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             670.686297                       # Core power per rank (mW)
+system.physmem.averagePower::1             670.727042                       # Core power per rank (mW)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9052455                       # DTB read hits
-system.cpu.dtb.read_misses                      10357                       # DTB read misses
+system.cpu.dtb.read_hits                      9053154                       # DTB read hits
+system.cpu.dtb.read_misses                      10325                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728916                       # DTB read accesses
-system.cpu.dtb.write_hits                     6349129                       # DTB write hits
-system.cpu.dtb.write_misses                      1143                       # DTB write misses
+system.cpu.dtb.read_accesses                   728854                       # DTB read accesses
+system.cpu.dtb.write_hits                     6349573                       # DTB write hits
+system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291932                       # DTB write accesses
-system.cpu.dtb.data_hits                     15401584                       # DTB hits
-system.cpu.dtb.data_misses                      11500                       # DTB misses
+system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
+system.cpu.dtb.data_hits                     15402727                       # DTB hits
+system.cpu.dtb.data_misses                      11467                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020848                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974880                       # ITB hits
+system.cpu.dtb.data_accesses                  1020785                       # DTB accesses
+system.cpu.itb.fetch_hits                     4974627                       # ITB hits
 system.cpu.itb.fetch_misses                      5010                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979890                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979637                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -484,34 +334,34 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3838878050                       # number of cpu cycles simulated
+system.cpu.numCycles                       3840855754                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56102180                       # Number of instructions committed
-system.cpu.committedOps                      56102180                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              51977296                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324326                       # Number of float alu accesses
-system.cpu.num_func_calls                     1481232                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6461044                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     51977296                       # number of integer instructions
-system.cpu.num_fp_insts                        324326                       # number of float instructions
-system.cpu.num_int_register_reads            71206831                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38459262                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163576                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166452                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15454224                       # number of memory refs
-system.cpu.num_load_insts                     9089337                       # Number of load instructions
-system.cpu.num_store_insts                    6364887                       # Number of store instructions
-system.cpu.num_idle_cycles               3587231475.998131                       # Number of idle cycles
-system.cpu.num_busy_cycles               251646574.001869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065552                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934448                       # Percentage of idle cycles
-system.cpu.Branches                           8412776                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3197684      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36172751     64.46%     70.16% # Class of executed instruction
-system.cpu.op_class::IntMult                    60997      0.11%     70.27% # Class of executed instruction
+system.cpu.committedInsts                    56105324                       # Number of instructions committed
+system.cpu.committedOps                      56105324                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              51980283                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324527                       # Number of float alu accesses
+system.cpu.num_func_calls                     1481352                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6461346                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     51980283                       # number of integer instructions
+system.cpu.num_fp_insts                        324527                       # number of float instructions
+system.cpu.num_int_register_reads            71211532                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38461399                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163675                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166554                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15455353                       # number of memory refs
+system.cpu.num_load_insts                     9090013                       # Number of load instructions
+system.cpu.num_store_insts                    6365340                       # Number of store instructions
+system.cpu.num_idle_cycles               3589191785.998131                       # Number of idle cycles
+system.cpu.num_busy_cycles               251663968.001869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065523                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934477                       # Percentage of idle cycles
+system.cpu.Branches                           8413247                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3197750      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36174854     64.46%     70.16% # Class of executed instruction
+system.cpu.op_class::IntMult                    61015      0.11%     70.27% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     70.27% # Class of executed instruction
-system.cpu.op_class::FloatAdd                   38083      0.07%     70.34% # Class of executed instruction
+system.cpu.op_class::FloatAdd                   38089      0.07%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
@@ -537,34 +387,34 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
-system.cpu.op_class::MemRead                  9316413     16.60%     86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6370959     11.35%     98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess                 953524      1.70%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                  9317103     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6371414     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::IprAccess                 953297      1.70%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56114047                       # Class of executed instruction
+system.cpu.op_class::total                   56117158                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6380                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     212017                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6382                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     212003                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74898     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106211     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183168                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106222     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183183                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73531     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149118                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857251860000     96.76%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91366000      0.00%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               736784000      0.04%     96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             61358281000      3.20%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1919438291000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73531     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149125                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1858233349500     96.76%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                91228000      0.00%     96.77% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               737074000      0.04%     96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             61365491500      3.20%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1920427143000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692282                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814105                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692239                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814077                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -600,184 +450,229 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4175      2.16%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4178      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175949     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175962     91.21%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192892                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1742                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1911                      
-system.cpu.kern.mode_good::user                  1742                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.323734                       # fraction of useful protection mode switches
+system.cpu.kern.callpal::total                 192910                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5901                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1743                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2100                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1914                      
+system.cpu.kern.mode_good::user                  1743                      
+system.cpu.kern.mode_good::idle                   171                      
+system.cpu.kern.mode_switch_good::kernel     0.324352                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080707                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392443                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46142250000      2.40%      2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5192719000      0.27%      2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1868103320000     97.33%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4176                       # number of times the context was actually changed
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51197                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            4                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2706164                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           374412187                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42016750                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            927651                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.304035                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55185726                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            928162                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.456998                       # Average number of references to valid blocks.
+system.cpu.kern.mode_switch_good::idle       0.081429                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392857                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46106755000      2.40%      2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5190620000      0.27%      2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1869129766000     97.33%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
+system.cpu.dcache.tags.replacements           1390139                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.978885                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14031130                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1390651                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.089613                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.978885                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63077780                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63077780                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7803062                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7803062                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5845783                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5845783                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183030                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183030                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199238                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199238                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13648845                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13648845                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13648845                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13648845                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069228                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069228                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304213                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304213                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17228                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17228                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1373441                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373441                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373441                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373441                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29002641750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29002641750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10915376130                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10915376130                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228802500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    228802500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39918017880                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39918017880                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39918017880                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39918017880                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8872290                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8872290                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6149996                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6149996                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200258                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200258                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199238                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199238                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15022286                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15022286                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15022286                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15022286                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120513                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120513                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049466                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049466                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086029                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086029                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091427                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091427                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091427                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091427                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29064.239294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29064.239294                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       834534                       # number of writebacks
+system.cpu.dcache.writebacks::total            834534                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069228                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069228                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304213                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304213                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17228                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17228                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373441                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373441                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373441                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373441                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26738553250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26738553250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10254282870                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10254282870                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194333500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194333500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36992836120                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36992836120                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36992836120                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36992836120                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424273000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424273000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2009400000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2009400000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3433673000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3433673000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120513                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120513                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049466                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049466                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086029                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086029                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091427                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091427                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25007.344785                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements            927958                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.305941                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55188530                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            928469                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.440358                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       39853785250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.304035                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992781                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.305941                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992785                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57042370                       # Number of tag accesses
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-system.cpu.icache.ReadReq_hits::cpu.inst     55185726                       # number of ReadReq hits
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-system.cpu.icache.overall_hits::total        55185726                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       928322                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928322                       # number of ReadReq misses
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-system.cpu.icache.overall_misses::cpu.inst       928322                       # number of overall misses
-system.cpu.icache.overall_misses::total        928322                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12909129000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12909129000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12909129000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12909129000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12909129000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12909129000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56114048                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total     56114048                       # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016543                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13905.874255                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13905.874255                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13905.874255                       # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13904.065563                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13904.065563                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -786,135 +681,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928322                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total       928322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11047351000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11047351000                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total  11047351000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total  11047351000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016543                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.521907                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           336238                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65296.035696                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2445623                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401399                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.092748                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             6.094045                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       6784872750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4767.074149                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4872                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3263                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55775                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994278                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::writebacks       834448                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
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 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876                       # average ReadReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 66514.450927                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -923,66 +818,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74180                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74180                       # number of writebacks
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 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116845                       # number of ReadExReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334183000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334183000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1893390000                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014321                       # mshr miss rate for ReadReq accesses
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 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384120                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279608                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173405                       # mshr miss rate for demand accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279608                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173405                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -990,184 +885,291 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1390025                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.978881                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14030084                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1390537                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.089688                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.978881                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63073026                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63073026                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7802461                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7802461                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5845351                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5845351                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183030                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183030                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199225                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199225                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13647812                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13647812                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13647812                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13647812                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069134                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069134                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304206                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304206                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17215                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17215                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373340                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373340                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373340                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373340                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  28994287250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  28994287250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10922192632                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10922192632                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228270750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    228270750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39916479882                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39916479882                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39916479882                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39916479882                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8871595                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8871595                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6149557                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6149557                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200245                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200245                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199225                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15021152                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15021152                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15021152                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15021152                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120512                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120512                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049468                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049468                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085970                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085970                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091427                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091427                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091427                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091427                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29065.256879                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29065.256879                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       834448                       # number of writebacks
-system.cpu.dcache.writebacks::total            834448                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069134                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069134                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304206                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304206                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17215                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17215                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373340                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373340                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373340                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373340                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26730348750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26730348750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10261067368                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10261067368                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193828250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193828250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36991416118                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36991416118                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36991416118                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36991416118                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424273000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424273000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2009178000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2009178000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3433451000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3433451000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120512                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120512                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049468                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049468                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091427                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091427                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091427                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2021774                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2021757                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       834448                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41564                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2022188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2022171                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       834534                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304189                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304189                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1856624                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3648872                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5505496                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59411328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142453644                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          201864972                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       41913                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3195062                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.013063                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.113544                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       304196                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304196                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1857238                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649188                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5506426                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59430976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142466452                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          201897428                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       41901                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3195557                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.013057                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.113520                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3153325     98.69%     98.69% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41737      1.31%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3153832     98.69%     98.69% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              41725      1.31%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3195062                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2424224500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3195557                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2424565000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1395050000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1395517500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2186768132                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2186897880                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               9650                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5156                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33160                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116610                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2706172                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              4767000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer29.occupancy           406189794                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy            42010500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements                41685                       # number of replacements
+system.iocache.tags.tagsinuse                1.352352                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1753525032000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.352352                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.084522                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.084522                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
+system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13634918911                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13634918911                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        206323                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23561                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.756971                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11474214911                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11474214911                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              292355                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292355                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
+system.membus.trans_dist::Writeback            115689                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116723                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116723                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1036082                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30456384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30500948                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                35818004                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              431                       # Total snoops (count)
+system.membus.snoop_fanout::samples            559521                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  559521    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total              559521                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30373000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy          1824623000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3751921620                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy           43109500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 1efe64b0a..a51b2d079 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,76 +1,73 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.802883                       # Number of seconds simulated
-sim_ticks                                2802882634000                       # Number of ticks simulated
-final_tick                               2802882634000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.802895                       # Number of seconds simulated
+sim_ticks                                2802895103500                       # Number of ticks simulated
+final_tick                               2802895103500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1078207                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1313778                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20582448891                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 574132                       # Number of bytes of host memory used
-host_seconds                                   136.18                       # Real time elapsed on the host
-sim_insts                                   146828350                       # Number of instructions simulated
-sim_ops                                     178908035                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 967895                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1179365                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18476638236                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 571628                       # Number of bytes of host memory used
+host_seconds                                   151.70                       # Real time elapsed on the host
+sim_insts                                   146829031                       # Number of instructions simulated
+sim_ops                                     178908942                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1117092                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          9456444                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1117540                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          9440380                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           151956                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1081888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           152404                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1082016                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11809044                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1117092                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       151956                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1269048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6071744                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11794004                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1117540                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       152404                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1269944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8387200                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8407824                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8404944                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             25908                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            148282                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             25915                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            148031                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2529                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16928                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2536                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16930                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                193673                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           94871                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                193438                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131050                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135531                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               135486                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           160                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              398551                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3373828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              398709                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3368082                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               54214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              385991                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               54374                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              386035                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4213178                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         398551                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          54214                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             452765                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2166250                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4207794                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         398709                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          54374                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             453083                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2992335                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6316                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          827126                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2999706                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2166250                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2998665                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2992335                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             398551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3380144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             398709                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3374398                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              54214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             386005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          827468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7212884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              54374                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             386049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7206459                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -119,9 +116,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    20339775                       # DTB read hits
-system.cpu0.dtb.read_misses                      6871                       # DTB read misses
-system.cpu0.dtb.write_hits                   16390998                       # DTB write hits
+system.cpu0.dtb.read_hits                    20339962                       # DTB read hits
+system.cpu0.dtb.read_misses                      6874                       # DTB read misses
+system.cpu0.dtb.write_hits                   16391171                       # DTB write hits
 system.cpu0.dtb.write_misses                     1093                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
@@ -132,12 +129,12 @@ system.cpu0.dtb.align_faults                        0                       # Nu
 system.cpu0.dtb.prefetch_faults                  1788                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                20346646                       # DTB read accesses
-system.cpu0.dtb.write_accesses               16392091                       # DTB write accesses
+system.cpu0.dtb.read_accesses                20346836                       # DTB read accesses
+system.cpu0.dtb.write_accesses               16392264                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         36730773                       # DTB hits
-system.cpu0.dtb.misses                           7964                       # DTB misses
-system.cpu0.dtb.accesses                     36738737                       # DTB accesses
+system.cpu0.dtb.hits                         36731133                       # DTB hits
+system.cpu0.dtb.misses                           7967                       # DTB misses
+system.cpu0.dtb.accesses                     36739100                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -159,7 +156,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    97439484                       # ITB inst hits
+system.cpu0.itb.inst_hits                    97440315                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -176,38 +173,38 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                97442842                       # ITB inst accesses
-system.cpu0.itb.hits                         97439484                       # DTB hits
+system.cpu0.itb.inst_accesses                97443673                       # ITB inst accesses
+system.cpu0.itb.hits                         97440315                       # DTB hits
 system.cpu0.itb.misses                           3358                       # DTB misses
-system.cpu0.itb.accesses                     97442842                       # DTB accesses
-system.cpu0.numCycles                      5605767234                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     97443673                       # DTB accesses
+system.cpu0.numCycles                      5605792176                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   95427026                       # Number of instructions committed
-system.cpu0.committedOps                    115560441                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            100762684                       # Number of integer alu accesses
+system.cpu0.committedInsts                   95427853                       # Number of instructions committed
+system.cpu0.committedOps                    115561498                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            100763618                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
-system.cpu0.num_func_calls                    8000257                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     13204260                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   100762684                       # number of integer instructions
+system.cpu0.num_func_calls                    8000324                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     13204344                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   100763618                       # number of integer instructions
 system.cpu0.num_fp_insts                         9755                       # number of float instructions
-system.cpu0.num_int_register_reads          182457418                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          69135520                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          182459108                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          69136203                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           349971578                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           44907537                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     37873766                       # number of memory refs
-system.cpu0.num_load_insts                   20597356                       # Number of load instructions
-system.cpu0.num_store_insts                  17276410                       # Number of store instructions
-system.cpu0.num_idle_cycles              5488182675.223932                       # Number of idle cycles
-system.cpu0.num_busy_cycles              117584558.776067                       # Number of busy cycles
+system.cpu0.num_cc_register_reads           349974767                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           44907843                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     37874145                       # number of memory refs
+system.cpu0.num_load_insts                   20597552                       # Number of load instructions
+system.cpu0.num_store_insts                  17276593                       # Number of store instructions
+system.cpu0.num_idle_cycles              5488206556.246817                       # Number of idle cycles
+system.cpu0.num_busy_cycles              117585619.753183                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.020976                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.979024                       # Percentage of idle cycles
-system.cpu0.Branches                         21941641                       # Number of branches fetched
+system.cpu0.Branches                         21941792                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 78887374     67.49%     67.50% # Class of executed instruction
-system.cpu0.op_class::IntMult                  110635      0.09%     67.59% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 78888049     67.49%     67.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                  110639      0.09%     67.59% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     67.59% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     67.59% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     67.59% # Class of executed instruction
@@ -235,20 +232,20 @@ system.cpu0.op_class::SimdFloatMisc              8087      0.01%     67.60% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.60% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.60% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.60% # Class of executed instruction
-system.cpu0.op_class::MemRead                20597356     17.62%     85.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite               17276410     14.78%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                20597552     17.62%     85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite               17276593     14.78%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 116882135                       # Class of executed instruction
+system.cpu0.op_class::total                 116883193                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1965                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           693468                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.853471                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           35932329                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           693980                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            51.777182                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    1968                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           693476                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.853661                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           35932684                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           693988                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.777097                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23661500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853471                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853661                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966511                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.966511                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -256,60 +253,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          277
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         74113668                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        74113668                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     19108613                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       19108613                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15690292                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15690292                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346080                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       346080                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379619                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       379619                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363025                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       363025                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     34798905                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        34798905                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     35144985                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       35144985                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       373094                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       373094                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       295766                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       295766                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100322                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       100322                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6740                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6740                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18448                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        18448                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       668860                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        668860                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       769182                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       769182                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481707                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     19481707                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986058                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     15986058                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446402                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       446402                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386359                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       386359                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381473                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381473                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     35467765                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     35467765                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     35914167                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     35914167                       # number of overall (read+write) accesses
+system.cpu0.dcache.tags.tag_accesses         74114402                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        74114402                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     19108775                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       19108775                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15690454                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15690454                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346093                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       346093                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379629                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       379629                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363052                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       363052                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     34799229                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        34799229                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     35145322                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       35145322                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       373098                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       373098                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       295765                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       295765                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100321                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       100321                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6742                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6742                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18433                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        18433                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       668863                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        668863                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       769184                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       769184                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481873                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     19481873                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986219                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     15986219                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446414                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446414                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386371                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       386371                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381485                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381485                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     35468092                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     35468092                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     35914506                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     35914506                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019151                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.019151                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018501                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.018501                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224735                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224735                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017445                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017445                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048360                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048360                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224726                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224726                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017450                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017450                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048319                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048319                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018858                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.018858                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021417                       # miss rate for overall accesses
@@ -322,16 +319,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       511566                       # number of writebacks
-system.cpu0.dcache.writebacks::total           511566                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       511648                       # number of writebacks
+system.cpu0.dcache.writebacks::total           511648                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1109631                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.809991                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           96331674                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1110143                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            86.774113                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1109742                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.809992                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           96332394                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1110254                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            86.766086                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       6345717000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809991                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809992                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999629                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999629                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -339,32 +336,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0          212
 system.cpu0.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        195993804                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       195993804                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     96331674                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       96331674                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     96331674                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        96331674                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     96331674                       # number of overall hits
-system.cpu0.icache.overall_hits::total       96331674                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1110152                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1110152                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1110152                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1110152                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1110152                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1110152                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     97441826                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     97441826                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     97441826                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     97441826                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     97441826                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     97441826                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011393                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011393                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011393                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011393                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011393                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011393                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        195995577                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       195995577                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     96332394                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       96332394                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     96332394                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        96332394                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     96332394                       # number of overall hits
+system.cpu0.icache.overall_hits::total       96332394                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1110263                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1110263                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1110263                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1110263                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1110263                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1110263                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     97442657                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     97442657                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     97442657                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     97442657                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     97442657                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     97442657                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011394                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011394                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011394                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011394                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011394                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011394                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -383,123 +380,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          252467                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16137.499100                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1809671                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          268655                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.736041                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements          252403                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16129.283805                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1810262                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          268606                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.739470                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      1814550500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  8061.791544                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.201142                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.081297                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4773.858530                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3298.566587                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.492053                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000195                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks  8068.095549                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.185761                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.086115                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4748.591048                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3309.325333                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.492437                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000194                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.291373                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.201329                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.984955                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16181                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          268                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5647                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7609                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2581                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.987610                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        39448657                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       39448657                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7673                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3273                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1065177                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       351940                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1428063                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       511566                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       511566                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           16                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total           16                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94243                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total        94243                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7673                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3273                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1065177                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       446183                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1522306                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7673                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3273                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1065177                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       446183                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1522306                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          211                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          123                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        44975                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data       128216                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       173525                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26236                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26236                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18448                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18448                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175271                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       175271                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          211                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          123                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        44975                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       303487                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       348796                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          211                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          123                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        44975                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       303487                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       348796                       # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7884                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3396                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1110152                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       480156                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      1601588                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       511566                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       511566                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26252                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        26252                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18448                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        18448                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269514                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269514                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7884                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3396                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1110152                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       749670                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1871102                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7884                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3396                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1110152                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       749670                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1871102                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.026763                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.036219                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040512                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.267030                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.108346                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999391                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999391                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.289831                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.201985                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.984453                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16192                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          279                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5587                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7674                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2571                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000671                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.988281                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        39450391                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       39450391                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7605                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3248                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1065251                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.data       352125                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total       1428229                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       511648                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       511648                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           17                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94130                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total        94130                       # number of ReadExReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7605                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3248                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1065251                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       446255                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1522359                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7605                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3248                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1065251                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       446255                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1522359                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          225                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          134                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst        45012                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.data       128036                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total       173407                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26231                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26231                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18433                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18433                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175387                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       175387                       # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          225                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          134                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        45012                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       303423                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       348794                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          225                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          134                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        45012                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       303423                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       348794                       # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7830                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3382                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1110263                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data       480161                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      1601636                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       511648                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       511648                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26248                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        26248                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18433                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        18433                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269517                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       269517                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7830                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3382                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1110263                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       749678                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1871153                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7830                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3382                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1110263                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       749678                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1871153                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.028736                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.039622                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040542                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.266652                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.108269                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999352                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999352                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.650322                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.650322                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.026763                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.036219                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040512                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404827                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.186412                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.026763                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.036219                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040512                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404827                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.186412                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.650746                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.650746                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.028736                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.039622                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040542                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404738                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.186406                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.028736                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.039622                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040542                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404738                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.186406                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -508,45 +505,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       192870                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          192870                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       192841                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          192841                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1651731                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1651731                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq       1651853                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1651853                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        28400                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        28400                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       511566                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        26252                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18448                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        44700                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       269514                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       269514                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2238348                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2220284                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.trans_dist::Writeback       511648                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        26248                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18433                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        44681                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       269517                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       269517                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2238570                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2220344                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28796                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4500256                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     71085816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80909882                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28808                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          4500550                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     71092920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80915642                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         152078946                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     322137                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      2656435                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.082643                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.275341                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         152091834                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     322042                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      2656528                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.082604                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.275283                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           2436900     91.74%     91.74% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            219535      8.26%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2437088     91.74%     91.74% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            219440      8.26%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       2656435                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total       2656528                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -570,9 +567,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12173905                       # DTB read hits
-system.cpu1.dtb.read_misses                      2853                       # DTB read misses
-system.cpu1.dtb.write_hits                    7587201                       # DTB write hits
+system.cpu1.dtb.read_hits                    12173884                       # DTB read hits
+system.cpu1.dtb.read_misses                      2852                       # DTB read misses
+system.cpu1.dtb.write_hits                    7587193                       # DTB write hits
 system.cpu1.dtb.write_misses                      506                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
@@ -583,12 +580,12 @@ system.cpu1.dtb.align_faults                        0                       # Nu
 system.cpu1.dtb.prefetch_faults                   290                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12176758                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7587707                       # DTB write accesses
+system.cpu1.dtb.read_accesses                12176736                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7587699                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         19761106                       # DTB hits
-system.cpu1.dtb.misses                           3359                       # DTB misses
-system.cpu1.dtb.accesses                     19764465                       # DTB accesses
+system.cpu1.dtb.hits                         19761077                       # DTB hits
+system.cpu1.dtb.misses                           3358                       # DTB misses
+system.cpu1.dtb.accesses                     19764435                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -610,7 +607,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    53671578                       # ITB inst hits
+system.cpu1.itb.inst_hits                    53671431                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -627,38 +624,38 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                53673312                       # ITB inst accesses
-system.cpu1.itb.hits                         53671578                       # DTB hits
+system.cpu1.itb.inst_accesses                53673165                       # ITB inst accesses
+system.cpu1.itb.hits                         53671431                       # DTB hits
 system.cpu1.itb.misses                           1734                       # DTB misses
-system.cpu1.itb.accesses                     53673312                       # DTB accesses
-system.cpu1.numCycles                      5605296143                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     53673165                       # DTB accesses
+system.cpu1.numCycles                      5605321082                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   51401324                       # Number of instructions committed
-system.cpu1.committedOps                     63347594                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             56984226                       # Number of integer alu accesses
+system.cpu1.committedInsts                   51401178                       # Number of instructions committed
+system.cpu1.committedOps                     63347444                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             56984089                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
-system.cpu1.num_func_calls                    9170833                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      5967095                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    56984226                       # number of integer instructions
+system.cpu1.num_func_calls                    9170823                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      5967084                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    56984089                       # number of integer instructions
 system.cpu1.num_fp_insts                         1792                       # number of float instructions
-system.cpu1.num_int_register_reads          110674651                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          41298354                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          110674435                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          41298241                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           196268580                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           18894392                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     20026364                       # number of memory refs
-system.cpu1.num_load_insts                   12289528                       # Number of load instructions
-system.cpu1.num_store_insts                   7736836                       # Number of store instructions
-system.cpu1.num_idle_cycles              5539682653.586912                       # Number of idle cycles
-system.cpu1.num_busy_cycles              65613489.413088                       # Number of busy cycles
+system.cpu1.num_cc_register_reads           196268127                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           18894317                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     20026333                       # number of memory refs
+system.cpu1.num_load_insts                   12289505                       # Number of load instructions
+system.cpu1.num_store_insts                   7736828                       # Number of store instructions
+system.cpu1.num_idle_cycles              5539707743.549846                       # Number of idle cycles
+system.cpu1.num_busy_cycles              65613338.450155                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.011706                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.988294                       # Percentage of idle cycles
-system.cpu1.Branches                         15217468                       # Number of branches fetched
+system.cpu1.Branches                         15217445                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 45401296     69.36%     69.36% # Class of executed instruction
-system.cpu1.op_class::IntMult                   28394      0.04%     69.40% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 45401182     69.36%     69.36% # Class of executed instruction
+system.cpu1.op_class::IntMult                   28388      0.04%     69.40% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     69.40% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
@@ -686,84 +683,84 @@ system.cpu1.op_class::SimdFloatMisc              3319      0.01%     69.41% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead                12289528     18.77%     88.18% # Class of executed instruction
-system.cpu1.op_class::MemWrite                7736836     11.82%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                12289505     18.77%     88.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite                7736828     11.82%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  65459439                       # Class of executed instruction
+system.cpu1.op_class::total                  65459288                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements           191947                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.736020                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           19503484                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           192301                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           101.421646                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.replacements           191938                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          472.735401                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           19503461                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           192292                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           101.426274                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     105851601500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.736020                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923313                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.923313                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.735401                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923311                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.923311                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         39751950                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        39751950                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     11858675                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       11858675                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7397476                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7397476                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50100                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        50100                       # number of SoftPFReq hits
+system.cpu1.dcache.tags.tag_accesses         39751883                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39751883                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     11858662                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       11858662                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7397475                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7397475                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50099                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50099                       # number of SoftPFReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91447                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        91447                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72420                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        72420                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19256151                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19256151                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19306251                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19306251                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       136639                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       136639                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        92478                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        92478                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30718                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30718                       # number of SoftPFReq misses
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72435                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        72435                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19256137                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19256137                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19306236                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19306236                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       136630                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       136630                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        92471                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        92471                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30719                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30719                       # number of SoftPFReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5318                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         5318                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22559                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        22559                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       229117                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        229117                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       259835                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       259835                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995314                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11995314                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489954                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7489954                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22544                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        22544                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       229101                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        229101                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       259820                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       259820                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995292                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11995292                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489946                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      7489946                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80818                       # number of SoftPFReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::total        80818                       # number of SoftPFReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96765                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        96765                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94979                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        94979                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     19485268                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     19485268                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     19566086                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     19566086                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011391                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.011391                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012347                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.012347                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380089                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380089                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.demand_accesses::cpu1.data     19485238                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     19485238                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     19566056                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     19566056                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011390                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.011390                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012346                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.012346                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380101                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380101                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054958                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054958                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237516                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237516                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237358                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237358                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011758                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     0.011758                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013280                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.013280                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -772,42 +769,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       120692                       # number of writebacks
-system.cpu1.dcache.writebacks::total           120692                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       120709                       # number of writebacks
+system.cpu1.dcache.writebacks::total           120709                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           523402                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.711076                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           53148754                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           523914                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           101.445569                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           523373                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.711131                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           53148636                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           523885                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           101.450960                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle      76931404500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711076                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711131                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975998                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.975998                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        107869250                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       107869250                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     53148754                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       53148754                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     53148754                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        53148754                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     53148754                       # number of overall hits
-system.cpu1.icache.overall_hits::total       53148754                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       523914                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       523914                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       523914                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        523914                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       523914                       # number of overall misses
-system.cpu1.icache.overall_misses::total       523914                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672668                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     53672668                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     53672668                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     53672668                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     53672668                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     53672668                       # number of overall (read+write) accesses
+system.cpu1.icache.tags.tag_accesses        107868927                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       107868927                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     53148636                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       53148636                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     53148636                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        53148636                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     53148636                       # number of overall hits
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+system.cpu1.icache.ReadReq_misses::cpu1.inst       523885                       # number of ReadReq misses
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+system.cpu1.icache.demand_misses::cpu1.inst       523885                       # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::cpu1.inst       523885                       # number of overall misses
+system.cpu1.icache.overall_misses::total       523885                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672521                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     53672521                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     53672521                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     53672521                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     53672521                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     53672521                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009761                       # miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_miss_rate::total     0.009761                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009761                       # miss rate for demand accesses
@@ -832,121 +829,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           48632                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15302.414906                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            716436                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           63462                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           11.289212                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements           48598                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15305.342188                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            716678                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           63421                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           11.300326                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  8289.533576                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     4.964027                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.029845                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3282.932073                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3722.955385                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.505953                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000303                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8327.809104                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     4.085339                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.030831                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3278.951411                       # Average occupied blocks per requestor
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 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000124                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.200131                       # Average percentage of cache occupancy
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 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          554                       # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001587                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903564                       # Percentage of cache occupancy per task id
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-system.cpu1.l2cache.ReadReq_hits::total        614395                       # number of ReadReq hits
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-system.cpu1.l2cache.Writeback_hits::total       120692                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            7                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total            7                       # number of UpgradeReq hits
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-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999757                       # miss rate for UpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.132122                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026481                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495814                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.171896                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.095967                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.132122                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026481                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495814                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.171896                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.688726                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.688726                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.098596                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.136273                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026355                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495804                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.171844                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.098596                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.136273                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026355                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495804                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.171844                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -955,45 +952,45 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        32939                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           32939                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        32919                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           32919                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        709339                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       709339                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq        709301                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       709301                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         2505                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         2505                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       120692                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        28863                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22559                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        51422                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        63615                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        63615                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1048182                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707576                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.trans_dist::Writeback       120709                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        28855                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22544                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        51399                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        63616                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        63616                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1048124                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707533                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12080                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          1774454                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33531204                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22866030                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12078                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          1774351                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33529348                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22866670                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          56434626                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     499621                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1371622                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.313465                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.463902                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24156                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          56433406                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     499587                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1371557                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.313464                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.463901                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5            941666     68.65%     68.65% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            429956     31.35%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5            941623     68.65%     68.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            429934     31.35%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1371622                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total       1371557                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                31002                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31002                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59433                       # Transaction distribution
@@ -1050,23 +1047,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse               14.586086                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.586092                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         246641286009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.586086                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.911630                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.911630                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide    14.586092                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.911631                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.911631                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
@@ -1081,6 +1078,8 @@ system.iocache.overall_accesses::realview.ide          252
 system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -1091,187 +1090,188 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   107659                       # number of replacements
-system.l2c.tags.tagsinuse                62143.932416                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     208094                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168104                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.237888                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   107620                       # number of replacements
+system.l2c.tags.tagsinuse                62052.354763                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     207975                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168018                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.237814                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48688.063077                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.972782                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030392                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7324.743178                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3758.906335                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.829103                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1656.372339                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      711.015210                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.742921                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   48595.577563                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.970677                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030393                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7329.733330                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3756.722499                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.823230                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1654.519056                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      710.978017                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.741510                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.111767                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.057356                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.111843                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.057323                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000028                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.025274                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.025246                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.010849                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.948241                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        60436                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1910                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        13081                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        45354                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000137                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.922180                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  4903872                       # Number of tag accesses
-system.l2c.tags.data_accesses                 4903872                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker           74                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker           63                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst              28084                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data              76119                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           40                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           38                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              11510                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              11381                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 127309                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          225809                       # number of Writeback hits
-system.l2c.Writeback_hits::total               225809                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             496                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              63                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 559                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            61                       # number of SCUpgradeReq hits
+system.l2c.tags.occ_percent::total           0.946844                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        60392                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1918                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        13006                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        45390                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.921509                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  4903951                       # Number of tag accesses
+system.l2c.tags.data_accesses                 4903951                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker           85                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker           75                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst              28112                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data              75977                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker           41                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker           36                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst              11436                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              11429                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 127191                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          225760                       # number of Writeback hits
+system.l2c.Writeback_hits::total               225760                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             516                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              57                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 573                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            52                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                70                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            13793                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             3108                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                16901                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker            74                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            63                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               28084                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               89912                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            40                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            38                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               11510                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               14489                       # number of demand (read+write) hits
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-system.l2c.overall_hits::total                 144210                       # number of overall hits
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 system.l2c.ReadReq_misses::cpu0.dtb.walker            7                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
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 system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu0.data         10009                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3295                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             13304                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          759                       # number of SCUpgradeReq misses
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 system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             16891                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            148074                       # number of demand (read+write) misses
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 system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total                184335                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            16891                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           148074                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            16900                       # number of overall misses
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 system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2364                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            16943                       # number of overall misses
-system.l2c.overall_misses::total               184283                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker           81                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total             159003                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       225809                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           225809                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        10505                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3358                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.UpgradeReq_accesses::total           13863                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          820                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.overall_accesses::cpu0.dtb.walker           81                       # number of overall (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.086420                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.375564                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.129312                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.170391                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.089811                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.199330                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.952784                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.981239                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.959677                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.925610                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.992450                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.965209                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.908390                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.835799                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.900283                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.086420                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.375564                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.622196                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.170391                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.539037                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.560995                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.086420                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.375564                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.622196                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.170391                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.539037                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.560995                       # miss rate for overall accesses
+system.l2c.SCUpgradeReq_accesses::cpu0.data          823                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1186                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2009                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       150714                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        18925                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.demand_accesses::cpu0.dtb.walker           92                       # number of demand (read+write) accesses
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+system.l2c.overall_accesses::cpu0.dtb.walker           92                       # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.076087                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.375455                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.129583                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.046512                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.171724                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.089250                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.199573                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.950890                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.983015                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.958667                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.936817                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.992411                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.969637                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.907653                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.836248                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.899687                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.076087                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.375455                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.622293                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.046512                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.171724                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.538413                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.561068                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.076087                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.375455                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.622293                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.046512                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.171724                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.538413                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.561068                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1280,49 +1280,49 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               94871                       # number of writebacks
-system.l2c.writebacks::total                    94871                       # number of writebacks
+system.l2c.writebacks::writebacks               94860                       # number of writebacks
+system.l2c.writebacks::total                    94860                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               75959                       # Transaction distribution
-system.membus.trans_dist::ReadResp              75959                       # Transaction distribution
+system.membus.trans_dist::ReadReq               75978                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75978                       # Transaction distribution
 system.membus.trans_dist::WriteReq              30905                       # Transaction distribution
 system.membus.trans_dist::WriteResp             30905                       # Transaction distribution
-system.membus.trans_dist::Writeback             94871                       # Transaction distribution
+system.membus.trans_dist::Writeback            131050                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60398                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40937                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15640                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            196324                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           152195                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            60385                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40916                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15642                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            196304                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           152218                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107918                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       652163                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       773589                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72952                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72952                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 846541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       652161                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       773587                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 882729                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162808                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17897572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18087396                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2334464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2334464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20421860                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17899556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18089380                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4650624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4650624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22740004                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            460700                       # Request fanout histogram
+system.membus.snoop_fanout::samples            496844                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  460700    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  496844    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              460700                       # Request fanout histogram
+system.membus.snoop_fanout::total              496844                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1354,33 +1354,33 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             305363                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            305363                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             305179                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            305179                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             30905                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            30905                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           225809                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           60563                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41007                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         101570                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           213619                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          213619                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1117852                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       410871                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1528723                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34663730                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10432818                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               45096548                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::Writeback           225760                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           60554                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40977                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         101531                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           213725                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          213725                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1117779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       410661                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1528440                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34662706                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10425714                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45088420                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                           36713                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           838824                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.043485                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.203946                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples           838658                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.043493                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.203965                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 802348     95.65%     95.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 802182     95.65%     95.65% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                  36476      4.35%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             838824                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total             838658                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 755cdf962..5c160a43e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,59 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783854                       # Number of seconds simulated
-sim_ticks                                2783854461500                       # Number of ticks simulated
-final_tick                               2783854461500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783867                       # Number of seconds simulated
+sim_ticks                                2783867165000                       # Number of ticks simulated
+final_tick                               2783867165000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1414038                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1721363                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27571822204                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560116                       # Number of bytes of host memory used
-host_seconds                                   100.97                       # Real time elapsed on the host
-sim_insts                                   142771592                       # Number of instructions simulated
-sim_ops                                     173801445                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1064003                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1295252                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            20746494205                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 558936                       # Number of bytes of host memory used
+host_seconds                                   134.19                       # Real time elapsed on the host
+sim_insts                                   142773109                       # Number of instructions simulated
+sim_ops                                     173803334                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1210980                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10345892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1210852                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10328292                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11558408                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1210980                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210980                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6521536                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11540680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1210852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1210852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8837632                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8857396                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8855156                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27375                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             162174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27373                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             161899                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189573                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          101899                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                189296                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138088                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142504                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142469                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               435001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3716391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               434953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3710052                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4151944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          435001                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             435001                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2342628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4145557                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          434953                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             434953                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3174588                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          832779                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3181702                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2342628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3180883                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3174588                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              435001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3722686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          833124                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7333646                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              434953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3716347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7326440                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -96,9 +93,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     31525959                       # DTB read hits
-system.cpu.dtb.read_misses                       8580                       # DTB read misses
-system.cpu.dtb.write_hits                    23124081                       # DTB write hits
+system.cpu.dtb.read_hits                     31526301                       # DTB read hits
+system.cpu.dtb.read_misses                       8581                       # DTB read misses
+system.cpu.dtb.write_hits                    23124463                       # DTB write hits
 system.cpu.dtb.write_misses                      1448                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -109,12 +106,12 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 31534539                       # DTB read accesses
-system.cpu.dtb.write_accesses                23125529                       # DTB write accesses
+system.cpu.dtb.read_accesses                 31534882                       # DTB read accesses
+system.cpu.dtb.write_accesses                23125911                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          54650040                       # DTB hits
-system.cpu.dtb.misses                           10028                       # DTB misses
-system.cpu.dtb.accesses                      54660068                       # DTB accesses
+system.cpu.dtb.hits                          54650764                       # DTB hits
+system.cpu.dtb.misses                           10029                       # DTB misses
+system.cpu.dtb.accesses                      54660793                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -136,7 +133,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    147038107                       # ITB inst hits
+system.cpu.itb.inst_hits                    147039592                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -153,38 +150,38 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                147042869                       # ITB inst accesses
-system.cpu.itb.hits                         147038107                       # DTB hits
+system.cpu.itb.inst_accesses                147044354                       # ITB inst accesses
+system.cpu.itb.hits                         147039592                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     147042869                       # DTB accesses
-system.cpu.numCycles                       5567712004                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     147044354                       # DTB accesses
+system.cpu.numCycles                       5567737414                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   142771592                       # Number of instructions committed
-system.cpu.committedOps                     173801445                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             153161099                       # Number of integer alu accesses
+system.cpu.committedInsts                   142773109                       # Number of instructions committed
+system.cpu.committedOps                     173803334                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             153162826                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
-system.cpu.num_func_calls                    16873874                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18730301                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    153161099                       # number of integer instructions
+system.cpu.num_func_calls                    16873879                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18730390                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    153162826                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285057250                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          107178308                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           285060124                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          107179564                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            530849099                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            62363961                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      55938603                       # number of memory refs
-system.cpu.num_load_insts                    31855595                       # Number of load instructions
-system.cpu.num_store_insts                   24083008                       # Number of store instructions
-system.cpu.num_idle_cycles               5389630193.939086                       # Number of idle cycles
-system.cpu.num_busy_cycles               178081810.060914                       # Number of busy cycles
+system.cpu.num_cc_register_reads            530854681                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            62364458                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      55939365                       # number of memory refs
+system.cpu.num_load_insts                    31855962                       # Number of load instructions
+system.cpu.num_store_insts                   24083403                       # Number of store instructions
+system.cpu.num_idle_cycles               5389653746.932553                       # Number of idle cycles
+system.cpu.num_busy_cycles               178083667.067447                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
-system.cpu.Branches                          36396923                       # Number of branches fetched
+system.cpu.Branches                          36397028                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 121151902     68.36%     68.36% # Class of executed instruction
-system.cpu.op_class::IntMult                   116873      0.07%     68.43% # Class of executed instruction
+system.cpu.op_class::IntAlu                 121152975     68.36%     68.36% # Class of executed instruction
+system.cpu.op_class::IntMult                   116892      0.07%     68.43% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     68.43% # Class of executed instruction
@@ -212,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc               8569      0.00%     68.44% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 31855595     17.98%     86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite                24083008     13.59%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 31855962     17.98%     86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                24083403     13.59%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  177218284                       # Class of executed instruction
+system.cpu.op_class::total                  177220138                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3080                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements            819396                       # number of replacements
+system.cpu.kern.inst.quiesce                     3083                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements            819403                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            53783832                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819908                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.597399                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            53784550                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819915                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.597714                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
@@ -233,58 +230,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          286
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         219234948                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        219234948                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     30128799                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30128799                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     22339754                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       22339754                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       395065                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        395065                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       457334                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457334                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460122                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      52468553                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         52468553                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     52863618                       # number of overall hits
-system.cpu.dcache.overall_hits::total        52863618                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       396285                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        396285                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       301663                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       301663                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       116121                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       116121                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data         8611                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8611                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         219237855                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        219237855                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     30129122                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30129122                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22340107                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22340107                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395080                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395080                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457347                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457347                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460136                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      52469229                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52469229                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     52864309                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52864309                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       396277                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396277                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301678                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       116120                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       116120                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       697948                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         697948                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       814069                       # number of overall misses
-system.cpu.dcache.overall_misses::total        814069                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     30525084                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30525084                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     22641417                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     22641417                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511186                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511186                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465945                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460124                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     53166501                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     53166501                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     53677687                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     53677687                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_misses::cpu.data       697955                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697955                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       814075                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814075                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     30525399                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30525399                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641785                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641785                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511200                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511200                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460138                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     53167184                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53167184                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53678384                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53678384                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.227160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018481                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018481                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227152                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.227152                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018482                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018482                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
@@ -299,16 +296,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       682037                       # number of writebacks
-system.cpu.dcache.writebacks::total            682037                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682060                       # number of writebacks
+system.cpu.dcache.writebacks::total            682060                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1699006                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           145341690                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1699518                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             85.519359                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1699220                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           145342961                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699732                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.509340                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.663679                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.663681                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -317,32 +314,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         148740738                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        148740738                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    145341690                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       145341690                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     145341690                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        145341690                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    145341690                       # number of overall hits
-system.cpu.icache.overall_hits::total       145341690                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1699524                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1699524                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1699524                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1699524                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1699524                       # number of overall misses
-system.cpu.icache.overall_misses::total       1699524                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    147041214                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    147041214                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    147041214                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    147041214                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    147041214                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    147041214                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011558                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.011558                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.011558                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         148742437                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        148742437                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    145342961                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145342961                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     145342961                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145342961                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    145342961                       # number of overall hits
+system.cpu.icache.overall_hits::total       145342961                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1699738                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699738                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1699738                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699738                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1699738                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699738                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    147042699                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147042699                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    147042699                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147042699                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147042699                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147042699                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011559                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.011559                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.011559                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,21 +350,21 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           110027                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65155.314992                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2727662                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        65155.309065                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2727894                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           175308                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            15.559256                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            15.560579                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931995                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004344                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.654834                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.310003                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.659727                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.315067                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109776                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.109777                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
@@ -379,29 +376,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26202418                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26202418                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7597                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         26204409                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26204409                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1681149                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       505483                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2197850                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       682037                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       682037                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1681362                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       505475                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2198059                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       682060                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       682060                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151043                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151043                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7597                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151058                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151058                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681149                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656526                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2348893                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7597                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681362                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2349117                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681149                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656526                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2348893                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681362                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656533                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2349117                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.inst        18358                       # number of ReadReq misses
@@ -423,50 +420,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker            2
 system.cpu.l2cache.overall_misses::cpu.inst        18358                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       181765                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7604                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699507                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       521017                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2231751                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       682037                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       682037                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699720                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       521009                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2231960                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       682060                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       682060                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       298907                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       298907                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7604                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1699507                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819924                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2530658                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7604                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1699720                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819931                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2530882                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7608                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1699507                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819924                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2530658                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699720                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819931                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530882                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010802                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010801                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029815                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015190                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015189                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494682                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494682                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010802                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199284                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071825                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010801                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071819                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010802                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199284                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071825                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010801                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071819                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -475,45 +472,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101899                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101899                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101898                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101898                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2288348                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2288348                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2288556                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288556                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27560                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27560                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       682037                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       682060                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       298907                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       298907                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417092                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444665                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417520                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444702                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        36996                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5917183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108805624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308299                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37000                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5917652                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108819320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96310219                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        73992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205224775                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       36632                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3268420                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205240399                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       36631                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3268666                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        5.011156                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.105033                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.105029                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            3231956     98.88%     98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3232202     98.88%     98.88% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::6              36464      1.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3268420                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        3268666                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30171                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30171                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59016                       # Transaction distribution
@@ -570,23 +567,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480255                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909893                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909962                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909893                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.909962                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          240                       # number of overall misses
@@ -601,6 +598,8 @@ system.iocache.overall_accesses::realview.ide          240
 system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -611,14 +610,16 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               74235                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74235                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27560                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27560                       # Transaction distribution
-system.membus.trans_dist::Writeback            101899                       # Transaction distribution
+system.membus.trans_dist::Writeback            138088                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
@@ -629,31 +630,31 @@ system.membus.trans_dist::ReadExResp           146085                       # Tr
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105446                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       498795                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       606197                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 679125                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       498794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       606196                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 715314                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159103                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18096508                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18259523                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20593219                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18096444                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18259459                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22909315                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            322858                       # Request fanout histogram
+system.membus.snoop_fanout::samples            359047                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  322858    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  359047    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              322858                       # Request fanout histogram
+system.membus.snoop_fanout::total              359047                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 23357c831..ede2b82db 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,169 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.866913                       # Number of seconds simulated
-sim_ticks                                2866913114000                       # Number of ticks simulated
-final_tick                               2866913114000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.867049                       # Number of seconds simulated
+sim_ticks                                2867048515500                       # Number of ticks simulated
+final_tick                               2867048515500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 786450                       # Simulator instruction rate (inst/s)
-host_op_rate                                   951292                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17090693254                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 609256                       # Number of bytes of host memory used
-host_seconds                                   167.75                       # Real time elapsed on the host
-sim_insts                                   131924636                       # Number of instructions simulated
-sim_ops                                     159576421                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 753572                       # Simulator instruction rate (inst/s)
+host_op_rate                                   911512                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            16376301643                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 607016                       # Number of bytes of host memory used
+host_seconds                                   175.07                       # Real time elapsed on the host
+sim_insts                                   131930165                       # Number of instructions simulated
+sim_ops                                     159581077                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           236004                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data           838784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      9619456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           233060                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data           810048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      9243456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            50964                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           440736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      1362944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            53844                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           455584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      1704320                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12550680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       236004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        50964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          286968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6395008                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12502168                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       233060                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        53844                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          286904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8696768                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8731088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8714512                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             13632                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       150304                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12095                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             13183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       144429                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               951                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              6910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        21296                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               996                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              7142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        26630                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                205262                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           99922                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                204504                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          135887                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               140582                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               140323                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           179                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               82320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              292574                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3355336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            67                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               81289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              282537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3224032                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            89                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               17777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              153732                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       475405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               18780                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              158903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       594451                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4377768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          82320                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          17777                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             100097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2230625                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4360641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          81289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          18780                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             100069                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3033352                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6175                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          808652                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3045467                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2230625                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3039541                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3033352                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          179                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              82320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             298749                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3355336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           67                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              81289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             288712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3224032                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           89                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              17777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             153746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       475405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          808987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7423234                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        205263                       # Number of read requests accepted
-system.physmem.writeReqs                       140582                       # Number of write requests accepted
-system.physmem.readBursts                      205263                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     140582                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 13120768                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     16064                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8744768                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12550744                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8731088                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      251                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3914                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          15112                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12846                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12299                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               13037                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12736                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               21227                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12513                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12853                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12957                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12050                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12106                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12270                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11010                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11804                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12158                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11709                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11437                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8735                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8638                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9213                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8824                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8594                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8713                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8840                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8875                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8399                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8546                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8611                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8118                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8409                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8327                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8185                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7610                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst              18780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             158917                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       594451                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7400182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        204505                       # Number of read requests accepted
+system.physmem.writeReqs                       176547                       # Number of write requests accepted
+system.physmem.readBursts                      204505                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     176547                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 13079232                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9088                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10932800                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12502232                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11032848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      142                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5691                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          15171                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12666                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12263                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12897                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12449                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               21010                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12626                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12991                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13024                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12039                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12109                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12276                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10996                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11725                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12231                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11672                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11389                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10702                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10814                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               11122                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10684                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10817                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               11014                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11094                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               11085                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10650                       # Per bank write bursts
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+system.physmem.perBankWrBursts::11              10150                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10760                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10359                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10115                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9574                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2866912757000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2867048141000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9742                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  195493                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  194735                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 136146                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    121382                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21626                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     11136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      9518                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      8180                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      7045                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      6231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      5373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       545                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 172111                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    120800                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     21636                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8                      5370                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::10                      257                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      171                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      166                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                      124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       75                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       70                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                       45                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -191,154 +188,178 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16                     3299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9789                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      211                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                      201                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42                      142                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::46                      113                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::51                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        80938                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.150881                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.124225                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     319.049708                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          39103     48.31%     48.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16130     19.93%     68.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6485      8.01%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3355      4.15%     80.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3128      3.86%     84.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1920      2.37%     86.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1075      1.33%     87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1014      1.25%     89.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8728     10.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          80938                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6722                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.497025                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      543.729847                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6720     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4683                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        83215                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      288.553362                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     159.296581                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.078048                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          39267     47.19%     47.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16171     19.43%     66.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6480      7.79%     74.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3347      4.02%     78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3132      3.76%     82.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1913      2.30%     84.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1073      1.29%     85.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1034      1.24%     87.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10798     12.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          83215                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7042                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.019171                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-2047           7040     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6722                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6722                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.326837                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.830242                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.742760                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5511     81.98%     81.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             381      5.67%     87.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              92      1.37%     89.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             211      3.14%     92.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             209      3.11%     95.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.31%     95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              13      0.19%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.21%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              24      0.36%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.12%     96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.07%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.06%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             163      2.42%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               8      0.12%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.04%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              17      0.25%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.10%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.04%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             7      0.10%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.12%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6722                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5976562250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9820537250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1025060000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29152.26                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7042                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7042                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.258023                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.337274                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.786425                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5509     78.23%     78.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             384      5.45%     83.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              77      1.09%     84.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             222      3.15%     87.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             122      1.73%     89.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              57      0.81%     90.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              43      0.61%     91.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.53%     91.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             124      1.76%     93.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              15      0.21%     93.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              18      0.26%     93.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              16      0.23%     94.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              34      0.48%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              16      0.23%     94.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.10%     94.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.38%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              62      0.88%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              11      0.16%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.09%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              10      0.14%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              88      1.25%     97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     97.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            12      0.17%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             6      0.09%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            19      0.27%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            11      0.16%     98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             4      0.06%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            36      0.51%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            11      0.16%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.06%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.10%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.07%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             7      0.10%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             4      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7042                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5974898500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9806704750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1021815000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29236.69                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47902.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.58                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47986.69                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.56                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.81                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.36                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.85                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.80                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     175010                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     85700                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  62.71                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8289588.56                       # Average gap between requests
-system.physmem.pageHitRate                      76.30                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2731202883250                       # Time in different power states
-system.physmem.memoryStateTime::REF       95732520000                       # Time in different power states
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         2.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     174382                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    117590                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  68.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      7524033.84                       # Average gap between requests
+system.physmem.pageHitRate                      77.81                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2731090191250                       # Time in different power states
+system.physmem.memoryStateTime::REF       95736940000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       39977707750                       # Time in different power states
+system.physmem.memoryStateTime::ACT       40221363750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 322237440                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 289653840                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 175824000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 158045250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                861650400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                737435400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               456399360                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               429008400                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          187252809120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          187252809120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           82565899920                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           81397166220                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1647721613250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1648746818250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1919356433490                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1919010936480                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.485397                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.364885                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 330432480                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 298672920                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 180295500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 162966375                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                857422800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                736600800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               565911360                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               541034640                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          187261454640                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          187261454640                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           82724898285                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           81530993385                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1647661560750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1648708845750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1919581975815                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1919240568510                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.533155                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.414075                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -387,25 +408,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24351477                       # DTB read hits
-system.cpu0.dtb.read_misses                      6408                       # DTB read misses
-system.cpu0.dtb.write_hits                   18124986                       # DTB write hits
-system.cpu0.dtb.write_misses                     1114                       # DTB write misses
+system.cpu0.dtb.read_hits                    22739909                       # DTB read hits
+system.cpu0.dtb.read_misses                      4142                       # DTB read misses
+system.cpu0.dtb.write_hits                   16676295                       # DTB write hits
+system.cpu0.dtb.write_misses                      677                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3406                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2392                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1440                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1346                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24357885                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18126100                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      187                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                22744051                       # DTB read accesses
+system.cpu0.dtb.write_accesses               16676972                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         42476463                       # DTB hits
-system.cpu0.dtb.misses                           7522                       # DTB misses
-system.cpu0.dtb.accesses                     42483985                       # DTB accesses
+system.cpu0.dtb.hits                         39416204                       # DTB hits
+system.cpu0.dtb.misses                           4819                       # DTB misses
+system.cpu0.dtb.accesses                     39421023                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -427,8 +448,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   115065570                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3350                       # ITB inst misses
+system.cpu0.itb.inst_hits                   107931670                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2300                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -437,179 +458,178 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2152                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1397                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               115068920                       # ITB inst accesses
-system.cpu0.itb.hits                        115065570                       # DTB hits
-system.cpu0.itb.misses                           3350                       # DTB misses
-system.cpu0.itb.accesses                    115068920                       # DTB accesses
-system.cpu0.numCycles                      5733826228                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               107933970                       # ITB inst accesses
+system.cpu0.itb.hits                        107931670                       # DTB hits
+system.cpu0.itb.misses                           2300                       # DTB misses
+system.cpu0.itb.accesses                    107933970                       # DTB accesses
+system.cpu0.numCycles                      5733190951                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  111421445                       # Number of instructions committed
-system.cpu0.committedOps                    134708041                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            119418221                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
-system.cpu0.num_func_calls                   12527454                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14979151                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   119418221                       # number of integer instructions
-system.cpu0.num_fp_insts                         9755                       # number of float instructions
-system.cpu0.num_int_register_reads          220362058                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          83043778                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           488373650                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           49988627                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     43585923                       # number of memory refs
-system.cpu0.num_load_insts                   24597873                       # Number of load instructions
-system.cpu0.num_store_insts                  18988050                       # Number of store instructions
-system.cpu0.num_idle_cycles              5477680330.504089                       # Number of idle cycles
-system.cpu0.num_busy_cycles              256145897.495911                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.044673                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.955327                       # Percentage of idle cycles
-system.cpu0.Branches                         28215151                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2272      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 94727035     68.43%     68.43% # Class of executed instruction
-system.cpu0.op_class::IntMult                  104174      0.08%     68.51% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              7381      0.01%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.51% # Class of executed instruction
-system.cpu0.op_class::MemRead                24597873     17.77%     86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite               18988050     13.72%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                  104697045                       # Number of instructions committed
+system.cpu0.committedOps                    126437300                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            112138973                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4560                       # Number of float alu accesses
+system.cpu0.num_func_calls                   12218983                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14112779                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   112138973                       # number of integer instructions
+system.cpu0.num_fp_insts                         4560                       # number of float instructions
+system.cpu0.num_int_register_reads          207168140                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          78157614                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3646                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           458862041                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           46623468                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     40473955                       # number of memory refs
+system.cpu0.num_load_insts                   22968630                       # Number of load instructions
+system.cpu0.num_store_insts                  17505325                       # Number of store instructions
+system.cpu0.num_idle_cycles              5494072814.437573                       # Number of idle cycles
+system.cpu0.num_busy_cycles              239118136.562427                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.041708                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.958292                       # Percentage of idle cycles
+system.cpu0.Branches                         26957408                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2171      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 89486890     68.80%     68.80% # Class of executed instruction
+system.cpu0.op_class::IntMult                   99356      0.08%     68.88% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              6997      0.01%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.88% # Class of executed instruction
+system.cpu0.op_class::MemRead                22968630     17.66%     86.54% # Class of executed instruction
+system.cpu0.op_class::MemWrite               17505325     13.46%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 138426785                       # Class of executed instruction
+system.cpu0.op_class::total                 130069369                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2075                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           658574                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          484.573597                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           41679745                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           659086                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            63.238705                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    1990                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           555287                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          484.900335                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           38705991                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           555652                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            69.658691                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1015660000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.573597                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.946433                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.946433                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         85564578                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        85564578                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     23153254                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23153254                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     17430094                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      17430094                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       323112                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       323112                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       358254                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       358254                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       353760                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       353760                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     40583348                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        40583348                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     40906460                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       40906460                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       360294                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       360294                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       297575                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       297575                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       106237                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       106237                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21398                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21398                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21370                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21370                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       657869                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        657869                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       764106                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       764106                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4477052020                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   4477052020                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4450265428                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   4450265428                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    335153501                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    335153501                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    473430117                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    473430117                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1336000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1336000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8927317448                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8927317448                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8927317448                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8927317448                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     23513548                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23513548                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17727669                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17727669                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       429349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       429349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379652                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       379652                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       375130                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       375130                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     41241217                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     41241217                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     41670566                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     41670566                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.015323                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.015323                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016786                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.016786                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.247437                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.247437                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056362                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056362                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056967                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056967                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.015952                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.015952                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018337                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.018337                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.900335                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947071                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.947071                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         79342035                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        79342035                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     21654746                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       21654746                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     16040843                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      16040843                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       304713                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       304713                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       334336                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       334336                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       329300                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       329300                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     37695589                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        37695589                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     38000302                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       38000302                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       304912                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       304912                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       263418                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       263418                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        92252                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total        92252                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20070                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20070                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20705                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20705                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       568330                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        568330                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       660582                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       660582                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3916535020                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3916535020                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4029841681                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4029841681                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    322461501                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    322461501                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    462579693                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    462579693                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1480500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1480500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   7946376701                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   7946376701                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   7946376701                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   7946376701                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     21959658                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     21959658                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     16304261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     16304261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       396965                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       396965                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       354406                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       354406                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       350005                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       350005                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     38263919                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     38263919                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     38660884                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     38660884                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013885                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.013885                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016156                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.016156                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.232393                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.232393                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056630                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056630                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.059156                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.059156                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.014853                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.014853                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.017087                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.017087                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -618,82 +638,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       483361                       # number of writebacks
-system.cpu0.dcache.writebacks::total           483361                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7378                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total         7378                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15071                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15071                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data         7378                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total         7378                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data         7378                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total         7378                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       352916                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       352916                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       297575                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       297575                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        96924                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        96924                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6327                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6327                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21370                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21370                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       650491                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       650491                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       747415                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       747415                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3678269480                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3678269480                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3844865572                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3844865572                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1196073992                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1196073992                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     89532500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89532500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    429878883                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    429878883                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1262000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1262000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7523135052                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7523135052                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8719209044                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   8719209044                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5564453750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5564453750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4183862994                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4183862994                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9748316744                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9748316744                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015009                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015009                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016786                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.016786                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225746                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225746                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016665                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016665                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056967                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056967                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017936                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.017936                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       420867                       # number of writebacks
+system.cpu0.dcache.writebacks::total           420867                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7211                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total         7211                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14132                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14132                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data         7211                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total         7211                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data         7211                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total         7211                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       297701                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       297701                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       263418                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       263418                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        83423                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        83423                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         5938                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5938                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20705                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20705                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       561119                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       561119                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       644542                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       644542                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3232031980                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3232031980                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3494328319                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3494328319                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1040331239                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1040331239                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     86260500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     86260500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    420440307                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    420440307                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1400500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1400500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6726360299                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   6726360299                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7766691538                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7766691538                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5556589244                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5556589244                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4171949493                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4171949493                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9728538737                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9728538737                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.013557                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.013557                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016156                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.016156                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.210152                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.210152                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016755                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016755                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.059156                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.059156                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.014664                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.014664                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.016672                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.016672                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -701,58 +721,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1061124                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.483230                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          114003925                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1061636                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           107.385135                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           945322                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.483250                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          106985827                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           945834                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           113.112689                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      12806917500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.483230                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.483250                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998991                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998991                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          390                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3          113                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::4            9                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        231192785                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       231192785                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    114003925                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      114003925                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    114003925                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       114003925                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    114003925                       # number of overall hits
-system.cpu0.icache.overall_hits::total      114003925                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1061645                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1061645                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1061645                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1061645                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1061645                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1061645                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9000982497                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   9000982497                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   9000982497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   9000982497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   9000982497                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   9000982497                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    115065570                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115065570                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    115065570                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115065570                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    115065570                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115065570                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009226                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009226                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009226                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009226                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009226                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009226                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8478.335505                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8478.335505                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8478.335505                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8478.335505                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8478.335505                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8478.335505                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        216809183                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       216809183                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    106985827                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      106985827                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    106985827                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       106985827                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    106985827                       # number of overall hits
+system.cpu0.icache.overall_hits::total      106985827                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       945843                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       945843                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       945843                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        945843                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       945843                       # number of overall misses
+system.cpu0.icache.overall_misses::total       945843                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   8025066767                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8025066767                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   8025066767                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8025066767                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   8025066767                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8025066767                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    107931670                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    107931670                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    107931670                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    107931670                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    107931670                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    107931670                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.008763                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.008763                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.008763                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.008763                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.008763                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.008763                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8484.565374                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8484.565374                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8484.565374                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8484.565374                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8484.565374                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8484.565374                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -761,359 +781,356 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1061645                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1061645                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1061645                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1061645                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1061645                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1061645                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   7407816003                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7407816003                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   7407816003                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7407816003                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   7407816003                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7407816003                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       945843                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       945843                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       945843                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       945843                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       945843                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       945843                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6605629733                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6605629733                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6605629733                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6605629733                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6605629733                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6605629733                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    719096500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    719096500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009226                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009226                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009226                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6977.677098                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  6977.677098                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  6977.677098                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.008763                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.008763                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.008763                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.008763                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.008763                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.008763                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6983.854332                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6983.854332                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6983.854332                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  6983.854332                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6983.854332                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  6983.854332                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      9923384                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       228338                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      9249316                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          376                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      8798864                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       212139                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      8184021                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          360                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           35                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       445319                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       778112                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           34                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       402310                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       695408                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          357554                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16100.801595                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           1935390                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          373791                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.177733                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements          309925                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16107.929627                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1687462                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          325154                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.189732                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6719.608952                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.125628                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.135893                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   793.879272                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1140.668616                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7443.383233                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.410132                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000191                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.048455                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.069621                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.454308                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.982715                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         7987                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8246                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           35                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          107                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1881                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4986                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          978                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2886                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4666                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          532                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.487488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.503296                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        38013369                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       38013369                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7065                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3186                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1046032                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       372434                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1428717                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       483361                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       483361                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        10097                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        10097                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2054                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2054                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212764                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       212764                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7065                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3186                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1046032                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       585198                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1641481                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7065                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3186                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1046032                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       585198                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1641481                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          284                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          213                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        15613                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        83733                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        99843                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        29803                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        29803                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19308                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19308                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6744.420736                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.207457                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.111326                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   773.977995                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1150.108298                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7436.103816                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.411647                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000196                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.047240                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.070197                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.453864                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983150                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         9588                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         5627                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           66                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         1190                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         8332                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2          265                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1207                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4155                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.585205                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.343445                       # Percentage of cache occupancy per task id
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total    522877259                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038645                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.746942                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.903848                       # miss rate for SCUpgradeReq accesses
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-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.062665                       # miss rate for demand accesses
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312                       # average SCUpgradeReq miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         6544                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.184321                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.184321                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.065963                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.094630                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.013326                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.194083                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.084250                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.065963                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.094630                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.013326                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.194083                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.084250                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21781.428571                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20642.857143                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 42135.927007                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27314.979085                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29338.721437                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17673.471476                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17673.471476                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19510.878627                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19510.878627                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 170061.875000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 170061.875000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33833.261348                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33833.261348                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21781.428571                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20642.857143                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 42135.927007                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29586.432612                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 30748.102867                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21781.428571                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20642.857143                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 42135.927007                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29586.432612                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 30748.102867                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         6541                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              99                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs             102                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    66.101010                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    64.127451                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       205226                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          205226                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         2290                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         2728                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         5018                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1210                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1210                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         2290                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3938                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6228                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         2290                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3938                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6228                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          284                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          213                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        13323                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        81005                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        94825                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       445317                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       445317                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        29803                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        29803                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19308                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19308                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       191905                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          191905                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         1866                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1034                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         1866                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        29431                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        29431                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19057                       # number of SCUpgradeReq MSHR misses
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 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43701                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        43701                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          284                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          213                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       124706                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       138526                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total       583843                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2130941732                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17831693567                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17831693567                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    489548028                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    489548028                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    261537598                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    261537598                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       965995                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       965995                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1080387358                       # number of ReadExReq MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::total   3211329090                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   2745849324                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  21043022657                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5172000                       # number of ReadReq MSHR miss cycles
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16697606620                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16697606620                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    471565864                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    471565864                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    257027175                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    257027175                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1080495                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1080495                       # number of SCUpgradeFailReq MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    647208500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5328411497                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5975619997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3986952006                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3986952006                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5320901002                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5968109502                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3975516507                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3975516507                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    647208500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9315363503                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9962572003                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.177578                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062036                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9296417509                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9943626009                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.065963                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.094630                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.011353                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.192799                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.064111                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.746942                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.746942                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.903848                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.903848                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.753173                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.753173                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.920761                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.920761                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.169597                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.169597                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.174697                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.077552                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.174697                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.179712                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.179712                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.065963                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.094630                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.011353                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.187997                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.080680                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.065963                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.094630                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.011353                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.187997                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.326857                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.337710                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1123,57 +1140,57 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       1734345                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1628634                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        26254                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        26254                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       483361                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       595652                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        80946                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43669                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       101586                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       279437                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       269063                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2141334                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2249028                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9800                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        21070                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          4421232                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     67981368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80878536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13596                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        29396                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         148902896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     988296                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3215199                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.272128                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.445055                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq       1585084                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1436635                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        26190                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        26190                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       420867                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       537670                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        82377                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43315                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       100677                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           43                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           75                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       246727                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       235853                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      1909730                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      1979159                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         7030                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        14021                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          3909940                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     60570040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     70330266                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10652                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        21224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         130932182                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     972661                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      2913864                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.296127                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.456548                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           2340254     72.79%     72.79% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            874945     27.21%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2050990     70.39%     70.39% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            862874     29.61%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3215199                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1699304627                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       2913864                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    1492069922                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115610498                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    116074499                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1603950497                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1150471329                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1430234267                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy    995136418                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      6401000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      4367000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     13721750                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy      8715750                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -1198,25 +1215,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4826061                       # DTB read hits
-system.cpu1.dtb.read_misses                      2744                       # DTB read misses
-system.cpu1.dtb.write_hits                    4130169                       # DTB write hits
-system.cpu1.dtb.write_misses                      524                       # DTB write misses
+system.cpu1.dtb.read_hits                     6438534                       # DTB read hits
+system.cpu1.dtb.read_misses                      5066                       # DTB read misses
+system.cpu1.dtb.write_hits                    5578600                       # DTB write hits
+system.cpu1.dtb.write_misses                      983                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    3048                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   437                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   541                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4828805                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4130693                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      258                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 6443600                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5579583                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          8956230                       # DTB hits
-system.cpu1.dtb.misses                           3268                       # DTB misses
-system.cpu1.dtb.accesses                      8959498                       # DTB accesses
+system.cpu1.dtb.hits                         12017134                       # DTB hits
+system.cpu1.dtb.misses                           6049                       # DTB misses
+system.cpu1.dtb.accesses                     12023183                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1238,8 +1255,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    20883965                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1747                       # ITB inst misses
+system.cpu1.itb.inst_hits                    28023624                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2794                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1248,178 +1265,179 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1149                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1901                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20885712                       # ITB inst accesses
-system.cpu1.itb.hits                         20883965                       # DTB hits
-system.cpu1.itb.misses                           1747                       # DTB misses
-system.cpu1.itb.accesses                     20885712                       # DTB accesses
-system.cpu1.numCycles                      5732918807                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                28026418                       # ITB inst accesses
+system.cpu1.itb.hits                         28023624                       # DTB hits
+system.cpu1.itb.misses                           2794                       # DTB misses
+system.cpu1.itb.accesses                     28026418                       # DTB accesses
+system.cpu1.numCycles                      5734097031                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   20503191                       # Number of instructions committed
-system.cpu1.committedOps                     24868380                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22184707                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1209330                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2571856                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22184707                       # number of integer instructions
-system.cpu1.num_fp_insts                         1792                       # number of float instructions
-system.cpu1.num_int_register_reads           39845208                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15444901                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            90439564                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            8859928                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      9245671                       # number of memory refs
-system.cpu1.num_load_insts                    4945342                       # Number of load instructions
-system.cpu1.num_store_insts                   4300329                       # Number of store instructions
-system.cpu1.num_idle_cycles              5671530100.732908                       # Number of idle cycles
-system.cpu1.num_busy_cycles              61388706.267092                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.010708                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.989292                       # Percentage of idle cycles
-system.cpu1.Branches                          3891928                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   67      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 16013514     63.30%     63.30% # Class of executed instruction
-system.cpu1.op_class::IntMult                   33536      0.13%     63.44% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4037      0.02%     63.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.45% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4945342     19.55%     83.00% # Class of executed instruction
-system.cpu1.op_class::MemWrite                4300329     17.00%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   27233120                       # Number of instructions committed
+system.cpu1.committedOps                     33143777                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             29468029                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  6988                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1518648                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3438745                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    29468029                       # number of integer instructions
+system.cpu1.num_fp_insts                         6988                       # number of float instructions
+system.cpu1.num_int_register_reads           53045981                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          20334319                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                5190                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1800                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           119969216                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           12226644                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     12358568                       # number of memory refs
+system.cpu1.num_load_insts                    6575418                       # Number of load instructions
+system.cpu1.num_store_insts                   5783150                       # Number of store instructions
+system.cpu1.num_idle_cycles              5655719559.150027                       # Number of idle cycles
+system.cpu1.num_busy_cycles              78377471.849973                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.013669                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.986331                       # Percentage of idle cycles
+system.cpu1.Branches                          5151142                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  168      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 21257809     63.16%     63.16% # Class of executed instruction
+system.cpu1.op_class::IntMult                   38403      0.11%     63.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4420      0.01%     63.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.28% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.28% # Class of executed instruction
+system.cpu1.op_class::MemRead                 6575418     19.54%     82.82% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5783150     17.18%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  25296825                       # Class of executed instruction
+system.cpu1.op_class::total                  33659368                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2733                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements           218952                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          479.963069                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            8650768                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           219309                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            39.445568                       # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce                    2818                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements           321673                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          481.284483                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11622088                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           322185                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            36.072716                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     104113347000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.963069                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.937428                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.937428                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          357                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           48                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.697266                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         18157371                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        18157371                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4461777                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4461777                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3918409                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3918409                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        64134                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        64134                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87180                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        87180                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79638                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79638                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      8380186                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         8380186                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      8444320                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        8444320                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       155208                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       155208                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       103786                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       103786                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34227                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        34227                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17933                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17933                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23205                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23205                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       258994                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        258994                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       293221                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       293221                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2219053526                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2219053526                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2269605832                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2269605832                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325236501                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    325236501                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    538183221                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    538183221                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1673500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1673500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4488659358                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4488659358                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4488659358                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4488659358                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4616985                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4616985                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4022195                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4022195                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        98361                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        98361                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105113                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       105113                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102843                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       102843                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      8639180                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      8639180                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      8737541                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      8737541                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.033617                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.033617                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025803                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.025803                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.347973                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.347973                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.170607                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.170607                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225635                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225635                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029979                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.029979                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033559                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.033559                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.284483                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.940009                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.940009                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         24380907                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        24380907                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      5961630                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        5961630                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5307193                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       5307193                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        82380                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        82380                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       110885                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total       110885                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       104150                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total       104150                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11268823                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11268823                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11351203                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11351203                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       210202                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       210202                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       138084                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       138084                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        48251                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        48251                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        19527                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        19527                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23870                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23870                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       348286                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        348286                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       396537                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       396537                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2787267513                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2787267513                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2672172287                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2672172287                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    339794001                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    339794001                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    550321118                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    550321118                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1627000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1627000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   5459439800                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   5459439800                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   5459439800                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   5459439800                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      6171832                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      6171832                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5445277                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5445277                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       130631                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       130631                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       130412                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       130412                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       128020                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       128020                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     11617109                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     11617109                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     11747740                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     11747740                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.034058                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.034058                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025358                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.025358                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.369369                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.369369                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.149733                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.149733                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.186455                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.186455                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029980                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.029980                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033754                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.033754                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1428,84 +1446,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       135060                       # number of writebacks
-system.cpu1.dcache.writebacks::total           135060                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          314                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data            1                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12325                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12325                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          315                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          315                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          315                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       154894                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       154894                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103785                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       103785                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33053                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        33053                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5608                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5608                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23205                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23205                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       258679                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       258679                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       291732                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       291732                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1899677974                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1899677974                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2055753168                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2055753168                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    496489496                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    496489496                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84032750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84032750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    490566779                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    490566779                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1599500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1599500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3955431142                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3955431142                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4451920638                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4451920638                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    961065499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    961065499                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    833382997                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    833382997                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1794448496                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1794448496                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033549                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033549                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025803                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025803                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.336038                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.336038                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.053352                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053352                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225635                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225635                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029943                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.029943                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033388                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033388                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       197265                       # number of writebacks
+system.cpu1.dcache.writebacks::total           197265                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          459                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          459                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13505                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13505                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          459                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          459                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          459                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          459                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       209743                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       209743                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       138084                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       138084                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        46648                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        46648                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         6022                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         6022                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23870                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23870                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       347827                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       347827                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       394475                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       394475                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2356483739                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2356483739                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2388185713                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2388185713                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    637646247                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    637646247                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87580250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87580250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    501268882                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    501268882                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1557000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1557000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4744669452                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4744669452                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5382315699                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5382315699                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    968585999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    968585999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    845308497                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    845308497                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1813894496                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1813894496                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033984                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033984                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025358                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025358                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.357097                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.357097                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.046177                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.046177                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.186455                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.186455                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029941                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029941                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033579                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033579                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1513,58 +1529,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           565004                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.690467                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           20318443                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           565516                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            35.929033                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           680772                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.691095                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           27342334                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           681284                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.133533                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     115083689500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.690467                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974005                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.974005                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.691095                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974006                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974006                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          110                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            5                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         42333437                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        42333437                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     20318443                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       20318443                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     20318443                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        20318443                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     20318443                       # number of overall hits
-system.cpu1.icache.overall_hits::total       20318443                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       565517                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       565517                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       565517                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        565517                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       565517                       # number of overall misses
-system.cpu1.icache.overall_misses::total       565517                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4683990281                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4683990281                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4683990281                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4683990281                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4683990281                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4683990281                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     20883960                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     20883960                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     20883960                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     20883960                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     20883960                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     20883960                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.027079                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.027079                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.027079                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.027079                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.027079                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.027079                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8282.669276                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8282.669276                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8282.669276                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8282.669276                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8282.669276                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8282.669276                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         56728523                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        56728523                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     27342334                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       27342334                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     27342334                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        27342334                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     27342334                       # number of overall hits
+system.cpu1.icache.overall_hits::total       27342334                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       681285                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       681285                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       681285                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        681285                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       681285                       # number of overall misses
+system.cpu1.icache.overall_misses::total       681285                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5656981010                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5656981010                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5656981010                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5656981010                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5656981010                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5656981010                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     28023619                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     28023619                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     28023619                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     28023619                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     28023619                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     28023619                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024311                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024311                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024311                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024311                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024311                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024311                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8303.398739                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8303.398739                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8303.398739                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8303.398739                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8303.398739                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8303.398739                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1573,356 +1589,361 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       565517                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       565517                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       565517                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       565517                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       565517                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       565517                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3835548219                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3835548219                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3835548219                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3835548219                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3835548219                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3835548219                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       681285                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       681285                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       681285                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       681285                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       681285                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       681285                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4634848490                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4634848490                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4634848490                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4634848490                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4634848490                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4634848490                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13880000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13880000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13880000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     13880000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027079                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027079                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027079                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6782.374746                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6782.374746                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6782.374746                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024311                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024311                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024311                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024311                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024311                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024311                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6803.097808                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6803.097808                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6803.097808                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  6803.097808                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6803.097808                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  6803.097808                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4611088                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        22954                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4468812                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          204                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      5735095                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        38649                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      5537320                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          267                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           20                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       119098                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       522488                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           19                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       158840                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       604377                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           85089                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15598.515375                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            830428                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs          100250                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.283571                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    2855976531500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4729.771122                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.150877                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.487977                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   867.406317                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1520.802657                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  8476.896425                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.288682                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000192                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000030                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.052942                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.092822                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.517389                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.952058                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9282                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5865                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           69                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1139                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         8074                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          273                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1132                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4460                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.566528                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.357971                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        16688806                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       16688806                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2996                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1704                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       559876                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       123244                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        687820                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       135060                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       135060                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1609                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1609                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          861                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          861                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        39179                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        39179                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2996                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1704                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       559876                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       162423                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         726999                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2996                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1704                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       559876                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       162423                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        726999                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          338                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5641                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        70311                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        76567                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29399                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29399                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22337                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22337                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33598                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        33598                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          338                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          277                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst         5641                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       103909                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       110165                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          338                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          277                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst         5641                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       103909                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       110165                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6952000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5546000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    192723218                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1546712890                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1751934108                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537154147                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    537154147                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    436854563                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    436854563                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1562500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1562500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1072389357                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1072389357                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6952000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5546000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    192723218                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   2619102247                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   2824323465                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6952000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5546000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    192723218                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   2619102247                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   2824323465                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3334                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1981                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       565517                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data       193555                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       764387                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       135060                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       135060                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31008                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31008                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23198                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23198                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        72777                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        72777                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3334                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1981                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       565517                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       266332                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3334                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1981                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       565517                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       266332                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       837164                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009975                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.363261                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.100168                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.948110                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.948110                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.962885                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962885                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.replacements          130093                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15612.463834                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1076740                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs          146334                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.358099                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  4806.943324                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.120223                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     1.343631                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   874.835505                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1500.703163                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  8425.517990                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.293393                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000190                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000082                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.053396                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.091596                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.514253                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.952909                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         7913                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         8324                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           47                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           90                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         2030                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4783                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          963                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2875                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4662                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          602                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.482971                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.508057                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        21325891                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       21325891                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         5234                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::cpu1.inst       672894                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data       186024                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        866845                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       197265                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       197265                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2024                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2024                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1217                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total         1217                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        69989                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        69989                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         5234                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2693                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       672894                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       256013                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         936834                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2693                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       672894                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       256013                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        936834                       # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          216                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst         8391                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data        76389                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        85257                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29955                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29955                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22648                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22648                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36116                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        36116                       # number of ReadExReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          261                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          216                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst         8391                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       112505                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       121373                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          261                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          216                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst         8391                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       112505                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       121373                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      5754999                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4668500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    255474477                       # number of ReadReq miss cycles
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+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    542491459                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    542491459                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    444517157                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    444517157                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1522000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1522000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1159011538                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1159011538                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      5754999                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4668500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    255474477                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   2861561194                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3127459170                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      5754999                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4668500                       # number of overall miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.data   2861561194                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         5495                       # number of ReadReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_accesses::total       952102                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       197265                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       197265                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31979                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        31979                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23865                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23865                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.047498                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.012316                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.291102                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.089546                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.936708                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.936708                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.949005                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.949005                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.461657                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.461657                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009975                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.390148                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.131593                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009975                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.390148                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.131593                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         1642                       # number of cycles access was blocked
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+system.cpu1.l2cache.blocked_cycles::no_mshrs         1081                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs              35                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              34                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    46.914286                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    31.794118                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        35198                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           35198                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          739                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          100                       # number of ReadReq MSHR hits
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-system.cpu1.l2cache.ReadExReq_mshr_hits::total          193                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          739                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          293                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          739                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          293                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1032                       # number of overall MSHR hits
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-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       119097                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       119097                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29399                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29399                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22337                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22337                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33405                       # number of ReadExReq MSHR misses
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-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          338                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          277                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4902                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4902                       # number of overall MSHR misses
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-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    143902025                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1053014200                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1205109225                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3247389638                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3247389638                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    430450689                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    430450689                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    306453691                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306453691                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1303500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1303500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    820460623                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    820460623                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4586000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    143902025                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1873474823                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2025569848                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4586000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3607000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    143902025                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1873474823                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total   5272959486                       # number of overall MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_hits::total         1331                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          387                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          387                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1186                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          532                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1718                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1186                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          532                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1718                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          261                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          216                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         7205                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        76244                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        83926                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       158839                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       158839                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29955                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29955                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22648                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22648                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35729                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        35729                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          261                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          216                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         7205                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       111973                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       119655                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          261                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          216                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         7205                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       111973                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       158839                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       278494                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      3927001                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3156500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    186017515                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1165742936                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1358843952                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   4336083136                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   4336083136                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    450926825                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    450926825                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    312179089                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    312179089                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1277000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1277000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    867144190                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    867144190                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      3927001                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3156500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    186017515                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2032887126                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2225988142                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      3927001                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3156500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    186017515                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2032887126                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   4336083136                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   6562071278                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12475500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    916023500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    928499000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    796472502                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    796472502                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    923111999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    935587499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    807820502                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    807820502                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12475500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1712496002                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1724971502                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.362744                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.099070                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1730932501                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1743408001                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.047498                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.074252                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.010576                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.290550                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.088148                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.948110                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.948110                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.962885                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962885                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.936708                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.936708                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.949005                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.949005                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.459005                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.459005                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.389048                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.130360                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.389048                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.336732                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.336732                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.047498                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.074252                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.010576                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.303847                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.113073                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.047498                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.074252                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.010576                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.303847                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.272623                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.263175                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       255400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       255400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1932,64 +1953,64 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1205511                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       816520                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         4921                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         4921                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       135060                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       171236                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        86319                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42477                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89729                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        90979                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        78176                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1131388                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       880635                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5306                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9255                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2026584                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     36193796                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     28781627                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7924                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          64996683                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     818999                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1762052                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.415245                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.492764                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq       1351518                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1008638                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         4998                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         4998                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       197265                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       224398                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        84264                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42890                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        91097                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           75                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq       123576                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp       111434                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1362924                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1150758                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8243                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        16496                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2538421                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     43602948                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     39320783                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11636                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        21980                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          82957347                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     826396                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      2054321                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.357816                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.479358                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5           1030369     58.48%     58.48% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            731683     41.52%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1319253     64.22%     64.22% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            735068     35.78%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1762052                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     658210715                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       2054321                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     864974439                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     89516500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     89802999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    848574281                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1022245510                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    438678337                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    593726174                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      3325000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      5334000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      5921000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     11001001                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31019                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31019                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59407                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           33                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59437                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              23213                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56642                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -2010,11 +2031,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107964                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107950                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180918                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71586                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -2035,11 +2056,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162847                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162833                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484103                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2484089                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40126000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2079,601 +2100,613 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326671825                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347096127                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84748000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84737000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36845580                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36842563                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36443                       # number of replacements
-system.iocache.tags.tagsinuse               14.446794                       # Cycle average of tags in use
+system.iocache.tags.replacements                36459                       # number of replacements
+system.iocache.tags.tagsinuse               14.453181                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36459                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         277163106000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.446794                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.902925                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.902925                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         277163175000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.453181                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.903324                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.903324                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328557                       # Number of tag accesses
-system.iocache.tags.data_accesses              328557                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses               328293                       # Number of tag accesses
+system.iocache.tags.data_accesses              328293                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ide          253                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              253                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide           33                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total           33                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          253                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               253                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          253                       # number of overall misses
 system.iocache.overall_misses::total              253                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31609377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31609377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31609377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31609377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31609377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31609377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     31619377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31619377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9617084187                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9617084187                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31619377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31619377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31619377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31619377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          253                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            253                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36257                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36257                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ide          253                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total             253                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ide          253                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total            253                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000910                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000910                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124938.249012                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124938.249012                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124938.249012                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124977.774704                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124977.774704                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124977.774704                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124977.774704                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124977.774704                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56586                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7227                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.829805                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36206                       # number of writebacks
+system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          253                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          253                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          253                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          253                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          253                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18452377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18452377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2250014028                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2250014028                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18452377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18452377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18452377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18452377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18462377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18462377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7733310313                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7733310313                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18462377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18462377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18462377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18462377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72973.822134                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72973.822134                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   132935                       # number of replacements
-system.l2c.tags.tagsinuse                64217.518730                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     488817                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   197475                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.475336                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   132552                       # number of replacements
+system.l2c.tags.tagsinuse                64217.240538                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     486427                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   197317                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.465206                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12771.193603                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     4.858844                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.037003                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1138.507599                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1415.888274                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.641656                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.007796                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      536.042723                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      904.271560                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8794.277876                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.194873                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   12673.098262                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     4.830088                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.037001                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1135.719993                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     1432.608438                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.654088                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.007784                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      545.091140                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      913.810052                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8789.608693                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.193376                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000074                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data       0.021605                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.589749                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000040                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008179                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.013798                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.134190                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.979882                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        44757                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        19776                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5076                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        39488                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1542                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        18030                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.682938                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.301758                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6143442                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6143442                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker          146                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker          155                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu0.data              29439                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       168037                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker           53                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker           44                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst               4112                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              10373                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        47653                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 270213                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          240423                       # number of Writeback hits
-system.l2c.Writeback_hits::total               240423                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            9633                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1000                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               10633                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           247                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           137                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               384                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4104                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total                 6670                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           146                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           155                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               10201                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               33543                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       168037                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.itb.walker            44                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                4112                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               12939                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher        47653                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  276883                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          146                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker          155                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              10201                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              33543                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       168037                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           53                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst               4112                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              12939                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher        47653                       # number of overall hits
-system.l2c.overall_hits::total                 276883                       # number of overall hits
+system.l2c.tags.occ_percent::cpu1.inst       0.008317                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1022::3         5031                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        39902                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         1352                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        18116                       # Occupied blocks per task id
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+system.l2c.ReadReq_hits::cpu0.itb.walker           80                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        75612                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 267683                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          239712                       # number of Writeback hits
+system.l2c.Writeback_hits::total               239712                       # number of Writeback hits
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+system.l2c.UpgradeReq_hits::total               10296                       # number of UpgradeReq hits
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+system.l2c.overall_hits::cpu1.l2cache.prefetcher        75612                       # number of overall hits
+system.l2c.overall_hits::total                 274257                       # number of overall hits
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 system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data             1400                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::total             12745                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          893                       # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total              11744                       # number of ReadExReq misses
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+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       102244                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              469547                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker           91                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           81                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          10740                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       283216                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          107                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker          108                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst           7208                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          27415                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       102244                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             469547                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.087912                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012346                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.286685                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.238558                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.510713                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.037383                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.009259                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.115289                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.083139                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.260475                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.406832                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.442988                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.801236                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.553571                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.793404                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.903958                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.859642                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.620896                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.662069                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.640175                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.087912                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.415912                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.087912                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.415912                       # miss rate for overall accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2280.861608                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1479.929855                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1441.707727                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1682.836040                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1584.333028                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377                       # average ReadExReq miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::total 98553.321604                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               370                       # number of cycles access was blocked
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+system.l2c.blocked_cycles::no_mshrs                 6                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
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 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     46.250000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs             3                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               99922                       # number of writebacks
-system.l2c.writebacks::total                    99922                       # number of writebacks
+system.l2c.writebacks::writebacks               99681                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
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 system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4191                       # number of UpgradeReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    476661000                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    476661000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8336984003                       # number of overall MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9143000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1526922000                       # number of overall MSHR uncacheable cycles
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.807359                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.545171                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.783333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.904196                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.850584                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.683951                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.637776                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.051948                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.160474                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::total      0.414055                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.053571                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.160474                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.414055                       # mshr miss rate for overall accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.801236                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.553571                       # mshr miss rate for UpgradeReq accesses
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 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196                       # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74894.283534                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70082.930580                       # average ReadReq mshr miss latency
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 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 86136.192391                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 86246.639722                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 86136.192391                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 86246.639722                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -2688,58 +2721,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              228475                       # Transaction distribution
-system.membus.trans_dist::ReadResp             228474                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31175                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31175                       # Transaction distribution
-system.membus.trans_dist::Writeback             99922                       # Transaction distribution
+system.membus.trans_dist::ReadReq              228161                       # Transaction distribution
+system.membus.trans_dist::ReadResp             228160                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31188                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31188                       # Transaction distribution
+system.membus.trans_dist::Writeback            135887                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            85905                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41202                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15112                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            85485                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41282                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15173                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28459                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            11563                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107964                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq             28446                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            11501                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107950                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678409                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       800961                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72716                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72716                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 873677                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162847                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       676793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       799389                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 908311                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162833                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29108                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18962472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19154495                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21473791                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           129134                       # Total snoops (count)
-system.membus.snoop_fanout::samples            475892                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18898536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19090661                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4636480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4636480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                23727141                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           129157                       # Total snoops (count)
+system.membus.snoop_fanout::samples            511174                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  475892    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  511174    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              475892                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88166996                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              511174                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88144997                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12082997                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12118496                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1515063497                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1838586997                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1971064197                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1967573382                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38584420                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38564437                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2772,44 +2805,44 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             633379                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            633359                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31175                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31175                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           240423                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           96357                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41586                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         137943                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           74                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            39964                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           39964                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1256968                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       399943                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1656911                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     37604672                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8289023                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               45893695                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          305031                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1043713                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.034956                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.183668                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq             630354                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            630338                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31188                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31188                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           239712                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           95586                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41643                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         137229                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           75                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           75                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            39856                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           39856                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1145062                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       504022                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1649084                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     33792786                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     11864019                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45656805                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          304478                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1039135                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.035103                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.184041                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1007229     96.50%     96.50% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36484      3.50%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1002658     96.49%     96.49% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36477      3.51%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1043713                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1520313197                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1039135                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1515175521                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy          1071000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2134327544                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1922628953                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         850356790                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1047459467                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 4e27b0ea0..5265a0ac0 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,123 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.902619                       # Number of seconds simulated
-sim_ticks                                2902619131000                       # Number of ticks simulated
-final_tick                               2902619131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.902845                       # Number of seconds simulated
+sim_ticks                                2902845442000                       # Number of ticks simulated
+final_tick                               2902845442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 783857                       # Simulator instruction rate (inst/s)
-host_op_rate                                   945096                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20223090080                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560080                       # Number of bytes of host memory used
-host_seconds                                   143.53                       # Real time elapsed on the host
-sim_insts                                   112507011                       # Number of instructions simulated
-sim_ops                                     135649580                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 666753                       # Simulator instruction rate (inst/s)
+host_op_rate                                   803907                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17201244826                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 558784                       # Number of bytes of host memory used
+host_seconds                                   168.76                       # Real time elapsed on the host
+sim_insts                                   112519801                       # Number of instructions simulated
+sim_ops                                     135665611                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1190564                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9003364                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1190500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8985828                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10195464                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1190564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1190564                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5259520                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10177864                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1190500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1190500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7575744                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7595380                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7593268                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27056                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141197                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27055                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140923                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168277                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           82180                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                168002                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118371                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122785                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122752                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               410169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3101807                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               410115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3095524                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3512505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          410169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             410169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1811991                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3506168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          410115                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             410115                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2609765                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6037                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          798705                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2616733                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1811991                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2615802                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2609765                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              410169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3107844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          799036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6129238                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        168277                       # Number of read requests accepted
-system.physmem.writeReqs                       122785                       # Number of write requests accepted
-system.physmem.readBursts                      168277                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     122785                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10758080                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7609472                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10195464                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7595380                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      182                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3868                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4505                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9709                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9253                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10215                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10266                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18988                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10225                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10580                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10353                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9698                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                9938                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9924                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8855                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9985                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10410                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9933                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9763                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7210                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6831                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8029                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7890                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7400                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7418                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7750                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7625                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7363                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7566                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7503                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6751                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7436                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7741                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7101                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              410115                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3101561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6121970                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168002                       # Number of read requests accepted
+system.physmem.writeReqs                       158976                       # Number of write requests accepted
+system.physmem.readBursts                      168002                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     158976                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10744064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9803776                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10177864                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9911604                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5765                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4503                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9689                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9233                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10196                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10261                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18984                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10217                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10550                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10349                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9691                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9930                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9906                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8846                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9937                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10409                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9928                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9750                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9383                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8873                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10202                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10003                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9293                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9372                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9902                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9747                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9662                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9936                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9764                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9057                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9756                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9847                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9332                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9055                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2902618754500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2902845065500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  158705                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  158430                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118404                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    167256                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       571                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 154595                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167074                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       244                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -162,157 +159,153 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6817                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6957                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58554                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      313.684599                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.640199                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.584074                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21469     36.67%     36.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14640     25.00%     61.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5516      9.42%     71.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3473      5.93%     77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2278      3.89%     80.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1576      2.69%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          999      1.71%     85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1064      1.82%     87.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7539     12.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58554                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5863                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.669452                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      558.899894                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5861     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8553                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    10886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    10725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6734                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      338.910027                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.312314                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     353.501529                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21458     35.39%     35.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14532     23.97%     59.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5550      9.15%     68.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3471      5.72%     74.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2318      3.82%     78.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1576      2.60%     80.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1018      1.68%     82.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1077      1.78%     84.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9629     15.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60629                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6199                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.078561                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      543.579220                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6197     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5863                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5863                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.279379                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.638132                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.466375                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5064     86.37%     86.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              42      0.72%     87.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              33      0.56%     87.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             216      3.68%     91.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             215      3.67%     95.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              12      0.20%     95.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              16      0.27%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.12%     95.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              25      0.43%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.05%     96.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.10%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.07%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             164      2.80%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               2      0.03%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.22%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               5      0.09%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.05%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.05%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.14%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5863                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1491102500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4642883750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    840475000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8870.59                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6199                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6199                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.711082                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.355367                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.633562                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            5127     82.71%     82.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             245      3.95%     86.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             162      2.61%     89.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              57      0.92%     90.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             142      2.29%     92.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              31      0.50%     92.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              44      0.71%     93.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              53      0.85%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              77      1.24%     95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              20      0.32%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            101      1.63%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            12      0.19%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            30      0.48%     98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            13      0.21%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            38      0.61%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            11      0.18%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            15      0.24%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             3      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             3      0.05%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.03%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             3      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6199                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1496514000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4644189000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    839380000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8914.40                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27620.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27664.40                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.70                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.38                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.62                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.41                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     138436                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     90002                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.36                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9972510.17                       # Average gap between requests
-system.physmem.pageHitRate                      79.59                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2755210874500                       # Time in different power states
-system.physmem.memoryStateTime::REF       96924620000                       # Time in different power states
+system.physmem.avgWrQLen                        27.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138272                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    122158                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8877799.32                       # Average gap between requests
+system.physmem.pageHitRate                      81.11                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2755332461750                       # Time in different power states
+system.physmem.memoryStateTime::REF       96932160000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       50483546000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       50580729750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 226731960                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 215936280                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 123712875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 117822375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                698794200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                612339000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               389791440                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               380667600                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          189584556720                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          189584556720                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           86730297120                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           85558991580                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1665488607000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1666516068000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1943242491315                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1942986381555                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.480387                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.392153                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 234216360                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 224138880                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 127796625                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 122298000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                697936200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                611488800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               497502000                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               495130320                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          189599304960                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          189599304960                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0           86744243025                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1           85632450615                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          1665611854500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          1666587111000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            1943512853670                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            1943271922575                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             669.521448                       # Core power per rank (mW)
+system.physmem.averagePower::1             669.438449                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -355,25 +348,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24532671                       # DTB read hits
-system.cpu.dtb.read_misses                       8148                       # DTB read misses
-system.cpu.dtb.write_hits                    19614515                       # DTB write hits
+system.cpu.dtb.read_hits                     24536392                       # DTB read hits
+system.cpu.dtb.read_misses                       8144                       # DTB read misses
+system.cpu.dtb.write_hits                    19617454                       # DTB write hits
 system.cpu.dtb.write_misses                      1410                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4272                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     4273                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                   1630                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24540819                       # DTB read accesses
-system.cpu.dtb.write_accesses                19615925                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24544536                       # DTB read accesses
+system.cpu.dtb.write_accesses                19618864                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44147186                       # DTB hits
-system.cpu.dtb.misses                            9558                       # DTB misses
-system.cpu.dtb.accesses                      44156744                       # DTB accesses
+system.cpu.dtb.hits                          44153846                       # DTB hits
+system.cpu.dtb.misses                            9554                       # DTB misses
+system.cpu.dtb.accesses                      44163400                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -395,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    115605918                       # ITB inst hits
+system.cpu.itb.inst_hits                    115618887                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -412,38 +405,38 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                115610680                       # ITB inst accesses
-system.cpu.itb.hits                         115605918                       # DTB hits
+system.cpu.itb.inst_accesses                115623649                       # ITB inst accesses
+system.cpu.itb.hits                         115618887                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     115610680                       # DTB accesses
-system.cpu.numCycles                       5805238262                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     115623649                       # DTB accesses
+system.cpu.numCycles                       5805690884                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112507011                       # Number of instructions committed
-system.cpu.committedOps                     135649580                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             119948946                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
-system.cpu.num_func_calls                     9898964                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15236406                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    119948946                       # number of integer instructions
-system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218165471                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           82686622                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
+system.cpu.committedInsts                   112519801                       # Number of instructions committed
+system.cpu.committedOps                     135665611                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119963928                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11290                       # Number of float alu accesses
+system.cpu.num_func_calls                     9899743                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15237612                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119963928                       # number of integer instructions
+system.cpu.num_fp_insts                         11290                       # number of float instructions
+system.cpu.num_int_register_reads           218192496                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82697523                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                 8578                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            489970666                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            51914345                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      45428250                       # number of memory refs
-system.cpu.num_load_insts                    24855398                       # Number of load instructions
-system.cpu.num_store_insts                   20572852                       # Number of store instructions
-system.cpu.num_idle_cycles               5386458042.024144                       # Number of idle cycles
-system.cpu.num_busy_cycles               418780219.975856                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.072138                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.927862                       # Percentage of idle cycles
-system.cpu.Branches                          25929462                       # Number of branches fetched
+system.cpu.num_cc_register_reads            490031044                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51919223                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45435185                       # number of memory refs
+system.cpu.num_load_insts                    24859277                       # Number of load instructions
+system.cpu.num_store_insts                   20575908                       # Number of store instructions
+system.cpu.num_idle_cycles               5386811452.570145                       # Number of idle cycles
+system.cpu.num_busy_cycles               418879431.429856                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.072150                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.927850                       # Percentage of idle cycles
+system.cpu.Branches                          25931479                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  93218062     67.17%     67.18% # Class of executed instruction
-system.cpu.op_class::IntMult                   114523      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93227451     67.17%     67.17% # Class of executed instruction
+system.cpu.op_class::IntMult                   114534      0.08%     67.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
@@ -467,24 +460,24 @@ system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Cl
 system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               8475      0.01%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8511      0.01%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::MemRead                 24855398     17.91%     85.18% # Class of executed instruction
-system.cpu.op_class::MemWrite                20572852     14.82%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 24859277     17.91%     85.17% # Class of executed instruction
+system.cpu.op_class::MemWrite                20575908     14.83%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  138771647                       # Class of executed instruction
+system.cpu.op_class::total                  138788018                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3032                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements            822746                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.850534                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43252602                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            823258                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             52.538332                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                     3037                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements            823273                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.850546                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            43258722                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            823785                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.512151                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         876905250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.850534                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.850546                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999708                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999708                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -493,88 +486,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          368
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         177194888                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        177194888                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23122389                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23122389                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18831358                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18831358                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       392121                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        392121                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443546                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443546                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460444                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460444                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41953747                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41953747                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42345868                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42345868                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       402166                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        402166                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       299026                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       299026                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       119155                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       119155                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22691                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22691                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         177222055                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177222055                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23125535                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23125535                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18834160                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18834160                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392158                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392158                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443620                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443620                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460509                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460509                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41959695                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41959695                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42351853                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42351853                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       402606                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        402606                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       299098                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       299098                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       119172                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       119172                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22698                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22698                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       701192                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         701192                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       820347                       # number of overall misses
-system.cpu.dcache.overall_misses::total        820347                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5900442000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5900442000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11658351003                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11658351003                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    279152000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    279152000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        53002                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        53002                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  17558793003                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  17558793003                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  17558793003                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  17558793003                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23524555                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23524555                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19130384                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19130384                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511276                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511276                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466237                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466237                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460446                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460446                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42654939                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42654939                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43166215                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43166215                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017096                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.017096                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015631                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015631                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.233054                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.233054                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048668                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048668                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data       701704                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         701704                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       820876                       # number of overall misses
+system.cpu.dcache.overall_misses::total        820876                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5915644250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5915644250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11659723253                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11659723253                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    280150250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    280150250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       150000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       150000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  17575367503                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  17575367503                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  17575367503                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  17575367503                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23528141                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23528141                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19133258                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19133258                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511330                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511330                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460511                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460511                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42661399                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42661399                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43172729                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43172729                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017112                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.017112                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015632                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015632                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.233063                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.233063                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048675                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048675                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016439                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016439                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.019004                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.019004                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25041.348166                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21404.104608                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016448                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016448                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.019014                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.019014                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14693.383233                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14693.383233                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38982.952922                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38982.952922                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12342.508150                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12342.508150                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        75000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25046.697045                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21410.502321                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
@@ -583,78 +576,78 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     1.757576
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       686230                       # number of writebacks
-system.cpu.dcache.writebacks::total            686230                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          627                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          627                       # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14222                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14222                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          627                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          627                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          627                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          627                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       401539                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       401539                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299026                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299026                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       117004                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       117004                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8469                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8469                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       686473                       # number of writebacks
+system.cpu.dcache.writebacks::total            686473                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          636                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          636                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14226                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14226                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          636                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          636                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          636                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          636                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       401970                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       401970                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299098                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299098                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       117021                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       117021                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8472                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8472                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       700565                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       700565                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       817569                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       817569                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5083326500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5083326500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11002800997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11002800997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1411190000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1411190000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data     99471250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total     99471250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        48998                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        48998                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16086127497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16086127497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17497317497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17497317497                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5791402750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5791402750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4429678000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4429678000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10221080750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10221080750                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017069                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017069                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015631                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015631                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228847                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228847                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018165                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018165                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       701068                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       701068                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       818089                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       818089                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5096620250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5096620250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11004051747                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11004051747                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1414370750                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1414370750                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data     99646250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total     99646250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       146000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16100671997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16100671997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17515042747                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17515042747                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5791399500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5791399500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4429678500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4429678500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10221078000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10221078000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017085                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017085                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015632                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015632                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228856                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228856                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018168                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018168                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016424                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016424                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018940                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.018940                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016433                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016433                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018949                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.018949                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        73000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -662,13 +655,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1699818                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.781939                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           113905582                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1700330                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             66.990280                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1700967                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.782035                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113917402                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1701479                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             66.951988                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       25181626250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.781939                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.782035                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997621                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.997621                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -677,44 +670,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          195
 system.cpu.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         117306254                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        117306254                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    113905582                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113905582                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     113905582                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        113905582                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    113905582                       # number of overall hits
-system.cpu.icache.overall_hits::total       113905582                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1700336                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1700336                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1700336                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1700336                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1700336                       # number of overall misses
-system.cpu.icache.overall_misses::total       1700336                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  23242723500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  23242723500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  23242723500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  23242723500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  23242723500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  23242723500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    115605918                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    115605918                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    115605918                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    115605918                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    115605918                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    115605918                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014708                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014708                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014708                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014708                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014708                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014708                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13669.488560                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13669.488560                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         117320372                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        117320372                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    113917402                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       113917402                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     113917402                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        113917402                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total       113917402                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1701485                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1701485                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total        1701485                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1701485                       # number of overall misses
+system.cpu.icache.overall_misses::total       1701485                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  23258305750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  23258305750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  23258305750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  23258305750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  23258305750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  23258305750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    115618887                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    115618887                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    115618887                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    115618887                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    115618887                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    115618887                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014716                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014716                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014716                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014716                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014716                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014716                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.415687                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13669.415687                       # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::total 13669.415687                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -723,196 +716,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_miss_latency::total  19835501500                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.Writeback_accesses::writebacks       686473                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       296284                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7104                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3702                       # number of demand (read+write) accesses
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-system.cpu.l2cache.demand_accesses::total      2534414                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7104                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000985                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000540                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010609                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991612                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991612                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991600                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.439561                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.439561                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000985                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000540                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000985                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857                       # average ReadReq miss latency
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 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72753.062808                       # average ReadReq miss latency
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-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73793.214061                       # average ReadReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   172.114748                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        23499                       # average SCUpgradeReq miss latency
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 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72753.062808                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69516.566259                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69880.954024                       # average overall miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69599.137210                       # average overall miss latency
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 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72753.062808                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69516.566259                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69880.954024                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72784.742239                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69599.137210                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69957.714120                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -921,100 +914,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        82180                       # number of writebacks
-system.cpu.l2cache.writebacks::total            82180                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        82181                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        18039                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        18040                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        12191                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2719                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2719                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of SCUpgradeReq MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
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 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    474215000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5385932000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5860147000                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4098166000                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    474215000                       # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000540                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010609                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991612                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9484091000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9958306000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001003                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010603                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.023113                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013503                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991600                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.439561                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.439561                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000540                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010609                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172995                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063318                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000985                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000540                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010609                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172995                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063318                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.439466                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.439466                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001003                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010603                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172890                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063283                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001003                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010603                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172890                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063283                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1024,59 +1017,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2294825                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2294810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2296418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2296403                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27618                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       686230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2742                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       686473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2738                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2744                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296284                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296284                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3418692                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2456073                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12917                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24956                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5912638                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108856056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96806921                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        28416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205706201                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       52963                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3276132                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.011129                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.104904                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2740                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296360                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296360                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3420989                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2457362                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12875                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24821                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5916047                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108929528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96856201                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          205828273                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       53126                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3278039                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.011122                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.104872                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            3239673     98.89%     98.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6              36459      1.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3241581     98.89%     98.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6              36458      1.11%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3276132                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2353772500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3278039                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2354969500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       328500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2564911000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2566643750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1311851755                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1312602003                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       9215000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      17852250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      17845000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59038                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -1167,42 +1161,44 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           326584349                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347056142                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36805009                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36804505                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.133398                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.134557                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         298397241000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.133398                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.070837                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.070837                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         298397320000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.134557                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.070910                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.070910                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28038377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28038377                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28038377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28038377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28038377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28038377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28034377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28034377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9588161260                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9588161260                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28034377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28034377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28034377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28034377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1213,104 +1209,114 @@ system.iocache.overall_accesses::realview.ide          234
 system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119822.123932                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119822.123932                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119822.123932                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119822.123932                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119822.123932                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119805.029915                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119805.029915                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119805.029915                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         55275                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7147                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.734014                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     15869377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     15869377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2206856981                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2206856981                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     15869377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     15869377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     15869377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     15869377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     15865377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     15865377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7704503270                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7704503270                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     15865377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     15865377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     15865377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     15865377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67817.850427                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67817.850427                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               70649                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70649                       # Transaction distribution
+system.membus.trans_dist::ReadReq               70650                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70650                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27618                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27618                       # Transaction distribution
-system.membus.trans_dist::Writeback             82180                       # Transaction distribution
+system.membus.trans_dist::Writeback            118371                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4503                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4505                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            128451                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           128451                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            128452                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           128452                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       436476                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       544158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 616855                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       436202                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       543884                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 652771                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15471548                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15635009                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17954305                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              219                       # Total snoops (count)
-system.membus.snoop_fanout::samples            281834                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15454012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15617473                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20252929                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              498                       # Total snoops (count)
+system.membus.snoop_fanout::samples            318026                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  281834    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  318026    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              281834                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            86774000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              318026                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            86773500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1752500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1756500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1264017500                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1594856995                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1589715500                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         1594842247                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38339991                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38335495                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index cdf4d3024..b2b55eb3a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,76 +1,73 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783854                       # Number of seconds simulated
-sim_ticks                                2783854461500                       # Number of ticks simulated
-final_tick                               2783854461500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783867                       # Number of seconds simulated
+sim_ticks                                2783867165000                       # Number of ticks simulated
+final_tick                               2783867165000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1108552                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1349484                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            21615280295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 562164                       # Number of bytes of host memory used
-host_seconds                                   128.79                       # Real time elapsed on the host
-sim_insts                                   142771592                       # Number of instructions simulated
-sim_ops                                     173801445                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1108011                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1348825                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            21604583679                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 560868                       # Number of bytes of host memory used
+host_seconds                                   128.86                       # Real time elapsed on the host
+sim_insts                                   142773109                       # Number of instructions simulated
+sim_ops                                     173803334                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           726948                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4668256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           728420                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4660384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           484032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5677316                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           482432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5667588                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11558024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       726948                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       484032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210980                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6521152                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11540296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       728420                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       482432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1210852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8837248                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8857012                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8854772                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             19812                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73460                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             19835                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73337                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7563                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             88709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7538                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             88557                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189567                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          101893                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                189290                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138082                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142498                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142463                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           115                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              261130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1676904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              261658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1674068                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              173871                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2039372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              173296                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2035869                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4151806                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         261130                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         173871                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             435001                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2342490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4145419                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         261658                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         173296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             434953                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3174450                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6292                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          832779                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3181564                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2342490                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3180745                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3174450                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          115                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             261130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1683196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             261658                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1680360                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             173871                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2039375                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          833124                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7333370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             173296                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2035872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7326164                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -113,25 +110,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    15997075                       # DTB read hits
-system.cpu0.dtb.read_misses                      4808                       # DTB read misses
-system.cpu0.dtb.write_hits                   11281657                       # DTB write hits
-system.cpu0.dtb.write_misses                      898                       # DTB write misses
+system.cpu0.dtb.read_hits                    15994592                       # DTB read hits
+system.cpu0.dtb.read_misses                      4787                       # DTB read misses
+system.cpu0.dtb.write_hits                   11285776                       # DTB write hits
+system.cpu0.dtb.write_misses                      895                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        2813                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     394                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3234                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3233                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   770                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   774                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      202                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16001883                       # DTB read accesses
-system.cpu0.dtb.write_accesses               11282555                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      200                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                15999379                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11286671                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         27278732                       # DTB hits
-system.cpu0.dtb.misses                           5706                       # DTB misses
-system.cpu0.dtb.accesses                     27284438                       # DTB accesses
+system.cpu0.dtb.hits                         27280368                       # DTB hits
+system.cpu0.dtb.misses                           5682                       # DTB misses
+system.cpu0.dtb.accesses                     27286050                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -153,189 +150,189 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    74797961                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2591                       # ITB inst misses
+system.cpu0.itb.inst_hits                    74779253                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2611                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        2813                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     394                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1908                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1917                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                74800552                       # ITB inst accesses
-system.cpu0.itb.hits                         74797961                       # DTB hits
-system.cpu0.itb.misses                           2591                       # DTB misses
-system.cpu0.itb.accesses                     74800552                       # DTB accesses
-system.cpu0.numCycles                      5536444794                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74781864                       # ITB inst accesses
+system.cpu0.itb.hits                         74779253                       # DTB hits
+system.cpu0.itb.misses                           2611                       # DTB misses
+system.cpu0.itb.accesses                     74781864                       # DTB accesses
+system.cpu0.numCycles                      5536444795                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72639396                       # Number of instructions committed
-system.cpu0.committedOps                     87981758                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             77492054                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5289                       # Number of float alu accesses
-system.cpu0.num_func_calls                    8694368                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      9459714                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    77492054                       # number of integer instructions
-system.cpu0.num_fp_insts                         5289                       # number of float instructions
-system.cpu0.num_int_register_reads          144071276                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          54447497                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4067                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           268879516                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           31833951                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     27909687                       # number of memory refs
-system.cpu0.num_load_insts                   16164649                       # Number of load instructions
-system.cpu0.num_store_insts                  11745038                       # Number of store instructions
-system.cpu0.num_idle_cycles              5353616424.336780                       # Number of idle cycles
-system.cpu0.num_busy_cycles              182828369.663220                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.033023                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.966977                       # Percentage of idle cycles
-system.cpu0.Branches                         18600789                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2188      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 61776684     68.83%     68.83% # Class of executed instruction
-system.cpu0.op_class::IntMult                   59679      0.07%     68.90% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4414      0.00%     68.90% # Class of executed instruction
+system.cpu0.committedInsts                   72626511                       # Number of instructions committed
+system.cpu0.committedOps                     87972361                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             77485845                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5272                       # Number of float alu accesses
+system.cpu0.num_func_calls                    8692455                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      9458284                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    77485845                       # number of integer instructions
+system.cpu0.num_fp_insts                         5272                       # number of float instructions
+system.cpu0.num_int_register_reads          144065543                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          54441741                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4114                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1160                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           268855206                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           31825195                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     27911692                       # number of memory refs
+system.cpu0.num_load_insts                   16162187                       # Number of load instructions
+system.cpu0.num_store_insts                  11749505                       # Number of store instructions
+system.cpu0.num_idle_cycles              5353607103.050808                       # Number of idle cycles
+system.cpu0.num_busy_cycles              182837691.949192                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.033024                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.966976                       # Percentage of idle cycles
+system.cpu0.Branches                         18597060                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2189      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 61764761     68.82%     68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59661      0.07%     68.89% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.89% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4406      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::MemRead                16164649     18.01%     86.91% # Class of executed instruction
-system.cpu0.op_class::MemWrite               11745038     13.09%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                16162187     18.01%     86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11749505     13.09%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  89752652                       # Class of executed instruction
+system.cpu0.op_class::total                  89742709                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3080                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           819395                       # number of replacements
+system.cpu0.kern.inst.quiesce                    3083                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements           819403                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997174                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           53783754                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           819907                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            65.597384                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           53784478                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           819915                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            65.597627                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.830585                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    36.166589                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929357                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.070638                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.821680                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    36.175494                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929339                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.070655                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        219234631                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       219234631                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15305258                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     14823504                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       30128762                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     10894595                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     11445159                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      22339754                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       185755                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       209287                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       395042                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       234989                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       222327                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       457316                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236688                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223434                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     26199853                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     26268663                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        52468516                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     26385608                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     26477950                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       52863558                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       197451                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       198871                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       396322                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       137556                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       164107                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       301663                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54345                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        61720                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       116065                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4663                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3966                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        219237567                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       219237567                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15302739                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     14826353                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       30129092                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     10898468                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     11441639                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      22340107                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186053                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       209002                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       395055                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       235062                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       222268                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       457330                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236768                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223368                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     26201207                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     26267992                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        52469199                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     26387260                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     26476994                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       52864254                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       197067                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       199240                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       396307                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       137729                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       163949                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54389                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        61684                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       116073                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4662                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3967                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         8629                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       335007                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       362978                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data       334796                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       363189                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total        697985                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       389352                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       424698                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       814050                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15502709                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     15022375                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     30525084                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     11032151                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     11609266                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     22641417                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       240100                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       271007                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       511107                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239652                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       226293                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236688                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223436                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     26534860                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     26631641                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     53166501                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     26774960                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     26902648                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     53677608                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.012737                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013238                       # miss rate for ReadReq accesses
+system.cpu0.dcache.overall_misses::cpu0.data       389185                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       424873                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       814058                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     15499806                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     15025593                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     30525399                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     11036197                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     11605588                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     22641785                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       240442                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       270686                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       511128                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239724                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       226235                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236768                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223370                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     26536003                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     26631181                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     53167184                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     26776445                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     26901867                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     53678312                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.012714                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013260                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.012983                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012469                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014136                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012480                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014127                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.226343                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227743                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.227086                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.019457                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.017526                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.226204                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227880                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.227092                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.019447                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.017535                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.018519                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000009                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.012625                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013630                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.012617                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013638                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.013128                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.014542                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015786                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.015166                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.014535                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015793                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.015165                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -344,19 +341,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       682260                       # number of writebacks
-system.cpu0.dcache.writebacks::total           682260                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       682284                       # number of writebacks
+system.cpu0.dcache.writebacks::total           682284                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1699006                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.663679                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          145341690                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1699518                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            85.519359                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1699220                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.663681                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          145342961                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1699732                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            85.509340                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   455.121641                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    56.542038                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.888909                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.110434                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   455.127365                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    56.536315                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.888921                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.110422                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
@@ -364,44 +361,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        148740738                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       148740738                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     73955769                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     71385921                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      145341690                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     73955769                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     71385921                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       145341690                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     73955769                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     71385921                       # number of overall hits
-system.cpu0.icache.overall_hits::total      145341690                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       844069                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       855455                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1699524                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       844069                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       855455                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1699524                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       844069                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       855455                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1699524                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     74799838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     72241376                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    147041214                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     74799838                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     72241376                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    147041214                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     74799838                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     72241376                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    147041214                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011284                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011842                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011284                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011842                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011284                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011842                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        148742437                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       148742437                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     73936562                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     71406399                       # number of ReadReq hits
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+system.cpu0.icache.demand_hits::cpu0.inst     73936562                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::total       145342961                       # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu1.inst     71406399                       # number of overall hits
+system.cpu0.icache.overall_hits::total      145342961                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       844577                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       855161                       # number of ReadReq misses
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+system.cpu0.icache.demand_misses::cpu0.inst       844577                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       855161                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu0.inst       844577                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       855161                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1699738                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74781139                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     72261560                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    147042699                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74781139                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     72261560                       # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::cpu0.inst     74781139                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     72261560                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    147042699                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011294                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011834                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011294                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011834                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011294                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011834                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -434,25 +431,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    15527184                       # DTB read hits
-system.cpu1.dtb.read_misses                      5393                       # DTB read misses
-system.cpu1.dtb.write_hits                   11842180                       # DTB write hits
-system.cpu1.dtb.write_misses                      794                       # DTB write misses
+system.cpu1.dtb.read_hits                    15530019                       # DTB read hits
+system.cpu1.dtb.read_misses                      5412                       # DTB read misses
+system.cpu1.dtb.write_hits                   11838449                       # DTB write hits
+system.cpu1.dtb.write_misses                      791                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2817                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     523                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3187                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    3183                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   922                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   911                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      243                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                15532577                       # DTB read accesses
-system.cpu1.dtb.write_accesses               11842974                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      245                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                15535431                       # DTB read accesses
+system.cpu1.dtb.write_accesses               11839240                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         27369364                       # DTB hits
-system.cpu1.dtb.misses                           6187                       # DTB misses
-system.cpu1.dtb.accesses                     27375551                       # DTB accesses
+system.cpu1.dtb.hits                         27368468                       # DTB hits
+system.cpu1.dtb.misses                           6203                       # DTB misses
+system.cpu1.dtb.accesses                     27374671                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -474,87 +471,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    72239267                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3050                       # ITB inst misses
+system.cpu1.itb.inst_hits                    72259450                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3040                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        2817                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     523                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2020                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2021                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                72242317                       # ITB inst accesses
-system.cpu1.itb.hits                         72239267                       # DTB hits
-system.cpu1.itb.misses                           3050                       # DTB misses
-system.cpu1.itb.accesses                     72242317                       # DTB accesses
-system.cpu1.numCycles                        88015463                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                72262490                       # ITB inst accesses
+system.cpu1.itb.hits                         72259450                       # DTB hits
+system.cpu1.itb.misses                           3040                       # DTB misses
+system.cpu1.itb.accesses                     72262490                       # DTB accesses
+system.cpu1.numCycles                        88040872                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   70132196                       # Number of instructions committed
-system.cpu1.committedOps                     85819687                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             75669045                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  6195                       # Number of float alu accesses
-system.cpu1.num_func_calls                    8179506                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      9270587                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    75669045                       # number of integer instructions
-system.cpu1.num_fp_insts                         6195                       # number of float instructions
-system.cpu1.num_int_register_reads          140985974                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          52730811                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4705                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           261969583                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           30530010                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     28028916                       # number of memory refs
-system.cpu1.num_load_insts                   15690946                       # Number of load instructions
-system.cpu1.num_store_insts                  12337970                       # Number of store instructions
-system.cpu1.num_idle_cycles              85360794.411583                       # Number of idle cycles
-system.cpu1.num_busy_cycles              2654668.588417                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030161                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969839                       # Percentage of idle cycles
-system.cpu1.Branches                         17796134                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                  149      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 59375218     67.88%     67.88% # Class of executed instruction
-system.cpu1.op_class::IntMult                   57194      0.07%     67.95% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4155      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.95% # Class of executed instruction
-system.cpu1.op_class::MemRead                15690946     17.94%     85.89% # Class of executed instruction
-system.cpu1.op_class::MemWrite               12337970     14.11%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   70146598                       # Number of instructions committed
+system.cpu1.committedOps                     85830973                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             75676981                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  6212                       # Number of float alu accesses
+system.cpu1.num_func_calls                    8181424                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      9272106                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    75676981                       # number of integer instructions
+system.cpu1.num_fp_insts                         6212                       # number of float instructions
+system.cpu1.num_int_register_reads          140994581                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          52737823                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4658                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1556                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           261999475                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           30539263                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     28027673                       # number of memory refs
+system.cpu1.num_load_insts                   15693775                       # Number of load instructions
+system.cpu1.num_store_insts                  12333898                       # Number of store instructions
+system.cpu1.num_idle_cycles              85385179.520823                       # Number of idle cycles
+system.cpu1.num_busy_cycles              2655692.479177                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030164                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969836                       # Percentage of idle cycles
+system.cpu1.Branches                         17799968                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  148      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 59388214     67.89%     67.89% # Class of executed instruction
+system.cpu1.op_class::IntMult                   57231      0.07%     67.96% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4163      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.96% # Class of executed instruction
+system.cpu1.op_class::MemRead                15693775     17.94%     85.90% # Class of executed instruction
+system.cpu1.op_class::MemWrite               12333898     14.10%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  87465632                       # Class of executed instruction
+system.cpu1.op_class::total                  87477429                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iobus.trans_dist::ReadReq                30171                       # Transaction distribution
@@ -613,23 +610,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480255                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909893                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909962                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909893                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.909962                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          240                       # number of overall misses
@@ -644,6 +641,8 @@ system.iocache.overall_accesses::realview.ide          240
 system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
@@ -654,31 +653,33 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      36224                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   110021                       # number of replacements
-system.l2c.tags.tagsinuse                65155.314991                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2731075                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                65155.309065                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2731330                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   175302                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    15.579258                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                    15.580712                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48893.450285                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924325                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   48893.434420                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924326                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5044.246320                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4729.238679                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5044.359026                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4729.332054                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.978702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4020.302070                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2464.174515                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4020.194257                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2464.086185                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.746055                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.076969                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.072162                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.076971                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.072164                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061345                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037600                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061343                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.037599                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.994191                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65277                       # Occupied blocks per task id
@@ -690,144 +691,144 @@ system.l2c.tags.age_task_id_blocks_1024::3        10700                       #
 system.l2c.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.996048                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26229756                       # Number of tag accesses
-system.l2c.tags.data_accesses                26229756                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4719                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2286                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::total                2201051                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          682260                       # number of Writeback hits
-system.l2c.Writeback_hits::total               682260                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              16                       # number of UpgradeReq hits
+system.l2c.tags.tag_accesses                 26231923                       # Number of tag accesses
+system.l2c.tags.data_accesses                26231923                       # Number of data accesses
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 system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            72325                       # number of ReadExReq hits
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 system.l2c.ReadReq_misses::cpu0.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
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 system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
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 system.l2c.ReadReq_misses::total                33895                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data          1249                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data          1479                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2728                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63970                       # number of ReadExReq misses
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 system.l2c.ReadExReq_misses::total             147864                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
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 system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
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 system.l2c.demand_misses::total                181759                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
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 system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
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 system.l2c.overall_misses::total               181759                       # number of overall misses
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 system.l2c.UpgradeReq_accesses::total            2756                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
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 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for ReadReq accesses
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 system.l2c.UpgradeReq_miss_rate::total       0.989840                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
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 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for demand accesses
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 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.012789                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.187700                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008841                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.209924                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.071732                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.012811                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.187814                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008815                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.209807                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.071725                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -836,14 +837,14 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              101893                       # number of writebacks
-system.l2c.writebacks::total                   101893                       # number of writebacks
+system.l2c.writebacks::writebacks              101892                       # number of writebacks
+system.l2c.writebacks::total                   101892                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               74229                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74229                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27560                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27560                       # Transaction distribution
-system.membus.trans_dist::Writeback            101893                       # Transaction distribution
+system.membus.trans_dist::Writeback            138082                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
@@ -854,31 +855,31 @@ system.membus.trans_dist::ReadExResp           146085                       # Tr
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105446                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       498777                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       606179                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 679107                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       498776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       606178                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 715296                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159103                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18095740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18258755                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2333696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20592451                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18095676                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18258691                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22908547                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            322846                       # Request fanout histogram
+system.membus.snoop_fanout::samples            359035                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  322846    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  359035    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              322846                       # Request fanout histogram
+system.membus.snoop_fanout::total              359035                       # Request fanout histogram
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -910,41 +911,41 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2291800                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2291800                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2291995                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2291995                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27560                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27560                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           682260                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           682284                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2756                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2758                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           298907                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          298907                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3417092                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2444886                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20766                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41566                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5924310                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108805624                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96322507                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41532                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83132                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              205252795                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           36632                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3272095                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.011144                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.104975                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadExReq           298922                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          298922                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3417520                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2444926                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20800                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41508                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5924754                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108819320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96324555                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83016                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205268491                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           36631                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3272329                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.011143                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.104971                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3235631     98.89%     98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3235865     98.89%     98.89% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                  36464      1.11%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3272095                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            3272329                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 27931ceba..818a22f67 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -1,80 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.256536                       # Number of seconds simulated
-sim_ticks                                47256535568000                       # Number of ticks simulated
-final_tick                               47256535568000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.177080                       # Number of seconds simulated
+sim_ticks                                47177080006500                       # Number of ticks simulated
+final_tick                               47177080006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1272324                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1496823                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            61628014219                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 661604                       # Number of bytes of host memory used
-host_seconds                                   766.80                       # Real time elapsed on the host
-sim_insts                                   975621413                       # Number of instructions simulated
-sim_ops                                    1147767763                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1024538                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1205255                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            49483118923                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 669884                       # Number of bytes of host memory used
+host_seconds                                   953.40                       # Real time elapsed on the host
+sim_insts                                   976792036                       # Number of instructions simulated
+sim_ops                                    1149086878                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        442560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       277248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       420864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3534260                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         43570904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       363264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       549184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2429256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         46602048                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             98189588                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3534260                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2429256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5963516                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     63972864                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6830592                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      69325260                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      32048196                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         172176912                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6915                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         4332                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         6576                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             95630                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            680817                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         5676                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         8581                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             38064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            728175                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1574766                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          999576                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106728                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          1085484                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           500754                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2692542                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             9365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          5867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          8906                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               74789                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              922008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          7687                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker         11621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               51406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              986150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2077799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          74789                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          51406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             126195                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1353736                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          144543                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            1466998                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             678175                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3643452                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1353736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          153908                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         5867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         8906                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              74789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2389006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         7687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker        11621                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              51406                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1664325                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5721251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.dtb.walker       149696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       124032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3867700                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         35125336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       224640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       222848                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2692808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         38798848                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        404992                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             81610900                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3867700                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2692808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6560508                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    100759808                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         100780624                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2339                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1938                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            100840                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            548855                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3510                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3482                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             42182                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            606250                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6328                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1315724                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1574372                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1576975                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2629                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               81983                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              744542                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               57079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              822409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8585                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1729885                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          81983                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          57079                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             139061                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2135779                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                441                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2136220                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2135779                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2629                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              81983                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             744984                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4724                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              57079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             822409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8585                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3866105                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -101,372 +98,13 @@ system.realview.nvmem.bw_total::cpu0.data            1                       # T
 system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              626516                       # Transaction distribution
-system.membus.trans_dist::ReadResp             626516                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38984                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38984                       # Transaction distribution
-system.membus.trans_dist::Writeback            999576                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1690363                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1690363                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           306222                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         316965                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          140146                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1165491                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           989253                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27744                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      8247325                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      8398069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       231310                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       231310                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                8629379                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156015                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55488                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    263093540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    263305247                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7401728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7401728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               270706975                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5022881                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5022881    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             5022881                       # Request fanout histogram
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                  1283901                       # number of replacements
-system.l2c.tags.tagsinuse                62124.562993                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3275357                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1342128                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.440421                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   34388.760809                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    79.804579                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   112.289142                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3576.253573                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7600.803334                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   295.890565                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   418.894238                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2948.167503                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    12703.699250                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.524731                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001218                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.001713                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.054569                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.115979                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004515                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006392                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.044985                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.193843                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.947946                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          419                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        57808                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1           13                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2           14                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           33                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          357                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2958                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4258                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        50148                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.006393                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.882080                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 65498174                       # Number of tag accesses
-system.l2c.tags.data_accesses                65498174                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         5628                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3525                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             452773                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             684956                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         4751                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         2824                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             443971                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             629104                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2227532                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2009484                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2009484                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           14899                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           10552                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               25451                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          1377                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1186                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              2563                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           159390                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           142180                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               301570                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5628                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3525                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              452773                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              844346                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4751                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          2824                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              443971                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              771284                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2529102                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5628                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3525                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             452773                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             844346                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4751                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         2824                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             443971                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             771284                       # number of overall hits
-system.l2c.overall_hits::total                2529102                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         4332                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         6576                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            52529                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           192774                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         5676                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         8581                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            37950                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           226922                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               535340                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         55008                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         52026                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            107034                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         8101                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         7689                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           15790                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         497215                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         509357                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total            1006572                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         4332                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         6576                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             52529                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            689989                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         5676                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         8581                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             37950                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            736279                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1541912                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         4332                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         6576                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            52529                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           689989                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         5676                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         8581                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            37950                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           736279                       # number of overall misses
-system.l2c.overall_misses::total              1541912                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         9960                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        10101                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         505302                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         877730                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10427                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        11405                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         481921                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         856026                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2762872                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2009484                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2009484                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        69907                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        62578                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          132485                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         9478                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         8875                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         18353                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       656605                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       651537                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1308142                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9960                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        10101                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          505302                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1534335                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10427                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        11405                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          481921                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1507563                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4071014                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9960                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        10101                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         505302                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1534335                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10427                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        11405                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         481921                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1507563                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4071014                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.434940                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.651025                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.103956                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.219628                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.544356                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.752389                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.078747                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.265088                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.193762                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.786874                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.831378                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.807895                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.854716                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.866366                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.860350                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.757251                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.781778                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.769467                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.434940                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.651025                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.103956                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.449699                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.544356                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.752389                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.078747                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.488390                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.378754                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.434940                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.651025                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.103956                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.449699                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.544356                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.752389                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.078747                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.488390                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.378754                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              999576                       # number of writebacks
-system.l2c.writebacks::total                   999576                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            3538474                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3538474                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38984                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38984                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2009484                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1583635                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1583635                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          314351                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        319528                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         633879                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1484380                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1484380                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9022261                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7545927                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16568188                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    295040248                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    251523687                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              546563935                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          117027                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9283255                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012458                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.110920                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9167600     98.75%     98.75% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115655      1.25%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9283255                       # Request fanout histogram
-system.iobus.trans_dist::ReadReq                40365                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40365                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136744                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              30016                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47974                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122908                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231230                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231230                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354218                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47994                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156015                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338936                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338936                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7497037                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -490,25 +128,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    91995299                       # DTB read hits
-system.cpu0.dtb.read_misses                     88130                       # DTB read misses
-system.cpu0.dtb.write_hits                   85085254                       # DTB write hits
-system.cpu0.dtb.write_misses                    36248                       # DTB write misses
+system.cpu0.dtb.read_hits                    91355479                       # DTB read hits
+system.cpu0.dtb.read_misses                     87819                       # DTB read misses
+system.cpu0.dtb.write_hits                   84601943                       # DTB write hits
+system.cpu0.dtb.write_misses                    36095                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              49413                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   36322                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                   36260                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  5755                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  5461                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10368                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                92083429                       # DTB read accesses
-system.cpu0.dtb.write_accesses               85121502                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10344                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                91443298                       # DTB read accesses
+system.cpu0.dtb.write_accesses               84638038                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        177080553                       # DTB hits
-system.cpu0.dtb.misses                         124378                       # DTB misses
-system.cpu0.dtb.accesses                    177204931                       # DTB accesses
+system.cpu0.dtb.hits                        175957422                       # DTB hits
+system.cpu0.dtb.misses                         123914                       # DTB misses
+system.cpu0.dtb.accesses                    176081336                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -530,56 +168,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   494454438                       # ITB inst hits
-system.cpu0.itb.inst_misses                     60733                       # ITB inst misses
+system.cpu0.itb.inst_hits                   491372488                       # ITB inst hits
+system.cpu0.itb.inst_misses                     60226                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              49413                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   25125                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                   25015                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               494515171                       # ITB inst accesses
-system.cpu0.itb.hits                        494454438                       # DTB hits
-system.cpu0.itb.misses                          60733                       # DTB misses
-system.cpu0.itb.accesses                    494515171                       # DTB accesses
-system.cpu0.numCycles                     94513084496                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               491432714                       # ITB inst accesses
+system.cpu0.itb.hits                        491372488                       # DTB hits
+system.cpu0.itb.misses                          60226                       # DTB misses
+system.cpu0.itb.accesses                    491432714                       # DTB accesses
+system.cpu0.numCycles                     94354173207                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  494220811                       # Number of instructions committed
-system.cpu0.committedOps                    581241865                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            532688106                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                523244                       # Number of float alu accesses
-system.cpu0.num_func_calls                   28754565                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     75974563                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   532688106                       # number of integer instructions
-system.cpu0.num_fp_insts                       523244                       # number of float instructions
-system.cpu0.num_int_register_reads          780601008                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         422746088                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              843511                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             445224                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           132982110                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          132652018                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    177182019                       # number of memory refs
-system.cpu0.num_load_insts                   92069289                       # Number of load instructions
-system.cpu0.num_store_insts                  85112730                       # Number of store instructions
-system.cpu0.num_idle_cycles              93931506106.304367                       # Number of idle cycles
-system.cpu0.num_busy_cycles              581578389.695634                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.006153                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.993847                       # Percentage of idle cycles
-system.cpu0.Branches                        110567100                       # Number of branches fetched
+system.cpu0.committedInsts                  491139120                       # Number of instructions committed
+system.cpu0.committedOps                    577575160                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            529301791                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                523058                       # Number of float alu accesses
+system.cpu0.num_func_calls                   28573576                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     75495865                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   529301791                       # number of integer instructions
+system.cpu0.num_fp_insts                       523058                       # number of float instructions
+system.cpu0.num_int_register_reads          775565033                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         419986522                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              843711                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             444676                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           132153354                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          131825344                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    176058068                       # number of memory refs
+system.cpu0.num_load_insts                   91428761                       # Number of load instructions
+system.cpu0.num_store_insts                  84629307                       # Number of store instructions
+system.cpu0.num_idle_cycles              93776262262.183929                       # Number of idle cycles
+system.cpu0.num_busy_cycles              577910944.816068                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.006125                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.993875                       # Percentage of idle cycles
+system.cpu0.Branches                        109891880                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                403026584     69.30%     69.30% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1232662      0.21%     69.51% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    59598      0.01%     69.52% # Class of executed instruction
+system.cpu0.op_class::IntAlu                400497126     69.30%     69.30% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1218559      0.21%     69.51% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    59561      0.01%     69.52% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
@@ -602,57 +240,149 @@ system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.52% # Cl
 system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.52% # Class of executed instruction
 system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             73071      0.01%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::MemRead                92069289     15.83%     85.37% # Class of executed instruction
-system.cpu0.op_class::MemWrite               85112730     14.63%    100.00% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             73140      0.01%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::MemRead                91428761     15.82%     85.36% # Class of executed instruction
+system.cpu0.op_class::MemWrite               84629307     14.64%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 581573977                       # Class of executed instruction
+system.cpu0.op_class::total                 577906497                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13359                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements          5478973                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.989014                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          489030308                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5479485                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            89.247495                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   13193                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          6189405                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.263112                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          169698310                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6189917                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.415280                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         35630500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.263112                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988795                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988795                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        358274198                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       358274198                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     84971856                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       84971856                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     79868150                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      79868150                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       214674                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       214674                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       260533                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       260533                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2068908                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      2068908                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2028668                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2028668                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    164840006                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       164840006                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    165054680                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      165054680                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3260277                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3260277                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1458399                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1458399                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       767112                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       767112                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       819206                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       819206                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       116959                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       116959                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       156094                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       156094                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4718676                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4718676                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5485788                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5485788                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     88232133                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     88232133                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     81326549                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     81326549                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       981786                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       981786                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1079739                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1079739                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2185867                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2185867                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2184762                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2184762                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    169558682                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    169558682                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    170540468                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    170540468                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036951                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036951                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017933                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017933                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781343                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781343                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.758707                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.758707                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053507                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053507                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.071447                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.071447                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027829                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.027829                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032167                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032167                       # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks      4407988                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4407988                       # number of writebacks
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements          5467768                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.988996                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          485959047                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5468280                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            88.868721                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       5759896500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989014                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.988996                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          202                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        994499086                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       994499086                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    489030308                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      489030308                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    489030308                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       489030308                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    489030308                       # number of overall hits
-system.cpu0.icache.overall_hits::total      489030308                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5479490                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5479490                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5479490                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5479490                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5479490                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5479490                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    494509798                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    494509798                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    494509798                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    494509798                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    494509798                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    494509798                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011081                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011081                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011081                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011081                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011081                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011081                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        988322949                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       988322949                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    485959047                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      485959047                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    485959047                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       485959047                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    485959047                       # number of overall hits
+system.cpu0.icache.overall_hits::total      485959047                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5468285                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      5468285                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5468285                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       5468285                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5468285                       # number of overall misses
+system.cpu0.icache.overall_misses::total      5468285                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    491427332                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    491427332                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    491427332                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    491427332                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    491427332                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    491427332                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011127                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011127                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011127                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011127                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011127                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011127                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -671,125 +401,132 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         2064608                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16133.195391                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          11362943                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2080515                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.461601                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      4425944000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  5245.148106                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    62.593184                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.054087                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4630.109792                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  6116.290221                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.320138                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003820                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004825                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.282599                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.373309                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.984692                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023          103                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15804                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           74                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.replacements         2648971                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16219.904236                       # Cycle average of tags in use
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+system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  5428.449185                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    50.127041                       # Average occupied blocks per requestor
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4608.843039                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  6080.573004                       # Average occupied blocks per requestor
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 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          878                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4606                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5039                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5169                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006287                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.964600                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       268288822                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      268288822                       # Number of data accesses
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-system.cpu0.l2cache.Writeback_hits::writebacks      3700491                       # number of Writeback hits
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-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         3834                       # number of UpgradeReq hits
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-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       125739                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       125739                       # number of UpgradeReq misses
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-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       129573                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.970411                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.970411                       # miss rate for UpgradeReq accesses
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+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003967                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.974670                       # Percentage of cache occupancy per task id
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+system.cpu0.l2cache.WriteInvalidateReq_accesses::total       818842                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::total       129427                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       156094                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.100667                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.297629                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.731739                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.731739                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.972479                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.972479                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.580063                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.580063                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.043951                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.069744                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092217                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.359719                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.219990                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.043951                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.069744                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092217                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.359719                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.219990                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.525788                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.525788                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.100667                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.353040                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.220132                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039540                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.056212                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.100667                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.353040                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.220132                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -798,134 +535,47 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1036299                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1036299                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks      1542533                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1542533                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          6244160                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          501.112038                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          170764768                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6244672                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.345675                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         35630500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.112038                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978734                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.978734                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        360574457                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       360574457                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     85562109                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       85562109                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     80321665                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      80321665                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       214579                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       214579                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data      1082882                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1082882                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2079487                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      2079487                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2037790                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2037790                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165883774                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       165883774                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    166098353                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      166098353                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3290675                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3290675                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1472676                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1472676                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       774388                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       774388                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       118159                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       118159                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158665                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       158665                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4763351                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4763351                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5537739                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5537739                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     88852784                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     88852784                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     81794341                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     81794341                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       988967                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       988967                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1082882                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1082882                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2197646                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2197646                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2196455                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2196455                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    170647125                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    170647125                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    171636092                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    171636092                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037035                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037035                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018005                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018005                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.783027                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.783027                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053766                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053766                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072237                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072237                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027913                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027913                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032264                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032264                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1082882                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3700491                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3700491                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      10282171                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     10282171                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        33363                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        33363                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3700491                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1082882                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp      1082882                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       129573                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158665                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       288238                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1343103                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1343103                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     11045230                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17628413                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       362824                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       723538                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         29760005                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    350859860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    660019940                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1451296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2894152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1015225248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    3571522                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     20011038                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.169428                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.375130                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      10228504                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     10228504                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        32523                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        32523                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      4407988                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       818842                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       818842                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       129427                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       156094                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       285521                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1329336                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1329336                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     11022820                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17694214                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       359792                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       720614                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         29797440                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    350142740                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    685026670                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1439168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2882456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1039491034                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    3383860                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     20196192                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.158528                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.365236                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          16620607     83.06%     83.06% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6           3390431     16.94%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          16994523     84.15%     84.15% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6           3201669     15.85%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      20011038                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total      20196192                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -949,25 +599,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    90837844                       # DTB read hits
-system.cpu1.dtb.read_misses                    112429                       # DTB read misses
-system.cpu1.dtb.write_hits                   81788331                       # DTB write hits
-system.cpu1.dtb.write_misses                    32675                       # DTB write misses
+system.cpu1.dtb.read_hits                    91720002                       # DTB read hits
+system.cpu1.dtb.read_misses                    112244                       # DTB read misses
+system.cpu1.dtb.write_hits                   82499013                       # DTB write hits
+system.cpu1.dtb.write_misses                    32608                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              49413                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   44635                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                   45118                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4658                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4542                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11499                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                90950273                       # DTB read accesses
-system.cpu1.dtb.write_accesses               81821006                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11534                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                91832246                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82531621                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        172626175                       # DTB hits
-system.cpu1.dtb.misses                         145104                       # DTB misses
-system.cpu1.dtb.accesses                    172771279                       # DTB accesses
+system.cpu1.dtb.hits                        174219015                       # DTB hits
+system.cpu1.dtb.misses                         144852                       # DTB misses
+system.cpu1.dtb.accesses                    174363867                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -989,129 +639,219 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   481654104                       # ITB inst hits
-system.cpu1.itb.inst_misses                     61573                       # ITB inst misses
+system.cpu1.itb.inst_hits                   485906850                       # ITB inst hits
+system.cpu1.itb.inst_misses                     61939                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              49413                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid              49428                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   31343                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                   31863                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               481715677                       # ITB inst accesses
-system.cpu1.itb.hits                        481654104                       # DTB hits
-system.cpu1.itb.misses                          61573                       # DTB misses
-system.cpu1.itb.accesses                    481715677                       # DTB accesses
-system.cpu1.numCycles                     94513077342                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               485968789                       # ITB inst accesses
+system.cpu1.itb.hits                        485906850                       # DTB hits
+system.cpu1.itb.misses                          61939                       # DTB misses
+system.cpu1.itb.accesses                    485968789                       # DTB accesses
+system.cpu1.numCycles                     94354166192                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  481400602                       # Number of instructions committed
-system.cpu1.committedOps                    566525898                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            519925383                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                376275                       # Number of float alu accesses
-system.cpu1.num_func_calls                   28379756                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     73707085                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   519925383                       # number of integer instructions
-system.cpu1.num_fp_insts                       376275                       # number of float instructions
-system.cpu1.num_int_register_reads          767883598                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         413862248                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              612543                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             304496                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           127269525                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          126984366                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    172747819                       # number of memory refs
-system.cpu1.num_load_insts                   90937276                       # Number of load instructions
-system.cpu1.num_store_insts                  81810543                       # Number of store instructions
-system.cpu1.num_idle_cycles              93946237892.041718                       # Number of idle cycles
-system.cpu1.num_busy_cycles              566839449.958294                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.005997                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.994003                       # Percentage of idle cycles
-system.cpu1.Branches                        107245418                       # Number of branches fetched
+system.cpu1.committedInsts                  485652916                       # Number of instructions committed
+system.cpu1.committedOps                    571511718                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            524558211                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                375128                       # Number of float alu accesses
+system.cpu1.num_func_calls                   28666071                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     74347572                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   524558211                       # number of integer instructions
+system.cpu1.num_fp_insts                       375128                       # number of float instructions
+system.cpu1.num_int_register_reads          774388464                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         417530639                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              610571                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             303256                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           128278137                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          127991607                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    174340371                       # number of memory refs
+system.cpu1.num_load_insts                   91819242                       # Number of load instructions
+system.cpu1.num_store_insts                  82521129                       # Number of store instructions
+system.cpu1.num_idle_cycles              93782340058.888657                       # Number of idle cycles
+system.cpu1.num_busy_cycles              571826133.111340                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.006060                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.993940                       # Percentage of idle cycles
+system.cpu1.Branches                        108195111                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                392850961     69.31%     69.31% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1138465      0.20%     69.51% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    60868      0.01%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             36493      0.01%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::MemRead                90937276     16.04%     85.57% # Class of executed instruction
-system.cpu1.op_class::MemWrite               81810543     14.43%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                396230726     69.29%     69.29% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1151823      0.20%     69.49% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    61886      0.01%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             36426      0.01%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
+system.cpu1.op_class::MemRead                91819242     16.06%     85.57% # Class of executed instruction
+system.cpu1.op_class::MemWrite               82521129     14.43%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 566834606                       # Class of executed instruction
+system.cpu1.op_class::total                 571821232                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    6205                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements          4804797                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.439171                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          476903871                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4805309                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            99.245204                       # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce                    6178                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements          6025220                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          443.938244                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          168203685                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          6025731                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            27.914237                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8470277778500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   443.938244                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867067                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.867067                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        354758936                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       354758936                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     85201700                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       85201700                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     78314445                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      78314445                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188411                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       188411                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        65692                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total        65692                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2073864                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      2073864                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2064069                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      2064069                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    163516145                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       163516145                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    163704556                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      163704556                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3403274                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3403274                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1467363                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1467363                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       796168                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       796168                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       438523                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       438523                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       149383                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       149383                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       157982                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       157982                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4870637                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4870637                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5666805                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5666805                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     88604974                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     88604974                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     79781808                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     79781808                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       984579                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       984579                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       504215                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       504215                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2223247                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2223247                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2222051                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2222051                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    168386782                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    168386782                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    169371361                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    169371361                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038410                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.038410                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018392                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018392                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808638                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808638                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.869714                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.869714                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.067191                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.067191                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071097                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071097                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028925                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.028925                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033458                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.033458                       # miss rate for overall accesses
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks      4091318                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4091318                       # number of writebacks
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements          4818195                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.412963                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          481143593                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          4818707                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            99.849107                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8470205816000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.439171                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969608                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969608                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.412963                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969557                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969557                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        968223669                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       968223669                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    476903871                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      476903871                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    476903871                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       476903871                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    476903871                       # number of overall hits
-system.cpu1.icache.overall_hits::total      476903871                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4805309                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4805309                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4805309                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4805309                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4805309                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4805309                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    481709180                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    481709180                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    481709180                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    481709180                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    481709180                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    481709180                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009976                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.009976                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009976                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.009976                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009976                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.009976                       # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses        976743307                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       976743307                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    481143593                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      481143593                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    481143593                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       481143593                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    481143593                       # number of overall hits
+system.cpu1.icache.overall_hits::total      481143593                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      4818707                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      4818707                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      4818707                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       4818707                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      4818707                       # number of overall misses
+system.cpu1.icache.overall_misses::total      4818707                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    485962300                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    485962300                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    485962300                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    485962300                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    485962300                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    485962300                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009916                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.009916                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009916                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.009916                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009916                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.009916                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1130,125 +870,133 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         2006739                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13469.548164                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          10823103                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2022814                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            5.350518                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    47068377163500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5364.772438                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.646390                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    85.907417                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2770.929506                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5181.292411                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.327440                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004068                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005243                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.169124                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.316241                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.822116                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           89                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15986                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.replacements         2333825                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13484.024344                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          11006559                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2349876                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.683889                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9726491548000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5253.379361                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    67.604678                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.064726                       # Average occupied blocks per requestor
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 system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          357                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1288                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4895                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4461                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4985                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005432                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.975708                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       249408047                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      249408047                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       323614                       # number of ReadReq hits
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-system.cpu1.l2cache.ReadReq_hits::total       7876323                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3626404                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3626404                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         4173                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         4173                       # number of UpgradeReq hits
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-system.cpu1.l2cache.ReadReq_misses::cpu1.data      1212062                       # number of ReadReq misses
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-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       130320                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       130320                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       160863                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.overall_accesses::cpu1.data      5678892                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10984957                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.111852                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.288174                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.187940                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.618571                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.618571                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.971939                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.971939                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.580900                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.580900                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.039866                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.078691                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.100289                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.351705                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.227573                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.039866                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.078691                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.100289                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.351705                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.227573                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532845                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532845                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.111852                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345479                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.229701                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.037339                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.064657                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.111852                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345479                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.229701                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1257,180 +1005,143 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       973185                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          973185                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks      1212706                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1212706                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements          5959116                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          422.411507                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          166676723                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5959628                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.967639                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8470277778500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   422.411507                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.825022                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.825022                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          348                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        351511714                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       351511714                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     84377625                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       84377625                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     77641502                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      77641502                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188364                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       188364                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       500753                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       500753                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062405                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      2062405                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2046128                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      2046128                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    162019127                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       162019127                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    162207491                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      162207491                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3366733                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3366733                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1448985                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1448985                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       790218                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       790218                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       145903                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       145903                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       160863                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       160863                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4815718                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4815718                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5605936                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5605936                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     87744358                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     87744358                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     79090487                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     79090487                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       978582                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       978582                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       500753                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       500753                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2208308                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2208308                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2206991                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2206991                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    166834845                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    166834845                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    167813427                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    167813427                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038370                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.038370                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018321                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018321                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.807513                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.807513                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066070                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066070                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.072888                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.072888                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028865                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.028865                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033406                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.033406                       # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                 500753                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3626404                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3626404                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       9718709                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9718709                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         5621                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         5621                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3626404                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       500753                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       500753                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       134493                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       160863                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       295356                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1314492                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1314492                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9610878                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16476244                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       368094                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       841050                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         27296266                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    307540296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    623681695                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1472376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3364200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         936058567                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    4159575                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     19448735                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.205617                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.404152                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq       9779239                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9779239                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         6380                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         6380                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      4091318                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       438296                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       438296                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       137523                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       157982                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       295505                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1330067                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1330067                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9637674                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16942172                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       370292                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       840154                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         27790292                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    308397768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    653382681                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1481168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3360616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         966622233                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    3659793                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     19426876                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.180108                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.384277                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          15449740     79.44%     79.44% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6           3998995     20.56%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          15927941     81.99%     81.99% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6           3498935     18.01%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      19448735                       # Request fanout histogram
-system.iocache.tags.replacements               115596                       # number of replacements
-system.iocache.tags.tagsinuse               11.294855                       # Cycle average of tags in use
+system.cpu1.toL2Bus.snoop_fanout::total      19426876                       # Request fanout histogram
+system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136741                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30013                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47950                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122884                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354174                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47970                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155991                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7496933                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements               115586                       # number of replacements
+system.iocache.tags.tagsinuse               11.286927                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115612                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115602                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         9107775783009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.848747                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.446108                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.240547                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.465382                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705928                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet     3.855232                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.431695                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.240952                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.464481                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705433                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040892                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040892                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106728                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106728                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1040802                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040802                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8887                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8924                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8877                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8914                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8887                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8927                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8877                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8917                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8887                       # number of overall misses
-system.iocache.overall_misses::total             8927                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8877                       # number of overall misses
+system.iocache.overall_misses::total             8917                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8887                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8924                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8877                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8914                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8887                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8927                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8877                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8917                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8887                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8927                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8877                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8917                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -1443,8 +1154,332 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106728                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1764050                       # number of replacements
+system.l2c.tags.tagsinuse                62893.103184                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3693923                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1823047                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.026236                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                482634500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35252.715261                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    32.297168                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    36.889266                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3199.431904                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6870.253722                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   308.072507                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   447.332489                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2890.642136                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    13855.468731                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.537914                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000493                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.104832                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004701                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006826                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1024        58788                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          542                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3602                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5588                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        49009                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003189                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.897034                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 66315846                       # Number of tag accesses
+system.l2c.tags.data_accesses                66315846                       # Number of data accesses
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+system.l2c.Writeback_hits::writebacks         2755239                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2755239                       # number of Writeback hits
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+system.l2c.WriteInvalidateReq_hits::total       218387                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.data           13978                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           10743                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               24721                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          1494                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_accesses::cpu0.data       573124                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       598686                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1171810                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8259                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6263                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          550478                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1478911                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9240                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7246                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          538984                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1498419                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4097800                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8259                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6263                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         550478                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1478911                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9240                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7246                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         538984                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1498419                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4097800                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.104889                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.201656                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.078075                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.214199                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.166258                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.804765                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.610587                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.744788                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805076                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836718                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.820216                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.834935                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.852491                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.843535                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.657055                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.702898                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.680476                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.104889                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.378137                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.078075                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.409456                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.313304                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.283206                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.309436                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.104889                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.378137                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.379870                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.480541                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.078075                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.409456                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.313304                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks             1467678                       # number of writebacks
+system.l2c.writebacks::total                  1467678                       # number of writebacks
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              577534                       # Transaction distribution
+system.membus.trans_dist::ReadResp             577534                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38903                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38903                       # Transaction distribution
+system.membus.trans_dist::Writeback           1574372                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       739425                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       739425                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           325897                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         311300                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          149445                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            961374                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780321                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122884                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27406                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6326067                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6476449                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337984                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       337984                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6814433                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155991                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        54812                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    215692580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    215903587                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14229504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14229504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               230133091                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4407750                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4407750    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             4407750                       # Request fanout histogram
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq            3699896                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3699896                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38903                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38903                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2755239                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       855709                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp       855709                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          328922                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        314076                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         642998                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1352863                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1352863                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8525495                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7410482                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15935977                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    295216066                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    254408545                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              549624611                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          117315                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9340198                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012381                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.110581                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                9224553     98.76%     98.76% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115645      1.24%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            9340198                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 3343b5f3d..09df20817 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -1,59 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.111167                       # Number of seconds simulated
-sim_ticks                                51111167186000                       # Number of ticks simulated
-final_tick                               51111167186000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.111151                       # Number of seconds simulated
+sim_ticks                                51111150553500                       # Number of ticks simulated
+final_tick                               51111150553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1374172                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1614949                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            71508211345                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 650720                       # Number of bytes of host memory used
-host_seconds                                   714.76                       # Real time elapsed on the host
-sim_insts                                   982202425                       # Number of instructions simulated
-sim_ops                                    1154300154                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1176583                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1382679                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            61065327647                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 656288                       # Number of bytes of host memory used
+host_seconds                                   836.99                       # Real time elapsed on the host
+sim_insts                                   984789519                       # Number of instructions simulated
+sim_ops                                    1157289961                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        441600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker       674240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       976256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5095732                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          90778056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             97965884                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5095732                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5095732                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65987904                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data      101336100                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         174150500                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6900                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker        10535                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker        15254                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             120028                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1418420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1571137                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1031061                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data           1585628                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2723353                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker          13192                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          19101                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst                99699                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1776090                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1916722                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           99699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              99699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1291066                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          133562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1982661                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3407289                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1291066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          142202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker         13192                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         19101                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               99699                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3758751                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5324010                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.dtb.walker       411136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       373504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5556020                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          75320200                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        437696                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             82098556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5556020                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5556020                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103277568                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103298148                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5836                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             127220                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1176891                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1323210                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1613712                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1616285                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           8044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           7308                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1473655                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8564                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1606275                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2020647                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2021049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2020647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          8044                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          7308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1474058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8564                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3627324                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -70,141 +67,12 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              581631                       # Transaction distribution
-system.membus.trans_dist::ReadResp             581631                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33712                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33712                       # Transaction distribution
-system.membus.trans_dist::Writeback           1031061                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1689719                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1689719                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40041                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40042                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1025075                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1025075                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122798                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      7410875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      7540385                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       231034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       231034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7771419                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    264848480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    265017848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7392896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7392896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               272410744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4290796                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4290796    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4290796                       # Request fanout histogram
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29957                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122798                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353832                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47936                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155928                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492262                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -229,25 +97,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183545113                       # DTB read hits
-system.cpu.dtb.read_misses                     195347                       # DTB read misses
-system.cpu.dtb.write_hits                   167775000                       # DTB write hits
-system.cpu.dtb.write_misses                     71236                       # DTB write misses
+system.cpu.dtb.read_hits                    184057973                       # DTB read hits
+system.cpu.dtb.read_misses                     194269                       # DTB read misses
+system.cpu.dtb.write_hits                   168276300                       # DTB write hits
+system.cpu.dtb.write_misses                     71349                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    82503                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                    81439                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9078                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   9105                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                     21651                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                183740460                       # DTB read accesses
-system.cpu.dtb.write_accesses               167846236                       # DTB write accesses
+system.cpu.dtb.read_accesses                184252242                       # DTB read accesses
+system.cpu.dtb.write_accesses               168347649                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         351320113                       # DTB hits
-system.cpu.dtb.misses                          266583                       # DTB misses
-system.cpu.dtb.accesses                     351586696                       # DTB accesses
+system.cpu.dtb.hits                         352334273                       # DTB hits
+system.cpu.dtb.misses                          265618                       # DTB misses
+system.cpu.dtb.accesses                     352599891                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -269,8 +137,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    982679430                       # ITB inst hits
-system.cpu.itb.inst_misses                     126834                       # ITB inst misses
+system.cpu.itb.inst_hits                    985266544                       # ITB inst hits
+system.cpu.itb.inst_misses                     126829                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -279,119 +147,210 @@ system.cpu.itb.flush_tlb                           11                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    58073                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    57079                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                982806264                       # ITB inst accesses
-system.cpu.itb.hits                         982679430                       # DTB hits
-system.cpu.itb.misses                          126834                       # DTB misses
-system.cpu.itb.accesses                     982806264                       # DTB accesses
-system.cpu.numCycles                     102222351148                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                985393373                       # ITB inst accesses
+system.cpu.itb.hits                         985266544                       # DTB hits
+system.cpu.itb.misses                          126829                       # DTB misses
+system.cpu.itb.accesses                     985393373                       # DTB accesses
+system.cpu.numCycles                     102222317883                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   982202425                       # Number of instructions committed
-system.cpu.committedOps                    1154300154                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1057881248                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 881349                       # Number of float alu accesses
-system.cpu.num_func_calls                    56834159                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    151623535                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1057881248                       # number of integer instructions
-system.cpu.num_fp_insts                        881349                       # number of float instructions
-system.cpu.num_int_register_reads          1560758600                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          840516230                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1419767                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              748560                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            264018450                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           263440675                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     351539543                       # number of memory refs
-system.cpu.num_load_insts                   183712417                       # Number of load instructions
-system.cpu.num_store_insts                  167827126                       # Number of store instructions
-system.cpu.num_idle_cycles               101067404227.616409                       # Number of idle cycles
-system.cpu.num_busy_cycles               1154946920.383593                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.011298                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.988702                       # Percentage of idle cycles
-system.cpu.Branches                         219533477                       # Number of branches fetched
+system.cpu.committedInsts                   984789519                       # Number of instructions committed
+system.cpu.committedOps                    1157289961                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1060698532                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 880773                       # Number of float alu accesses
+system.cpu.num_func_calls                    57075493                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    151966445                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1060698532                       # number of integer instructions
+system.cpu.num_fp_insts                        880773                       # number of float instructions
+system.cpu.num_int_register_reads          1564314393                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          842633326                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1418999                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              747792                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            264443211                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           263865511                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     352552781                       # number of memory refs
+system.cpu.num_load_insts                   184224242                       # Number of load instructions
+system.cpu.num_store_insts                  168328539                       # Number of store instructions
+system.cpu.num_idle_cycles               101064381138.333679                       # Number of idle cycles
+system.cpu.num_busy_cycles               1157936744.666323                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.011328                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.988672                       # Percentage of idle cycles
+system.cpu.Branches                         220135160                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 800832645     69.34%     69.34% # Class of executed instruction
-system.cpu.op_class::IntMult                  2354384      0.20%     69.54% # Class of executed instruction
-system.cpu.op_class::IntDiv                    100543      0.01%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             107822      0.01%     69.56% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     69.56% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.56% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.56% # Class of executed instruction
-system.cpu.op_class::MemRead                183712417     15.91%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               167827126     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 802806903     69.33%     69.33% # Class of executed instruction
+system.cpu.op_class::IntMult                  2355402      0.20%     69.53% # Class of executed instruction
+system.cpu.op_class::IntDiv                    101851      0.01%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             107822      0.01%     69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.55% # Class of executed instruction
+system.cpu.op_class::MemRead                184224242     15.91%     85.46% # Class of executed instruction
+system.cpu.op_class::MemWrite               168328539     14.54%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1154934980                       # Class of executed instruction
+system.cpu.op_class::total                 1157924802                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements          14265263                       # number of replacements
+system.cpu.dcache.tags.replacements          11615783                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.999718                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           340859576                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11616295                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.343227                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.999718                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1421519854                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1421519854                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    171606610                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       171606610                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    159566138                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      159566138                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       424146                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        424146                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       337798                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       337798                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4310377                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4310377                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4563246                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4563246                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     331172748                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        331172748                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    331596894                       # number of overall hits
+system.cpu.dcache.overall_hits::total       331596894                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6013361                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6013361                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2569466                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2569466                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1584813                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1584813                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1245259                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1245259                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       254671                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       254671                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      8582827                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8582827                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     10167640                       # number of overall misses
+system.cpu.dcache.overall_misses::total      10167640                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data    177619971                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177619971                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    162135604                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    162135604                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2008959                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2008959                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583057                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1583057                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4565048                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4565048                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4563247                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4563247                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    339755575                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    339755575                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    341764534                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    341764534                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033855                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033855                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015848                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015848                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788873                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.788873                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786617                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786617                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055787                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055787                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025262                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025262                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.029750                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.029750                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      8923646                       # number of writebacks
+system.cpu.dcache.writebacks::total           8923646                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          14287218                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           968528346                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          14265775                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.891744                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           971093500                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14287730                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.966955                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        6061930000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.984599                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999970                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         997059906                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        997059906                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    968528346                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       968528346                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     968528346                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        968528346                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    968528346                       # number of overall hits
-system.cpu.icache.overall_hits::total       968528346                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     14265780                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      14265780                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     14265780                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       14265780                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     14265780                       # number of overall misses
-system.cpu.icache.overall_misses::total      14265780                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    982794126                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    982794126                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    982794126                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    982794126                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    982794126                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    982794126                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014516                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014516                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014516                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014516                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014516                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         999668970                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        999668970                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    971093500                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       971093500                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     971093500                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        971093500                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    971093500                       # number of overall hits
+system.cpu.icache.overall_hits::total       971093500                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     14287735                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      14287735                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     14287735                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       14287735                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     14287735                       # number of overall misses
+system.cpu.icache.overall_misses::total      14287735                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    985381235                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    985381235                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    985381235                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    985381235                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    985381235                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    985381235                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014500                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014500                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014500                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014500                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014500                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014500                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,124 +360,130 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1249729                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64613.042707                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29358469                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1311519                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            22.385089                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     13800320247500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36056.727460                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   328.031175                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   484.456162                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6427.999826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21315.828084                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.550182                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005005                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007392                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.098083                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.325254                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.985917                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          450                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61340                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2192                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4810                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53977                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.006866                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935974                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.tags.data_accesses       283403664                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       246769                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total       22390438                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7859784                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7859784                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        11730                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        11730                       # number of UpgradeReq hits
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-system.cpu.l2cache.UpgradeReq_misses::cpu.data        39478                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        39478                       # number of UpgradeReq misses
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+system.cpu.l2cache.tags.tagsinuse        65261.456081                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           29978708                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1789688                       # Sample count of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          597                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2750                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4968                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54019                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003784                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953537                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        290358067                       # Number of tag accesses
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+system.cpu.l2cache.Writeback_hits::total      8923646                       # number of Writeback hits
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012411                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022044                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005888                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.113593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.050095                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -527,181 +492,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1031061                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1031061                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1507081                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1507081                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements          11606184                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           339855980                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11606696                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.281027                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.999719                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1417457465                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1417457465                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    171111123                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       171111123                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    159073587                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      159073587                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       424480                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        424480                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data      1583055                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total      1583055                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303648                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4303648                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4555648                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4555648                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     330184710                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        330184710                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    330609190                       # number of overall hits
-system.cpu.dcache.overall_hits::total       330609190                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6002953                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6002953                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2568202                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2568202                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1586188                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1586188                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       253804                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       253804                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      8571155                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8571155                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     10157343                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10157343                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data    177114076                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177114076                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    161641789                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    161641789                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2010668                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2010668                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583055                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1583055                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557452                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4557452                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4555649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    338755865                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    338755865                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    340766533                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    340766533                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033893                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033893                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788886                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.788886                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055690                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055690                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025302                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025302                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.029807                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.029807                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                 1583055                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7859784                       # number of writebacks
-system.cpu.dcache.writebacks::total           7859784                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23338761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23338761                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       23368238                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23368238                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33712                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33712                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7859784                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1583055                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1583055                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        51208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8923646                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1245259                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1245259                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        51260                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        51209                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2516994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2516994                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     28617810                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31982828                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758208                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1548400                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          62907246                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    913182420                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1267567780                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6193600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2189976632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      116124                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     35388588                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.003264                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.057040                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        51261                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2518206                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2518206                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     28661720                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32393426                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758172                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1543680                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          63356998                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    914587540                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1314747172                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6174720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2238542120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      116335                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     36145396                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.003196                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.056442                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           35273071     99.67%     99.67% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115517      0.33%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           36029878     99.68%     99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115518      0.32%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       35388588                       # Request fanout histogram
-system.iocache.tags.replacements               115459                       # number of replacements
-system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
+system.cpu.toL2Bus.snoop_fanout::total       36145396                       # Request fanout histogram
+system.iobus.trans_dist::ReadReq                40296                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40296                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              29957                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122798                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47936                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155928                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492270                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements               115460                       # number of replacements
+system.iocache.tags.tagsinuse               10.407109                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115476                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13082113302009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet     3.554601                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.852508                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.222163                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.428282                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.650444                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039650                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039659                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039659                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8814                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8851                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
+system.iocache.overall_misses::total             8854                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -714,8 +641,92 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              526448                       # Transaction distribution
+system.membus.trans_dist::ReadResp             526448                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33712                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33712                       # Transaction distribution
+system.membus.trans_dist::Writeback           1613712                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       654602                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       654602                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40596                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40597                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            833043                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           833043                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122798                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5323339                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5452849                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337667                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       337667                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5790516                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    213244448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    213413816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14217344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               227631160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3591670                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3591670    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             3591670                       # Request fanout histogram
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 36c2b5576..2d0abc648 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,175 +1,172 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.566016                       # Number of seconds simulated
-sim_ticks                                47566015848000                       # Number of ticks simulated
-final_tick                               47566015848000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.398431                       # Number of seconds simulated
+sim_ticks                                47398431268500                       # Number of ticks simulated
+final_tick                               47398431268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 675626                       # Simulator instruction rate (inst/s)
-host_op_rate                                   794684                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            35963293075                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 873656                       # Number of bytes of host memory used
-host_seconds                                  1322.63                       # Real time elapsed on the host
-sim_insts                                   893600449                       # Number of instructions simulated
-sim_ops                                    1051070162                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 671569                       # Simulator instruction rate (inst/s)
+host_op_rate                                   790318                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            37657329129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 861000                       # Number of bytes of host memory used
+host_seconds                                  1258.68                       # Real time elapsed on the host
+sim_insts                                   845288376                       # Number of instructions simulated
+sim_ops                                     994755388                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       233408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       408704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           743028                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         13616152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     28206528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       271488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       437568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           534776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         13513568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     26761152                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        461312                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             85187684                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       743028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       534776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1277804                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     43935424                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      56825292                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      43859652                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6846976                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         151467344                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3647                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         6386                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             52017                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            212774                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       440727                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         4242                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         6837                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              8444                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            211164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       418143                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1371589                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          686491                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           890172                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           685308                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106984                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2368955                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          4907                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          8592                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               15621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              286258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       592997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          5708                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          9199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               11243                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              284101                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       562611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9698                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1790936                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          15621                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          11243                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              26864                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            923673                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            1194662                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             922080                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          143947                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3184361                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            923673                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4907                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         8592                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              15621                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1480920                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       592997                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         5708                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         9199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              11243                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1206181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       562611                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          153645                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4975296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1371589                       # Number of read requests accepted
-system.physmem.writeReqs                      2368955                       # Number of write requests accepted
-system.physmem.readBursts                     1371589                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2368955                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 87480576                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    301120                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 145871552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  85187684                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              151467344                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     4705                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   89687                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          96177                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               85059                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               83413                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               77756                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               83623                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               79267                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               92440                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               79265                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               88179                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               75468                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              124700                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              77875                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              89966                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              78954                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              87199                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              85039                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              78681                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              146127                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              131230                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              144620                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              127213                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              148937                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              150009                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              182023                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              144700                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              124458                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              140305                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             119798                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             155853                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             153554                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             129042                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             144270                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             137104                       # Per bank write bursts
+system.physmem.bytes_read::cpu0.dtb.walker        36416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        41984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           768052                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          7936536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     44723840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        83456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        97984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           589368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          8667104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     21031552                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        441920                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             84418212                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       768052                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       589368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1357420                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65101248                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65122064                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          569                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker          656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             52408                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            124030                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       698810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1304                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1531                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            135438                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       328618                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6905                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1359566                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1017207                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1019810                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               16204                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              167443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       943572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1761                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2067                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               12434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              182856                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       443718                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9324                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1781034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          16204                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          12434                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              28639                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1373490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1373929                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1373490                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          886                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              16204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             167882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       943572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2067                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              12434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             182856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       443718                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9324                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3154963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1359566                       # Number of read requests accepted
+system.physmem.writeReqs                      1139623                       # Number of write requests accepted
+system.physmem.readBursts                     1359566                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1139623                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 86962304                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     49920                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  72439488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  84418212                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               72790096                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      780                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7732                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          85004                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               81504                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               94599                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               79086                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               89082                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               90127                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               94039                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               78740                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               79772                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               80197                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              124149                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              71869                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              83577                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              73174                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              83519                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              78794                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              76558                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               70549                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               76959                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               69527                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76268                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               71760                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               76111                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               67646                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               68141                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               69345                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               72887                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65485                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              73987                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65828                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              73935                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66021                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              67418                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47566012867000                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47398428076000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1328352                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1316329                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2366352                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    854051                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    158360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     84564                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     68503                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     51448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     44074                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     37830                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     31756                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     25068                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4404                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1973                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1006                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      782                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      591                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      229                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1137020                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    566894                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    282234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    134057                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    101972                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     67644                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     58693                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     53670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     46721                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     35916                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3762                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1955                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      882                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      709                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      229                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      184                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       75                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
@@ -191,157 +188,158 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    89303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    97776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                   118763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                   123056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   124315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   149365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   133979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   128880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   131405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   133820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   133411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   132599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   131583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   133798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   128352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   124285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   123534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   120195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       832768                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      280.211728                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.211424                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     337.275385                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         413524     49.66%     49.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       160093     19.22%     68.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        57236      6.87%     75.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        29306      3.52%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        24972      3.00%     82.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        16042      1.93%     84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        12534      1.51%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        12228      1.47%     87.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       106833     12.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         832768                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        117976                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        11.586017                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      192.972695                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         117973    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-59391            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          117976                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        117976                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.319548                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.993188                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        4.933657                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           75459     63.96%     63.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23           36712     31.12%     95.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            3025      2.56%     97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             865      0.73%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             773      0.66%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             198      0.17%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             143      0.12%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              73      0.06%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              88      0.07%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              20      0.02%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              14      0.01%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.01%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             383      0.32%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              36      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              51      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              22      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              46      0.04%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               9      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             5      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             6      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            16      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          117976                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    39242427762                       # Total ticks spent queuing
-system.physmem.totMemAccLat               64871502762                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6834420000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28709.41                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                    16911                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    22466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    30737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    39170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    44059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    50283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    58139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    68202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    72051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    76579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    76851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    78478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    78341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    80363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    74556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    75992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    78312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    75395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    11828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     7611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     4129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      505                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       648906                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      245.646870                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.183985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     295.195613                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         325424     50.15%     50.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       135792     20.93%     71.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        50411      7.77%     78.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        26706      4.12%     82.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22287      3.43%     86.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        16108      2.48%     88.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10950      1.69%     90.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        13619      2.10%     92.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        47609      7.34%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         648906                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         58676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.156827                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      139.787244                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          58673     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-25599            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           58676                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         58676                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.290119                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.850822                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.308232                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           54948     93.65%     93.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             970      1.65%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             598      1.02%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             219      0.37%     96.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             626      1.07%     97.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             147      0.25%     98.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             195      0.33%     98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             132      0.22%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             184      0.31%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              81      0.14%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            205      0.35%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            24      0.04%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            63      0.11%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            38      0.06%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           129      0.22%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            15      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            27      0.05%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            11      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            19      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             8      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            11      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             6      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           58676                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    69966976258                       # Total ticks spent queuing
+system.physmem.totMemAccLat               95444213758                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6793930000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51492.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47459.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  70242.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.83                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.32                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.10                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1063781                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1749574                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12716335.61                       # Average gap between requests
-system.physmem.pageHitRate                      77.16                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     45509072189751                       # Time in different power states
-system.physmem.memoryStateTime::REF      1588333760000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1114788                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    726958                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  64.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18965523.65                       # Average gap between requests
+system.physmem.pageHitRate                      73.95                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     45538400789750                       # Time in different power states
+system.physmem.memoryStateTime::REF      1582737780000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      468608703999                       # Time in different power states
+system.physmem.memoryStateTime::ACT      277292625250                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3171472920                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3124253160                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1730466375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1704701625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               5218192200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               5443409400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              7613086320                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              7156408320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3106780834560                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3106780834560                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1266482203425                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1265693181210                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          27428659482750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          27429351607500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            31819655738550                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            31819254395775                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.957784                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.949346                       # Core power per rank (mW)
+system.physmem.actEnergy::0                2564850960                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                2340878400                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1399472250                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1277265000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               5358202200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               5240320800                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              3738707280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              3595790880                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3095835097680                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3095835097680                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1171174509540                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1161726671475                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          27411712647750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          27420000225000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            31691783487660                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            31690016249235                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.625157                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.587872                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -371,9 +369,9 @@ system.realview.nvmem.bw_total::total               4                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cf0.dma_write_full_pages                  1670                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6842880                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1673                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -398,25 +396,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    86716512                       # DTB read hits
-system.cpu0.dtb.read_misses                     82712                       # DTB read misses
-system.cpu0.dtb.write_hits                   78633728                       # DTB write hits
-system.cpu0.dtb.write_misses                    28389                       # DTB write misses
+system.cpu0.dtb.read_hits                    74706058                       # DTB read hits
+system.cpu0.dtb.read_misses                     64792                       # DTB read misses
+system.cpu0.dtb.write_hits                   67192400                       # DTB write hits
+system.cpu0.dtb.write_misses                    21129                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   34135                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   33482                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4682                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3817                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9159                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                86799224                       # DTB read accesses
-system.cpu0.dtb.write_accesses               78662117                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     8375                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                74770850                       # DTB read accesses
+system.cpu0.dtb.write_accesses               67213529                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        165350240                       # DTB hits
-system.cpu0.dtb.misses                         111101                       # DTB misses
-system.cpu0.dtb.accesses                    165461341                       # DTB accesses
+system.cpu0.dtb.hits                        141898458                       # DTB hits
+system.cpu0.dtb.misses                          85921                       # DTB misses
+system.cpu0.dtb.accesses                    141984379                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -438,283 +436,295 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   459685693                       # ITB inst hits
-system.cpu0.itb.inst_misses                     60045                       # ITB inst misses
+system.cpu0.itb.inst_hits                   397874920                       # ITB inst hits
+system.cpu0.itb.inst_misses                     49120                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24187                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   23760                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               459745738                       # ITB inst accesses
-system.cpu0.itb.hits                        459685693                       # DTB hits
-system.cpu0.itb.misses                          60045                       # DTB misses
-system.cpu0.itb.accesses                    459745738                       # DTB accesses
-system.cpu0.numCycles                     95132031682                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               397924040                       # ITB inst accesses
+system.cpu0.itb.hits                        397874920                       # DTB hits
+system.cpu0.itb.misses                          49120                       # DTB misses
+system.cpu0.itb.accesses                    397924040                       # DTB accesses
+system.cpu0.numCycles                     94796862537                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  459439593                       # Number of instructions committed
-system.cpu0.committedOps                    539347874                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            495403687                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                451172                       # Number of float alu accesses
-system.cpu0.num_func_calls                   27064307                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     69711991                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   495403687                       # number of integer instructions
-system.cpu0.num_fp_insts                       451172                       # number of float instructions
-system.cpu0.num_int_register_reads          715734727                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         392523746                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              749199                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             337216                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           119686995                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          119275623                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    165340768                       # number of memory refs
-system.cpu0.num_load_insts                   86711184                       # Number of load instructions
-system.cpu0.num_store_insts                  78629584                       # Number of store instructions
-system.cpu0.num_idle_cycles              94014587829.536469                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1117443852.463529                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011746                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988254                       # Percentage of idle cycles
-system.cpu0.Branches                        102470244                       # Number of branches fetched
+system.cpu0.committedInsts                  397643174                       # Number of instructions committed
+system.cpu0.committedOps                    466635553                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            429030148                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                322477                       # Number of float alu accesses
+system.cpu0.num_func_calls                   23930039                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     59901605                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   429030148                       # number of integer instructions
+system.cpu0.num_fp_insts                       322477                       # number of float instructions
+system.cpu0.num_int_register_reads          621630892                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         340702516                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              547437                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             211832                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           102593685                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          102325899                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    141893093                       # number of memory refs
+system.cpu0.num_load_insts                   74704433                       # Number of load instructions
+system.cpu0.num_store_insts                  67188660                       # Number of store instructions
+system.cpu0.num_idle_cycles              93886429062.298019                       # Number of idle cycles
+system.cpu0.num_busy_cycles              910433474.701981                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.009604                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.990396                       # Percentage of idle cycles
+system.cpu0.Branches                         88352328                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                373021399     69.12%     69.12% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1165287      0.22%     69.34% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    62749      0.01%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             46895      0.01%     69.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
-system.cpu0.op_class::MemRead                86711184     16.07%     85.43% # Class of executed instruction
-system.cpu0.op_class::MemWrite               78629584     14.57%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                323823287     69.35%     69.35% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1114929      0.24%     69.59% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    56737      0.01%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             22377      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
+system.cpu0.op_class::MemRead                74704433     16.00%     85.61% # Class of executed instruction
+system.cpu0.op_class::MemWrite               67188660     14.39%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 539637098                       # Class of executed instruction
+system.cpu0.op_class::total                 466910423                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5368                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          5553236                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          507.463915                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          159572063                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5553747                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.732325                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    5105                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          4859280                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          480.680410                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          136835586                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          4859789                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.156693                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       3644536500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.463915                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.991140                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.991140                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        336276505                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       336276505                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80841388                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       80841388                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     74354122                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      74354122                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186421                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       186421                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       887570                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       887570                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1858688                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1858688                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1820106                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1820106                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    155195510                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       155195510                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    155381931                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      155381931                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3020518                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3020518                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1355895                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1355895                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       638649                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       638649                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       156836                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       156836                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194186                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       194186                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4376413                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4376413                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5015062                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5015062                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44235181893                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  44235181893                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  23644478419                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  23644478419                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2243299062                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2243299062                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4135736633                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4135736633                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1563000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1563000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  67879660312                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  67879660312                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  67879660312                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  67879660312                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     83861906                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     83861906                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     75710017                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     75710017                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       825070                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       825070                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       887570                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total       887570                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2015524                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2015524                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2014292                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2014292                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    159571923                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    159571923                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    160396993                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    160396993                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036018                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036018                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774054                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774054                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077814                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077814                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.096404                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.096404                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027426                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027426                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031267                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.031267                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.680410                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938829                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.938829                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          406                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2            9                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        288671468                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       288671468                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     69599952                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       69599952                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     63413457                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      63413457                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       173858                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       173858                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       133135                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       133135                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1596886                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1596886                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1561841                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1561841                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    133013409                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       133013409                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    133187267                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      133187267                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2622769                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      2622769                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1185607                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1185607                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       553155                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       553155                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       697992                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       697992                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145021                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       145021                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       178721                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       178721                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3808376                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3808376                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4361531                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4361531                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36725560788                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  36725560788                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  18496940456                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  18496940456                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  11951080104                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  11951080104                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2007745317                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2007745317                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3807661334                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3807661334                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       927000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       927000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  55222501244                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  55222501244                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  55222501244                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  55222501244                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     72222721                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     72222721                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     64599064                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     64599064                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       727013                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       727013                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       831127                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total       831127                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1741907                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1741907                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1740562                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1740562                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    136821785                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    136821785                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    137548798                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    137548798                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036315                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036315                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018353                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018353                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.760860                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760860                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.839814                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.839814                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083254                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083254                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.102680                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.102680                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027835                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.027835                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031709                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.031709                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                 887570                       # number of fast writes performed
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3048439                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3048439                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        28957                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        28957                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21342                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21342                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43075                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43075                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        50299                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        50299                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        50299                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        50299                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2991561                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2991561                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1334553                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1334553                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       637409                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       637409                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113761                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113761                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194186                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       194186                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4326114                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4326114                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4963523                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4963523                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  36853741584                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  36853741584                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  20599874090                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  20599874090                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14249969925                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14249969925                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  39555111210                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  39555111210                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1322683967                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1322683967                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3736995367                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3736995367                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1491000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1491000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  57453615674                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  57453615674                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  71703585599                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  71703585599                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2269904707                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2269904707                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2228690449                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2228690449                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4498595156                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4498595156                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035672                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035672                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017627                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017627                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.772551                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.772551                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056442                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056442                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.096404                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.096404                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027111                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027111                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030945                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.030945                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3276433                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3276433                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        20828                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        20828                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21424                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21424                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        36174                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        36174                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        42252                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        42252                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        42252                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        42252                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2601941                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2601941                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1164183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1164183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       551435                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       551435                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       697992                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       697992                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       108847                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       108847                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       178721                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       178721                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3766124                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      3766124                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4317559                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4317559                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30561578872                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30561578872                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  15647124797                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  15647124797                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  11524265112                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  11524265112                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  10542114896                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  10542114896                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1234908207                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1234908207                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3440508666                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3440508666                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       879000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       879000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  46208703669                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  46208703669                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  57732968781                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  57732968781                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2384094697                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2384094697                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2386757695                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2386757695                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4770852392                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4770852392                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036027                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036027                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018022                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018022                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758494                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758494                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.839814                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.839814                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062487                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062487                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.102680                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.102680                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027526                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027526                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031389                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031389                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -722,58 +732,59 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5136279                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.921269                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          454548902                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5136791                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            88.488884                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      24248022750                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.921269                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999846                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          4269396                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.932974                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          393605012                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          4269908                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            92.181146                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      18918806750                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932974                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999869                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          222                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        924508177                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       924508177                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    454548902                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      454548902                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    454548902                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       454548902                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    454548902                       # number of overall hits
-system.cpu0.icache.overall_hits::total      454548902                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5136791                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5136791                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5136791                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5136791                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5136791                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5136791                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  44728233484                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  44728233484                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  44728233484                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  44728233484                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  44728233484                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  44728233484                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    459685693                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    459685693                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    459685693                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    459685693                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    459685693                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    459685693                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011175                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011175                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011175                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011175                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011175                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011175                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8707.427163                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8707.427163                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8707.427163                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8707.427163                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8707.427163                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8707.427163                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        800019748                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       800019748                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    393605012                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      393605012                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    393605012                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       393605012                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    393605012                       # number of overall hits
+system.cpu0.icache.overall_hits::total      393605012                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      4269908                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      4269908                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      4269908                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       4269908                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      4269908                       # number of overall misses
+system.cpu0.icache.overall_misses::total      4269908                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  37643365597                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  37643365597                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  37643365597                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  37643365597                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  37643365597                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  37643365597                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    397874920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    397874920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    397874920                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    397874920                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    397874920                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    397874920                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010732                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.010732                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010732                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.010732                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010732                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.010732                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8815.966432                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8815.966432                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8815.966432                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8815.966432                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8815.966432                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8815.966432                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -782,365 +793,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5136791                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5136791                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5136791                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5136791                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5136791                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5136791                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  37020068050                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  37020068050                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  37020068050                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  37020068050                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  37020068050                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  37020068050                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4269908                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      4269908                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      4269908                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      4269908                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      4269908                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      4269908                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  31235618425                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  31235618425                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  31235618425                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  31235618425                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  31235618425                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  31235618425                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3405609750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   3405609750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011175                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011175                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011175                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7206.847242                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7206.847242                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7206.847242                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010732                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010732                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010732                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7315.290733                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  7315.290733                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  7315.290733                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     47709911                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       798067                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     44351595                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8146                       # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     45505774                       # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2657797                       # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     39900232                       # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8744                       # number of hwpf that were already in the prefetch queue
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          467                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2551636                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3941553                       # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          580                       # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2938421                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3808538                       # number of hwpf spanning a virtual page
 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         3159231                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16263.767973                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          10999510                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3175316                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.464068                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     20647851500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  3883.106993                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    48.905367                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    55.754013                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   900.341601                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2586.177603                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8789.482396                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.237006                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002985                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003403                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.054952                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.157848                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.536467                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.992662                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8304                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023          112                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7669                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           44                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          543                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2171                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5264                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          282                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.replacements         3291824                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16191.272385                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           9909292                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         3307923                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            2.995624                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     16044231500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  5217.724609                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    49.949148                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    58.574202                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   727.292976                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2667.900561                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7469.830889                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.318465                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003049                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003575                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.044390                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.162836                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.455922                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.988237                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8632                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7367                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           22                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          210                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1111                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         7012                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          277                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            6                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           43                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           59                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          738                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3430                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3305                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          150                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.506836                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006836                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.468079                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       240919913                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      240919913                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       231031                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       134927                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4959117                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data      2742170                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       8067245                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3048439                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3048439                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        86825                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        86825                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33826                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        33826                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       910939                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       910939                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       231031                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       134927                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4959117                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3653109                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8978184                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       231031                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       134927                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4959117                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3653109                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8978184                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12665                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11145                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       177674                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data      1000560                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total      1202044                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       109590                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       109590                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       160357                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       160357                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       232216                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       232216                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12665                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11145                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       177674                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1232776                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1434260                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12665                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11145                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       177674                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1232776                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1434260                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    536996706                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    703824955                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   4673573829                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  32218538016                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  38132933506                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2159798630                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2159798630                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3254740509                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3254740509                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1454999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1454999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  10558981803                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  10558981803                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    536996706                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    703824955                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4673573829                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  42777519819                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  48691915309                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    536996706                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    703824955                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4673573829                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  42777519819                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  48691915309                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       243696                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       146072                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5136791                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3742730                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      9269289                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3048439                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3048439                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       196415                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       196415                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194183                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       194183                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1143155                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1143155                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       243696                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       146072                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5136791                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4885885                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10412444                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       243696                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       146072                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5136791                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4885885                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10412444                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.034589                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.267334                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.129680                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.557951                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.557951                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.825803                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.825803                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           77                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1042                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         1532                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4604                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          127                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.526855                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.449646                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       215960486                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      215960486                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       166834                       # number of ReadReq hits
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+system.cpu0.l2cache.Writeback_hits::writebacks      3276433                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3276433                       # number of Writeback hits
+system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       610572                       # number of WriteInvalidateReq hits
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+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        75583                       # number of UpgradeReq hits
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+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31346                       # number of SCUpgradeReq hits
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+system.cpu0.l2cache.overall_hits::cpu0.data      3205178                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       7583453                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9451                       # number of ReadReq misses
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+system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data        86357                       # number of WriteInvalidateReq misses
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+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       147374                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9451                       # number of overall misses
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+system.cpu0.l2cache.overall_misses::total      1226556                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    247144715                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    215825476                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   4449371565                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  25701723776                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total  30614065532                       # number of ReadReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data   5651418353                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total   5651418353                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2080242902                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2080242902                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2994303005                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2994303005                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       855000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       855000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   6538293027                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   6538293027                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    247144715                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    215825476                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.data  32240016803                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.data  32240016803                       # number of overall miss cycles
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+system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3262221                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      7822505                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3276433                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3276433                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       696929                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::total       182479                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       178720                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       178720                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
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+system.cpu0.l2cache.overall_accesses::total      8810009                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.053612                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.267174                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.134687                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.123911                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.123911                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.585799                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.585799                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.824608                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.824608                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.203136                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.203136                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034589                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252314                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.137745                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034589                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252314                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.137745                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26304.207869                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32200.505733                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31723.409048                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19707.990054                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19707.990054                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20296.840855                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20296.840855                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 484999.666667                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 484999.666667                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45470.517979                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45470.517979                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26304.207869                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34700.156248                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 33949.155180                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26304.207869                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34700.156248                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 33949.155180                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        12605                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.175156                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.175156                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.053612                       # miss rate for demand accesses
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+system.cpu0.l2cache.overall_miss_rate::total     0.139223                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26150.112686                       # average ReadReq miss latency
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+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26971.609523                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29488.657124                       # average ReadReq miss latency
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+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 65442.504406                       # average WriteInvalidateReq miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19460.437266                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20317.715506                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20317.715506                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       855000                       # average SCUpgradeFailReq miss latency
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+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37800.811872                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37800.811872                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26150.112686                       # average overall miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 30865.070507                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 30289.981508                       # average overall miss latency
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+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 30865.070507                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 30289.981508                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs        52335                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs             256                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs             662                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    49.238281                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    79.055891                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1033934                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1033934                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        26777                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         5375                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total        32152                       # number of ReadReq MSHR hits
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2157592792                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5219457542                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2114914551                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2114914551                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2268405055                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4272507343                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7334372093                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.265898                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.126212                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4536939856                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7598804606                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.032837                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.265568                       # mshr miss rate for ReadReq accesses
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 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.557951                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.557951                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.825803                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.825803                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.070057                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.070057                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.585799                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.585799                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.824608                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.824608                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.198807                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.198807                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.250201                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.134182                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.250201                       # mshr miss rate for overall accesses
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+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.172158                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.032837                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.243863                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.135483                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for overall accesses
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+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.243863                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.379230                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.469001                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       687000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       687000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1150,58 +1180,58 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      12709886                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9530898                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        15163                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        15163                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3048439                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      3732092                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       887570                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       380241                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       351950                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       457079                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1289201                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1150842                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     10359832                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15601688                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       325277                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       566209                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         26853006                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    328927124                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    571100341                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1168576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1949568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         903145609                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    8562261                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     23134597                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.358060                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.479430                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      11465749                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      8074092                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        15773                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        15773                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      3276433                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      4228803                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       811507                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       696929                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       407420                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       328722                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       423022                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1108208                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       995011                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      8626066                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     14109371                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       260774                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       426575                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         23422786                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    273446612                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    532438419                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       912728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1410280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         808208039                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    8581549                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     21569506                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.385644                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.486747                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          14851033     64.19%     64.19% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6           8283564     35.81%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          13251364     61.44%     61.44% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6           8318142     38.56%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      23134597                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   11405856452                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      21569506                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   10644176370                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    183601993                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    173370992                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7759954717                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   6459583336                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8048372726                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   6973558574                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    179758799                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    146771777                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    322845049                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    250366041                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -1226,25 +1256,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    81769828                       # DTB read hits
-system.cpu1.dtb.read_misses                     79673                       # DTB read misses
-system.cpu1.dtb.write_hits                   74311746                       # DTB write hits
-system.cpu1.dtb.write_misses                    27355                       # DTB write misses
+system.cpu1.dtb.read_hits                    84980512                       # DTB read hits
+system.cpu1.dtb.read_misses                     74547                       # DTB read misses
+system.cpu1.dtb.write_hits                   77969612                       # DTB write hits
+system.cpu1.dtb.write_misses                    26781                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   41105                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37319                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4547                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4156                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10770                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                81849501                       # DTB read accesses
-system.cpu1.dtb.write_accesses               74339101                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10210                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                85055059                       # DTB read accesses
+system.cpu1.dtb.write_accesses               77996393                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        156081574                       # DTB hits
-system.cpu1.dtb.misses                         107028                       # DTB misses
-system.cpu1.dtb.accesses                    156188602                       # DTB accesses
+system.cpu1.dtb.hits                        162950124                       # DTB hits
+system.cpu1.dtb.misses                         101328                       # DTB misses
+system.cpu1.dtb.accesses                    163051452                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1266,283 +1296,295 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   434473512                       # ITB inst hits
-system.cpu1.itb.inst_misses                     57336                       # ITB inst misses
+system.cpu1.itb.inst_hits                   447940407                       # ITB inst hits
+system.cpu1.itb.inst_misses                     68561                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   28749                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26339                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               434530848                       # ITB inst accesses
-system.cpu1.itb.hits                        434473512                       # DTB hits
-system.cpu1.itb.misses                          57336                       # DTB misses
-system.cpu1.itb.accesses                    434530848                       # DTB accesses
-system.cpu1.numCycles                     95132031696                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               448008968                       # ITB inst accesses
+system.cpu1.itb.hits                        447940407                       # DTB hits
+system.cpu1.itb.misses                          68561                       # DTB misses
+system.cpu1.itb.accesses                    448008968                       # DTB accesses
+system.cpu1.numCycles                     94796862537                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  434160856                       # Number of instructions committed
-system.cpu1.committedOps                    511722288                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            470175639                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                456535                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26230713                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     66122636                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   470175639                       # number of integer instructions
-system.cpu1.num_fp_insts                       456535                       # number of float instructions
-system.cpu1.num_int_register_reads          688104482                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         373632663                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              726332                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             408756                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           113709240                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          113476936                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    156073929                       # number of memory refs
-system.cpu1.num_load_insts                   81768358                       # Number of load instructions
-system.cpu1.num_store_insts                  74305571                       # Number of store instructions
-system.cpu1.num_idle_cycles              94082707842.004028                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1049323853.995978                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011030                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988970                       # Percentage of idle cycles
-system.cpu1.Branches                         96877428                       # Number of branches fetched
+system.cpu1.committedInsts                  447645202                       # Number of instructions committed
+system.cpu1.committedOps                    528119835                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            486291398                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                624474                       # Number of float alu accesses
+system.cpu1.num_func_calls                   27450761                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     67545606                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   486291398                       # number of integer instructions
+system.cpu1.num_fp_insts                       624474                       # number of float instructions
+system.cpu1.num_int_register_reads          698728829                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         384530758                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              985803                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             576512                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           114161169                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          113813296                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    162934099                       # number of memory refs
+system.cpu1.num_load_insts                   84972579                       # Number of load instructions
+system.cpu1.num_store_insts                  77961520                       # Number of store instructions
+system.cpu1.num_idle_cycles              93770083152.566025                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1026779384.433978                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010831                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989169                       # Percentage of idle cycles
+system.cpu1.Branches                        100081816                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                354755827     69.28%     69.28% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1081291      0.21%     69.49% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    57437      0.01%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             66526      0.01%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu1.op_class::MemRead                81768358     15.97%     85.49% # Class of executed instruction
-system.cpu1.op_class::MemWrite               74305571     14.51%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                364276895     68.94%     68.94% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1051011      0.20%     69.14% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    60606      0.01%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             92495      0.02%     69.17% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.17% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.17% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.17% # Class of executed instruction
+system.cpu1.op_class::MemRead                84972579     16.08%     85.25% # Class of executed instruction
+system.cpu1.op_class::MemWrite               77961520     14.75%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 512035053                       # Class of executed instruction
+system.cpu1.op_class::total                 528415149                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13728                       # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements          5229569                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          446.555743                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          150635340                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5230081                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.801722                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8374220312000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   446.555743                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.872179                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.872179                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   13701                       # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements          5194711                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          457.134068                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          157559099                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5195223                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.327687                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8367548601000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.134068                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.892840                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.892840                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          408                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        317363377                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       317363377                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     76086699                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       76086699                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     70396756                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      70396756                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188905                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       188905                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       685307                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       685307                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1701097                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1701097                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1676869                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1676869                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    146483455                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       146483455                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    146672360                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      146672360                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2949268                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2949268                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1324938                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1324938                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       648778                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       648778                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       170596                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       170596                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193531                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       193531                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4274206                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4274206                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      4922984                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      4922984                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43925732439                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  43925732439                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  22816644952                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  22816644952                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2487645065                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2487645065                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4103865813                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4103865813                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1896000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1896000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  66742377391                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  66742377391                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  66742377391                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  66742377391                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     79035967                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     79035967                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     71721694                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     71721694                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       837683                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       837683                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       685307                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       685307                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1871693                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1871693                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1870400                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1870400                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    150757661                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    150757661                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    151595344                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    151595344                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037316                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.037316                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018473                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018473                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.774491                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.774491                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091145                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091145                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103470                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103470                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028352                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.028352                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032475                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.032475                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        331059949                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       331059949                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     79405575                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       79405575                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     74066119                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      74066119                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       191889                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       191889                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       197632                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total       197632                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1669680                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1669680                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1654141                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1654141                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    153471694                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       153471694                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    153663583                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      153663583                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2946837                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2946837                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1283113                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1283113                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       571898                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       571898                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       550709                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       550709                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       171203                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       171203                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       185528                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       185528                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4229950                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4229950                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      4801848                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      4801848                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  41215882509                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  41215882509                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  19312866378                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  19312866378                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data   6595698094                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total   6595698094                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2383654561                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2383654561                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3901847697                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3901847697                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1095500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1095500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  60528748887                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  60528748887                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  60528748887                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  60528748887                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     82352412                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     82352412                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     75349232                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     75349232                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       763787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       763787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       748341                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       748341                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1840883                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1840883                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1839669                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1839669                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    157701644                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    157701644                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    158465431                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    158465431                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035783                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017029                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.017029                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.748766                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.748766                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.735906                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.735906                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.093000                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.093000                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100849                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100849                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026822                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026822                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.030302                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.030302                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                 685307                       # number of fast writes performed
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      2978181                       # number of writebacks
-system.cpu1.dcache.writebacks::total          2978181                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        23865                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        23865                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          515                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          515                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45192                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45192                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        24380                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        24380                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        24380                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        24380                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2925403                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2925403                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1324423                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1324423                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       648778                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       648778                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       125404                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       125404                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193531                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       193531                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4249826                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4249826                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4898604                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4898604                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36900792539                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36900792539                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20082419307                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20082419307                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13833136236                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13833136236                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  30583171682                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  30583171682                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1453819204                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1453819204                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3706136187                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3706136187                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1808000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1808000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  56983211846                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  56983211846                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  70816348082                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  70816348082                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4114514480                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4114514480                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3994198470                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3994198470                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8108712950                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8108712950                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037014                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037014                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018466                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018466                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.774491                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.774491                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103470                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103470                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028190                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028190                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032314                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032314                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3397427                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3397427                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14736                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        14736                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          407                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          407                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        48814                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        48814                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        15143                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        15143                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        15143                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        15143                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2932101                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2932101                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1282706                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1282706                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       571898                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       571898                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       550709                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       550709                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       122389                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       122389                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       185528                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       185528                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4214807                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4214807                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4786705                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4786705                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  34665979416                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  34665979416                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  16693598628                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  16693598628                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11612454284                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11612454284                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   5490664906                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total   5490664906                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1373965707                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1373965707                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3521472303                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3521472303                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1037500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1037500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  51359578044                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  51359578044                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  62972032328                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  62972032328                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3972621225                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3972621225                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3807943973                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3807943973                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7780565198                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7780565198                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035604                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035604                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017023                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017023                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.748766                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.748766                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.735906                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.735906                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066484                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066484                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100849                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100849                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026726                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026726                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030207                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.030207                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data  9970.174640                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total  9970.174640                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1550,59 +1592,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          4838786                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.335132                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          429634209                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4839298                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            88.780275                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8374030789000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.335132                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969405                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969405                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5786522                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.339295                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          442153368                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5787034                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            76.404142                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8367526246000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.339295                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969413                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969413                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        873786327                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       873786327                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    429634209                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      429634209                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    429634209                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       429634209                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    429634209                       # number of overall hits
-system.cpu1.icache.overall_hits::total      429634209                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4839303                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4839303                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4839303                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4839303                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4839303                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4839303                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  42201450669                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  42201450669                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  42201450669                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  42201450669                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  42201450669                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  42201450669                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    434473512                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    434473512                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    434473512                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    434473512                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    434473512                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    434473512                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011138                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.011138                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011138                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.011138                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011138                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.011138                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8720.563823                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8720.563823                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8720.563823                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8720.563823                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8720.563823                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8720.563823                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        901667853                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       901667853                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    442153368                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      442153368                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    442153368                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       442153368                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    442153368                       # number of overall hits
+system.cpu1.icache.overall_hits::total      442153368                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5787039                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5787039                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5787039                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5787039                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5787039                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5787039                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  50052191468                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  50052191468                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  50052191468                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  50052191468                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  50052191468                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  50052191468                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    447940407                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    447940407                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    447940407                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    447940407                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    447940407                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    447940407                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.012919                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.012919                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.012919                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.012919                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.012919                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.012919                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8649.015752                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8649.015752                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8649.015752                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8649.015752                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8649.015752                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8649.015752                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1611,367 +1653,384 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4839303                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      4839303                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      4839303                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      4839303                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      4839303                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      4839303                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  34939638885                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  34939638885                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  34939638885                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  34939638885                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  34939638885                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  34939638885                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8745500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8745500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011138                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.011138                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.011138                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7219.973390                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  7219.973390                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  7219.973390                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5787039                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5787039                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5787039                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5787039                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5787039                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5787039                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  41368714588                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  41368714588                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  41368714588                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  41368714588                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  41368714588                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  41368714588                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9075250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9075250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9075250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9075250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.012919                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.012919                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.012919                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7148.511456                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  7148.511456                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  7148.511456                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     45129085                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       818764                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     41906843                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8141                       # number of hwpf that were already in the prefetch queue
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     55302288                       # number of hwpf identified
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       976452                       # number of hwpf that were already in mshr
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     51578919                       # number of hwpf that were already in the cache
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9282                       # number of hwpf that were already in the prefetch queue
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          514                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2394823                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3842139                       # number of hwpf spanning a virtual page
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          584                       # number of hwpf removed because MSHR allocated
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2737051                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4557576                       # number of hwpf spanning a virtual page
 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         3029134                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13674.379805                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          10606046                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         3045261                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            3.482804                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10454752865000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4179.016177                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    54.517433                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    70.326677                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   591.513668                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3188.927208                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  5590.078642                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.255067                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003327                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004292                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036103                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.194637                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.341191                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.834618                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8556                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         7510                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           76                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          438                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         3359                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4072                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          611                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           28                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2836                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3841                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          307                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.522217                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.458374                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       230495604                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      230495604                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       221576                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       129888                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4667071                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2714218                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       7732753                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      2978176                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      2978176                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        79936                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        79936                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35720                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        35720                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       908771                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       908771                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       221576                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       129888                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4667071                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3622989                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8641524                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       221576                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       129888                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4667071                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3622989                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8641524                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12665                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        11221                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       172232                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data       985367                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1181485                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       109801                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       109801                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       157805                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       157805                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       226147                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       226147                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12665                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11221                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       172232                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1211514                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1407632                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12665                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11221                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       172232                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1211514                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1407632                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    578928201                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    733432437                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   4494366580                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  32191641510                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  37998368728                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2189702140                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2189702140                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3225705678                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3225705678                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1763999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1763999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10153420884                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10153420884                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    578928201                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    733432437                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   4494366580                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  42345062394                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  48151789612                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    578928201                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    733432437                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   4494366580                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  42345062394                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  48151789612                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       234241                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       141109                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4839303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3699585                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total      8914238                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      2978176                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      2978176                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       189737                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       189737                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193525                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       193525                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1134918                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1134918                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       234241                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       141109                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      4839303                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4834503                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10049156                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       234241                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       141109                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      4839303                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4834503                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10049156                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.054068                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.079520                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.035590                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.266345                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.132539                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.578701                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.578701                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.815424                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.815424                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.tags.replacements         3265247                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13732.593717                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          11929802                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         3281353                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            3.635635                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9719592338000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  3548.297662                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    58.425503                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    65.675774                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   758.406628                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2477.157386                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6824.630764                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.216571                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003566                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004009                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.046289                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.151194                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.416542                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.838171                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8592                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           40                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024         7474                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           93                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          541                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         2721                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4842                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          395                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          810                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3409                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2963                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          229                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.524414                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002441                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.456177                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       249010603                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      249010603                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       204488                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       158918                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5602514                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.data      2695724                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total       8661644                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3397427                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3397427                       # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       491178                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total       491178                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        77109                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        77109                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35497                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        35497                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       899510                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       899510                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       204488                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       158918                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5602514                       # number of demand (read+write) hits
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+system.cpu1.l2cache.Writeback_accesses::writebacks      3397427                       # number of Writeback accesses(hits+misses)
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+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.591620                       # miss rate for UpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.199263                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.199263                       # miss rate for ReadExReq accesses
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-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.250597                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.140075                       # miss rate for demand accesses
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-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.250597                       # miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32669.697189                       # average ReadReq miss latency
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-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19942.460815                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20441.086645                       # average SCUpgradeReq miss latency
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-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44897.437879                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44897.437879                       # average ReadExReq miss latency
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-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34952.185773                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34207.654850                       # average overall miss latency
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-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26094.840564                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34952.185773                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34207.654850                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         6147                       # number of cycles access was blocked
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 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs             166                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs             326                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    37.030120                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    39.996933                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       960563                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          960563                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        26607                       # number of ReadReq MSHR hits
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-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7001                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.ReadReq_mshr_misses::total      1153966                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2394712                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total      2394712                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       109801                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       109801                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       157805                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       157805                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
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-system.cpu1.l2cache.ReadExReq_mshr_misses::total       220058                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12665                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        11221                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       145625                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1204513                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total      3768736                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    489322313                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   3045903499                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  25194010676                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  29382774555                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  71059948043                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  71059948043                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  25441892262                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25441892262                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   1899234087                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   1899234087                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2195015270                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2195015270                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1455999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1455999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7950904534                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7950904534                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    489322313                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   3045903499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33144915210                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  37333679089                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   3045903499                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33144915210                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total 108393627132                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3918463269                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3926347769                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3819021030                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3819021030                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7737484299                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7745368799                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.266099                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.129452                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks      1118692                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1118692                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        28597                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       111708                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       150027                       # number of SCUpgradeReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   1851219395                       # number of UpgradeReq MSHR miss cycles
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+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2073994150                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       805500                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   5288290642                       # number of ReadExReq MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26545800160                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  69697772473                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 100044165436                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8211750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3785003026                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3793214776                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3642241027                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3642241027                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8211750                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7427244053                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7435455803                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.256472                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.112967                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.578701                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.578701                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.815424                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.815424                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.087836                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.087836                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.591620                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.591620                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808666                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808666                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.193898                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.193898                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.249149                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136730                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.249149                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.176371                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.176371                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.237888                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119344                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.237888                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.375030                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.370592                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       201375                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       201375                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1981,65 +2040,65 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      12427806                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9137324                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        23353                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        23353                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      2978176                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      3478890                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       685307                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       370922                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       353849                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       446809                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1290596                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1141918                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9678826                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15042396                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       312565                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       544877                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         25578664                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    309715832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    550341480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1128872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1873928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         863060112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    8621982                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     22555543                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.370325                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.482892                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq      13482596                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10019474                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        22090                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        22090                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3397427                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      3948207                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       669175                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       549365                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       394300                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       332875                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       429984                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           28                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1203009                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1101184                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11574298                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     14922836                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       373561                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       511408                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         27382103                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    370370936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    560535931                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1349320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1724480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         933980667                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    8332859                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     23404111                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.344949                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.475352                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          14202655     62.97%     62.97% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6           8352888     37.03%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          15330876     65.51%     65.51% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6           8073235     34.49%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      22555543                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   10801104660                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      23404111                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   11646725084                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    179932994                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    158989494                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7260511142                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8682146940                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7881710673                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7623277083                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    172097315                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    205120292                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    311084554                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    296049290                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40536                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40536                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              137093                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             137147                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq           54                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48328                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40487                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40487                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              137083                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30163                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106920                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48390                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2049,18 +2108,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123470                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231816                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231816                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123480                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231580                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231580                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  355366                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48348                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  355140                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2070,18 +2129,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156485                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355616                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156518                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7351088                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7351088                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7514187                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36745000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7509692                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36789000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2101,7 +2160,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            22142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            22103000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2109,678 +2168,707 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           984235192                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1044839337                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93310000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            93320000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179557795                       # Layer occupancy (ticks)
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 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
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 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
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 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
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 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
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 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 219038.930365                       # average ReadReq miss latency
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 220564.510161                       # average ReadReq miss latency
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 system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 219307.581242                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 219005.450134                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 219307.581242                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 219005.450134                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         53861                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       149600                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 220850.179481                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 220530.313356                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       149600                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 220850.179481                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 220530.313356                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        225288                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27401                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.810747                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.221890                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106984                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106886                       # number of writebacks
+system.iocache.writebacks::total               106886                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8924                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8961                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8870                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8907                       # number of ReadReq MSHR misses
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 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106920                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106920                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8924                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8964                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8870                       # number of demand (read+write) MSHR misses
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-system.iocache.overall_mshr_misses::realview.ide         8924                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8964                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1492924359                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1496707359                       # number of ReadReq MSHR miss cycles
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+system.iocache.overall_mshr_misses::total         8910                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3703000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1497575112                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1501278112                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6628374628                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6628374628                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1492924359                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1496908359                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1492924359                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1496908359                       # number of overall MSHR miss cycles
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+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23337113496                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3904000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1497575112                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1501479112                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3904000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1497575112                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1501479112                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
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 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166991.115462                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166991.115462                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        97600                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 168516.174186                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        97600                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 168516.174186                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1086855                       # number of replacements
-system.l2c.tags.tagsinuse                64099.647179                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6672114                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1148598                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     5.808920                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    9469.927163                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    51.211523                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    68.031290                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      696.373428                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3179.738420                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   291.904824                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   401.470147                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      563.131009                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    10017.603756                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.144500                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000781                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.001038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.010626                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.048519                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.273804                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004454                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006126                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008593                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.152857                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.326786                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.978083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        31587                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          309                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        29847                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0            9                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1          114                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1585                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4136                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        25743                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            9                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2           33                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           47                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          219                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1360                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9152                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        19154                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.481979                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004715                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.455429                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 80637866                       # Number of tag accesses
-system.l2c.tags.data_accesses                80637866                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         6250                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4321                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             142068                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             620262                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1618371                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6096                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         4059                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             137369                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             611754                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1545913                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                4696463                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1994497                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1994497                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           23769                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           27954                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               51723                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          7971                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          7653                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             15624                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            52432                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            49853                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               102285                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6250                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4321                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              142068                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              672694                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher      1618371                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6096                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4059                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              137369                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              661607                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher      1545913                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 4798748                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6250                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4321                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             142068                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             672694                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher      1618371                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6096                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4059                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             137369                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             661607                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher      1545913                       # number of overall hits
-system.l2c.overall_hits::total                4798748                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         3647                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         6386                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             8946                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           136148                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       441016                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         4242                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         6837                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             8364                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           140626                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       418325                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total              1174537                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         34627                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         36381                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             71008                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10699                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11055                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           21754                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          78297                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          72282                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             150579                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3647                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         6386                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              8946                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            214445                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       441016                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         4242                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         6837                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              8364                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            212908                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       418325                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1325116                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3647                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         6386                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             8946                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           214445                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       441016                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         4242                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         6837                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             8364                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           212908                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       418325                       # number of overall misses
-system.l2c.overall_misses::total              1325116                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    290095498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    510585994                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    795450996                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  11077065870                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    335992750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    542306996                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    742040494                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  11432821383                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total   116290930305                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    147041544                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    142085765                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    289127309                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     51916806                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     56203152                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    108119958                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5726616061                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5297244481                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11023860542                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    290095498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    510585994                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    795450996                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  16803681931                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    335992750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    542306996                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    742040494                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  16730065864                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    127314790847                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    290095498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    510585994                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    795450996                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  16803681931                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    335992750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    542306996                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    742040494                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  16730065864                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   127314790847                       # number of overall miss cycles
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-system.l2c.ReadReq_accesses::cpu0.itb.walker        10707                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         151014                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         756410                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2059387                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10338                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        10896                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         145733                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         752380                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total            5871000                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1994497                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1994497                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        58396                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        64335                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          122731                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        18670                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::total         37378                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.itb.walker        10707                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          151014                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          887139                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2059387                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.itb.walker        10896                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          145733                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          874515                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher      1964238                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.inst         151014                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         887139                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2059387                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.itb.walker        10896                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         145733                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         874515                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher      1964238                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            6123864                       # number of overall (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.059240                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.179992                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.057393                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.186908                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.200057                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.592969                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.565493                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.578566                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.573058                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590924                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.582000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.598926                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.591821                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.595494                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.368496                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.059240                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.241726                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.057393                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.243458                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.216386                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.368496                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.059240                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.241726                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.057393                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.243458                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.216386                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 88916.945674                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 81360.474410                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88718.375658                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 81299.485038                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 99010.018675                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4246.441909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3905.493664                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4071.756830                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4852.491448                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5083.957666                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4970.118507                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73139.661302                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73285.803948                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73209.813732                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 88916.945674                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 78358.935536                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 88718.375658                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 78578.850320                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 96078.223225                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 88916.945674                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 78358.935536                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 88718.375658                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 78578.850320                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 96078.223225                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              2524                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1310456                       # number of replacements
+system.l2c.tags.tagsinuse                64677.337118                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    7257968                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1373726                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     5.283418                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               5621833500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    9998.305247                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    56.991260                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    77.146603                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      791.679733                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4513.780403                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   150.211809                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   222.184258                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      784.998757                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     7219.989726                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.152562                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000870                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001177                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.012080                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.068875                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.363444                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002292                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003390                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.011978                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.110168                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.260061                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.986898                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        38915                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          205                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        24150                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           26                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          487                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         8729                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        29647                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          188                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5282                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        18136                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.593796                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003128                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.368500                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 74054042                       # Number of tag accesses
+system.l2c.tags.data_accesses                74054042                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         5514                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         4407                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu0.data             549137                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.itb.walker         6374                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.data             607953                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1853450                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                4964901                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         2477309                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2477309                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data         3452                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::cpu1.data         4029                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::total         7481                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.data           31717                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           34608                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               66325                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          7299                       # number of SCUpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::total             15892                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            45918                       # number of ReadExReq hits
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+system.l2c.ReadExReq_hits::total               105573                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5514                       # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu1.dtb.walker         7096                       # number of overall hits
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+system.l2c.overall_hits::cpu1.data             667608                       # number of overall hits
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+system.l2c.overall_hits::total                5070474                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker          569                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker          656                       # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu0.data            87213                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       698997                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker         1304                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker         1531                       # number of ReadReq misses
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+system.l2c.ReadReq_misses::total              1237733                       # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.data         9435                       # number of WriteInvalidateReq misses
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+system.l2c.WriteInvalidateReq_misses::total        13061                       # number of WriteInvalidateReq misses
+system.l2c.UpgradeReq_misses::cpu0.data         30881                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         31286                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             62167                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         9976                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::total              75823                       # number of ReadExReq misses
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+system.l2c.overall_miss_latency::cpu1.itb.walker    124997499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    812177995                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  10713178263                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  38448513875                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   161142785750                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         6083                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         5063                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         140315                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         636350                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2352132                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         8400                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         7905                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         156047                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         707940                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2182399                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            6202634                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      2477309                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2477309                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data        12887                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu1.data         7655                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::total        20542                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        62598                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        65894                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          128492                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        17275                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        18192                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         35467                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        84403                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        96993                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           181396                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         6083                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5063                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          140315                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          720753                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2352132                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         8400                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7905                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          156047                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          804933                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2182399                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             6384030                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         6083                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5063                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         140315                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         720753                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2352132                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         8400                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7905                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         156047                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         804933                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2182399                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            6384030                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.066379                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.137052                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.059040                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.141237                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.199550                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.732133                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.473677                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.635819                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.493322                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.474793                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.483820                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.577482                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.527650                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.551922                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.455967                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.384956                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.417997                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.066379                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.174398                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.059040                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.170604                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.205757                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.066379                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.174398                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.059040                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.170604                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.205757                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 90745.731265                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 81075.836687                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88155.649083                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 79829.484813                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 125684.206842                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   195.063169                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   571.266133                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   299.504785                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4347.525015                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4533.993352                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4441.366577                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4938.694266                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5142.455568                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5038.612771                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74003.580564                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73149.808908                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 73583.152381                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 90745.731265                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 78910.521591                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 88155.649083                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 78013.313403                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 122676.753599                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 90745.731265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 78910.521591                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 88155.649083                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 78013.313403                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 122676.753599                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              4412                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       54                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       93                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     46.740741                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     47.440860                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              686491                       # number of writebacks
-system.l2c.writebacks::total                   686491                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst            30                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            24                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            14                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               551                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             30                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             24                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             14                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                551                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            30                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            24                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            14                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               551                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         3647                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         6386                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         8916                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       136124                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         4242                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         6837                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         8350                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       140614                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total         1173986                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        34627                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        36381                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        71008                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10699                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11055                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        21754                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        78297                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72282                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        150579                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3647                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         6386                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         8916                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       214421                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         4242                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         6837                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         8350                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       212896                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1324565                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3647                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         6386                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         8916                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       214421                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         4242                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         6837                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         8350                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       212896                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1324565                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    244781998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    431307994                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    682060496                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data   9367961184                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  40693405448                       # number of ReadReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of overall MSHR uncacheable cycles
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.565493                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.578566                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.573058                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590924                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.582000                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.591821                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.595494                       # mshr miss rate for ReadExReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.data     0.241699                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.627478                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.data     0.243445                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.212878                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.216296                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.368496                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.596432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.059041                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.241699                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.214009                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.410331                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.627478                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.057297                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.243445                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.212878                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.216296                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68819.320502                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 83682.306474                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 83682.306474                       # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005699250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6158750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6627525497                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12885580747                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.137025                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.141222                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.199502                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.732133                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.473677                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.635819                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.493322                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.474793                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.483820                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.577482                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.527650                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.551922                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.455967                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.384956                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.417997                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.174375                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.170592                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.205710                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.174375                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.170592                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.205710                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 110391.140090                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 110391.140090                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -2795,58 +2883,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             1264717                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1264717                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38516                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38516                       # Transaction distribution
-system.membus.trans_dist::Writeback            686491                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1679861                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1679861                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           316703                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         302467                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           96183                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            163141                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           147161                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123470                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq             1327465                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1327465                       # Transaction distribution
+system.membus.trans_dist::WriteReq              37863                       # Transaction distribution
+system.membus.trans_dist::WriteResp             37863                       # Transaction distribution
+system.membus.trans_dist::Writeback           1017207                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       119813                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       119813                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           367379                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         281461                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           85028                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             87184                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            72708                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25330                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      7297543                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      7446435                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       230140                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       230140                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7676575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156485                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        22714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4395675                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4541961                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       336541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4878502                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156518                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50660                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    229346740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    229554089                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7308288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7308288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               236862377                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           540732                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4331622                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        45428                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143082804                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    143284954                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14125504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14125504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               157410458                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           581037                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3119395                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4331622    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3119395    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4331622                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101146499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3119395                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101251489                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               55500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            22031996                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            19693498                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         23154905719                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         11963097483                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        14237686781                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        12443113804                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          187996205                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          187409729                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2857,11 +2945,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -2890,45 +2978,45 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            6727338                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           6719778                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38516                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38516                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1994497                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1572877                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          365008                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        318091                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         683099                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           80                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           301724                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          301724                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10020344                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9267363                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              19287707                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    322818441                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    297911776                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              620730217                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1454894                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         11304872                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.010257                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.100757                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            7096727                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7089473                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             37863                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            37863                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2477309                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       127465                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp        20542                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          430421                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        297353                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         727774                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           228196                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          228196                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8832957                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8435767                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17268724                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    294458407                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    274483891                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              568942298                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1532220                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         10576474                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.010952                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.104077                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               11188916     98.97%     98.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115956      1.03%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10460641     98.90%     98.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115833      1.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           11304872                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        19960086799                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           10576474                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        15316484616                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          6306000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          7440499                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       16653624789                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       16737915607                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       15972471023                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       16438547163                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index c88d045b6..e087cdc41 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,140 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.781056                       # Number of seconds simulated
-sim_ticks                                51781056074000                       # Number of ticks simulated
-final_tick                               51781056074000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.821204                       # Number of seconds simulated
+sim_ticks                                51821203872000                       # Number of ticks simulated
+final_tick                               51821203872000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 717486                       # Simulator instruction rate (inst/s)
-host_op_rate                                   843154                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            44175728553                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 650840                       # Number of bytes of host memory used
-host_seconds                                  1172.16                       # Real time elapsed on the host
-sim_insts                                   841009423                       # Number of instructions simulated
-sim_ops                                     988312418                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 797175                       # Simulator instruction rate (inst/s)
+host_op_rate                                   936716                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            46008450754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 656028                       # Number of bytes of host memory used
+host_seconds                                  1126.34                       # Real time elapsed on the host
+sim_insts                                   897890420                       # Number of instructions simulated
+sim_ops                                    1055061464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::realview.ide        385216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker       437760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       790272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           4324596                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          53060296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             58998140                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      4324596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4324596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     30687936                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data       99485540                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         136999972                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6019                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker         6840                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker        12348                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             107979                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             829080                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                962266                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          479499                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data           1556713                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2142876                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             7439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           8454                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker          15262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst                83517                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1024705                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1139377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           83517                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              83517                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            592648                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          131834                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1921273                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2645755                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            592648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          139273                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          8454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker         15262                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               83517                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2945978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3785132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        962266                       # Number of read requests accepted
-system.physmem.writeReqs                      2142876                       # Number of write requests accepted
-system.physmem.readBursts                      962266                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2142876                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 61369728                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    215296                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 132432768                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  58998140                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              136999972                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     3364                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   73592                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          33443                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               65026                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               59757                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               57697                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               55201                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               59686                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               66424                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               54909                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               46752                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               56185                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              105428                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              56738                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              56925                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              52656                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              52461                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              54958                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              58099                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              127089                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              113639                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              227284                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              120346                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              128596                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              124885                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              105979                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               88244                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              113178                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              146103                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             105873                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             119118                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             106014                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             144894                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             168059                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             129961                       # Per bank write bursts
+system.physmem.bytes_read::cpu.dtb.walker       274944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       280896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5219828                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          52654408                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        402752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             58832828                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5219828                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5219828                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     79485888                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          79506468                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         4296                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         4389                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             121967                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             822738                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6293                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                959683                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1241967                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1244540                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           5306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           5420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               100728                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1016078                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7772                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1135304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          100728                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             100728                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1533849                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1534246                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1533849                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          5306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          5420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              100728                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1016476                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7772                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2669550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        959683                       # Number of read requests accepted
+system.physmem.writeReqs                      1860672                       # Number of write requests accepted
+system.physmem.readBursts                      959683                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1860672                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 61376064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 118595648                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  58832828                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              118938916                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      682                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7593                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          36288                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               56975                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               58359                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               58716                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               57264                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               61545                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               66145                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               57228                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               52937                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               52189                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               99547                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              57680                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              61393                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              54506                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              60286                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              51564                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              52667                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              114739                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              115397                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              117633                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              119136                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              120318                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              121968                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              116613                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              113695                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              109286                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              116370                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             115629                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             118249                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             111968                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             117797                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             110347                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             113912                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51781053518000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51821201316000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  919150                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  916567                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2140303                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    916619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36737                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       554                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       703                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       262                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       188                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      116                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       99                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       78                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       40                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1858099                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    925038                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     28111                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       593                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::7                       306                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       221                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       147                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       90                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -162,158 +159,157 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::18                   115210                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                   117814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   132602                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32                   104685                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::47                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      261                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::53                      123                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::56                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       43                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       577071                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      335.837219                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     186.071808                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     364.354794                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         225600     39.09%     39.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       129681     22.47%     61.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48337      8.38%     69.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        25344      4.39%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        16032      2.78%     77.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12773      2.21%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9903      1.72%     81.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        10527      1.82%     82.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        98874     17.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         577071                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples        103651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean         9.251131                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      174.136795                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047         103646    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::22528-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total          103651                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples        103651                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.963744                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.612401                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.068688                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           47209     45.55%     45.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23           51400     49.59%     95.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            1703      1.64%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1371      1.32%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             882      0.85%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             145      0.14%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             167      0.16%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              75      0.07%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              86      0.08%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.01%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              11      0.01%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.01%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             393      0.38%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              31      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              40      0.04%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              32      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              31      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              13      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total          103651                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10497513500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               28476926000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4794510000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10947.43                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::54                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       68                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       617611                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      291.399266                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     166.446996                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.841680                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         256797     41.58%     41.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       151085     24.46%     66.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        51876      8.40%     74.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        29038      4.70%     79.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        19766      3.20%     82.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        13229      2.14%     84.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10059      1.63%     86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9064      1.47%     87.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        76697     12.42%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         617611                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         92036                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        10.419705                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      106.178395                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          92034    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           92036                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         92036                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.134045                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.130429                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       10.695121                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           84651     91.98%     91.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            3801      4.13%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            1276      1.39%     97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             446      0.48%     97.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             607      0.66%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             136      0.15%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             198      0.22%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             105      0.11%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             166      0.18%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              53      0.06%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            197      0.21%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            35      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            54      0.06%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            56      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           137      0.15%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            24      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            33      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             9      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            16      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             8      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           92036                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12714966775                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30696235525                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4795005000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13258.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29697.43                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.56                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32008.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.29                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.14                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.65                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.30                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     723659                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1727431                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.48                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16675905.17                       # Average gap between requests
-system.physmem.pageHitRate                      80.94                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49473510377000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1729083200000                       # Time in different power states
+system.physmem.avgWrQLen                        23.23                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     722338                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1472108                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.32                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18373999.48                       # Average gap between requests
+system.physmem.pageHitRate                      78.04                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     49686658091000                       # Time in different power states
+system.physmem.memoryStateTime::REF      1730423760000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      578461163500                       # Time in different power states
+system.physmem.memoryStateTime::ACT      404121645500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2226745080                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2135911680                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1214989875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1165428000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               3630494400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               3848871000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              6713681760                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              6695136000                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3382086739200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3382086739200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1381227557085                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1374892031880                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29857029495750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29862586974000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34634129703150                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34633411091760                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.857174                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.843296                       # Core power per rank (mW)
+system.physmem.actEnergy::0                2414648880                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                2254490280                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                1317516750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                1230128625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0               3659518200                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1               3820650600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0              6087953520                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1              5919855840                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          3384708874560                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          3384708874560                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          1312804436175                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          1305168623550                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          29941137312000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          29947835393250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            34652130260085                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            34650938016705                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.686370                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.663363                       # Core power per rank (mW)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -330,191 +326,12 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              445419                       # Transaction distribution
-system.membus.trans_dist::ReadResp             445419                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33871                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33871                       # Transaction distribution
-system.membus.trans_dist::Writeback            479499                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1660804                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1660804                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33447                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           33449                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            553497                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           553497                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5572311                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5702495                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       228222                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       228222                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5930717                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    188786400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    188956724                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7211712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7211712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               196168436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2862                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3095773                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3095773    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3095773                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106099500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5682499                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         21134514240                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        11065598028                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186599963                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                40401                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40401                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136730                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136733                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            3                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230998                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230998                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334424                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334424                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492830                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           981107027                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179038037                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -539,25 +356,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    158219223                       # DTB read hits
-system.cpu.dtb.read_misses                     140465                       # DTB read misses
-system.cpu.dtb.write_hits                   143634632                       # DTB write hits
-system.cpu.dtb.write_misses                     49220                       # DTB write misses
+system.cpu.dtb.read_hits                    168646043                       # DTB read hits
+system.cpu.dtb.read_misses                     158497                       # DTB read misses
+system.cpu.dtb.write_hits                   153371607                       # DTB write hits
+system.cpu.dtb.write_misses                     56347                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               38918                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1015                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71391                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid               43049                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    74830                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   7071                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   7977                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     18891                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                158359688                       # DTB read accesses
-system.cpu.dtb.write_accesses               143683852                       # DTB write accesses
+system.cpu.dtb.perms_faults                     19966                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                168804540                       # DTB read accesses
+system.cpu.dtb.write_accesses               153427954                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         301853855                       # DTB hits
-system.cpu.dtb.misses                          189685                       # DTB misses
-system.cpu.dtb.accesses                     302043540                       # DTB accesses
+system.cpu.dtb.hits                         322017650                       # DTB hits
+system.cpu.dtb.misses                          214844                       # DTB misses
+system.cpu.dtb.accesses                     322232494                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -579,142 +396,348 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    841528845                       # ITB inst hits
-system.cpu.itb.inst_misses                     119634                       # ITB inst misses
+system.cpu.itb.inst_hits                    898442559                       # ITB inst hits
+system.cpu.itb.inst_misses                     123457                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               38918                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1015                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    51154                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               43049                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53017                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                841648479                       # ITB inst accesses
-system.cpu.itb.hits                         841528845                       # DTB hits
-system.cpu.itb.misses                          119634                       # DTB misses
-system.cpu.itb.accesses                     841648479                       # DTB accesses
-system.cpu.numCycles                     103562112148                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                898566016                       # ITB inst accesses
+system.cpu.itb.hits                         898442559                       # DTB hits
+system.cpu.itb.misses                          123457                       # DTB misses
+system.cpu.itb.accesses                     898566016                       # DTB accesses
+system.cpu.numCycles                     103642407744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   841009423                       # Number of instructions committed
-system.cpu.committedOps                     988312418                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             908272324                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 899019                       # Number of float alu accesses
-system.cpu.num_func_calls                    50313277                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    127741607                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    908272324                       # number of integer instructions
-system.cpu.num_fp_insts                        899019                       # number of float instructions
-system.cpu.num_int_register_reads          1317064952                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          720072212                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1450897                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              759632                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            218662872                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           218058310                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     301832909                       # number of memory refs
-system.cpu.num_load_insts                   158209551                       # Number of load instructions
-system.cpu.num_store_insts                  143623358                       # Number of store instructions
-system.cpu.num_idle_cycles               100527171614.894058                       # Number of idle cycles
-system.cpu.num_busy_cycles               3034940533.105942                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.029306                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.970694                       # Percentage of idle cycles
-system.cpu.Branches                         187669847                       # Number of branches fetched
+system.cpu.committedInsts                   897890420                       # Number of instructions committed
+system.cpu.committedOps                    1055061464                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             968615704                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 900077                       # Number of float alu accesses
+system.cpu.num_func_calls                    53165114                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    137212632                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    968615704                       # number of integer instructions
+system.cpu.num_fp_insts                        900077                       # number of float instructions
+system.cpu.num_int_register_reads          1413530400                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          768471074                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1450010                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              764580                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            236283447                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           235682818                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     322001322                       # number of memory refs
+system.cpu.num_load_insts                   168639088                       # Number of load instructions
+system.cpu.num_store_insts                  153362234                       # Number of store instructions
+system.cpu.num_idle_cycles               100472196154.122070                       # Number of idle cycles
+system.cpu.num_busy_cycles               3170211589.877939                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.030588                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.969412                       # Percentage of idle cycles
+system.cpu.Branches                         200577010                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 684692132     69.24%     69.24% # Class of executed instruction
-system.cpu.op_class::IntMult                  2140683      0.22%     69.46% # Class of executed instruction
-system.cpu.op_class::IntDiv                     96951      0.01%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             112246      0.01%     69.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     69.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.48% # Class of executed instruction
-system.cpu.op_class::MemRead                158209551     16.00%     85.48% # Class of executed instruction
-system.cpu.op_class::MemWrite               143623358     14.52%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 731218910     69.27%     69.27% # Class of executed instruction
+system.cpu.op_class::IntMult                  2226806      0.21%     69.48% # Class of executed instruction
+system.cpu.op_class::IntDiv                     99223      0.01%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             110423      0.01%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::MemRead                168639088     15.97%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               153362234     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  988874964                       # Class of executed instruction
+system.cpu.op_class::total                 1055656727                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16062                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements          13492469                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.894753                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           828035859                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          13492981                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             61.367896                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31319075250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.894753                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999794                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999794                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16365                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements          10282368                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.969706                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           311548704                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10282880                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.297806                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3093156250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.969706                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999941                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          410                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1298012717                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1298012717                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    157556193                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       157556193                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    145511723                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      145511723                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       396994                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        396994                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       336687                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       336687                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3698345                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3698345                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4003149                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4003149                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     303067916                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        303067916                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    303464910                       # number of overall hits
+system.cpu.dcache.overall_hits::total       303464910                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      5344087                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       5344087                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2236666                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2236666                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1310162                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1310162                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1231947                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1231947                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       306495                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       306495                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      7580753                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7580753                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      8890915                       # number of overall misses
+system.cpu.dcache.overall_misses::total       8890915                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  83712196260                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  83712196260                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  64378240535                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  64378240535                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  27514486506                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  27514486506                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4474608500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4474608500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       251501                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       251501                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 148090436795                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 148090436795                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 148090436795                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 148090436795                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    162900280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    162900280                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    147748389                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    147748389                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1707156                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1707156                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1568634                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1568634                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4004840                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4004840                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4003153                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4003153                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    310648669                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    310648669                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    312355825                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    312355825                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032806                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032806                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015138                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015138                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.767453                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.767453                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.785363                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.785363                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076531                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076531                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024403                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024403                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028464                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028464                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19535.056319                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16656.377526                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      7918344                       # number of writebacks
+system.cpu.dcache.writebacks::total           7918344                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7198                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         7198                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21104                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21104                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70788                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70788                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        28302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        28302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        28302                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        28302                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5336889                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5336889                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2215562                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2215562                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1308413                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1308413                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1231947                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1231947                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       235707                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       235707                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7552451                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7552451                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8860864                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8860864                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  72465482990                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  72465482990                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  59129774715                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  59129774715                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  19473134500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  19473134500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  25050592494                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  25050592494                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2902318500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2902318500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       243499                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       243499                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 131595257705                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151068392205                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 151068392205                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5727938750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5727938750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5573388000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5573388000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11301326750                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11301326750                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032762                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032762                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014996                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014996                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.766428                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.766428                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.785363                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.785363                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058856                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058856                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024312                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024312                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028368                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028368                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13578.225627                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13578.225627                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26688.386385                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 60874.750000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17424.178946                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17424.178946                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17048.946040                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17048.946040                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          13856298                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.892935                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           884585744                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          13856810                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             63.837618                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31832974250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.892935                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999791                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999791                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         855021831                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        855021831                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    828035859                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       828035859                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     828035859                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        828035859                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    828035859                       # number of overall hits
-system.cpu.icache.overall_hits::total       828035859                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     13492986                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      13492986                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     13492986                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       13492986                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     13492986                       # number of overall misses
-system.cpu.icache.overall_misses::total      13492986                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 179568208714                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 179568208714                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 179568208714                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 179568208714                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 179568208714                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 179568208714                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    841528845                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016034                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13308.263176                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13308.263176                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13308.263176                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13308.263176                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13308.263176                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13308.263176                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         912299374                       # Number of tag accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13370.106441                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13370.106441                       # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13370.106441                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13370.106441                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -723,199 +746,208 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13492986                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total     13492986                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 152559106286                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 152559106286                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 152559106286                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 152559106286                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 152559106286                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 152559106286                       # number of overall MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2831639000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2831639000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2831639000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   2831639000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016034                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016034                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total     0.016034                       # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total     0.016034                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11306.548920                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11306.548920                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11306.548920                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11306.548920                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11306.548920                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11306.548920                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11368.073545                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11368.073545                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           628827                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64292.510551                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           25964475                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           690318                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            37.612340                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     13963583388500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36090.515742                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   282.968665                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   462.557574                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8120.436200                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19336.032370                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.550698                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007058                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::total     0.981026                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          448                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61043                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          436                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1832                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53784                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.006836                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.931442                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        245315088                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.021407                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.050650                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.004808                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043949                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.017693                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.773406                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.773406                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.replacements          1326931                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65218.833700                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           27835482                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1389841                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            20.027818                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6373825000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 38602.265871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   305.289253                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   445.157205                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.data 19488.149376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.589024                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62664                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2454                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54290                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003754                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.956177                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        266276553                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       383012                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       255352                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::writebacks      7918344                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      7918344                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1231947                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.011216                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.041978                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.413551                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.413551                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783332                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783332                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283741                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.283741                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.021407                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.050650                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004808                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.100891                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.041011                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.021407                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.050650                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004808                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.100891                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.041011                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76629.678363                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78198.048267                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73748.223358                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74156.951374                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74268.996188                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.501247                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.501247                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        23499                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        23499                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71126.901555                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71126.901555                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76629.678363                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78198.048267                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73748.223358                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72133.371770                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72363.656925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76629.678363                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78198.048267                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73748.223358                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72133.371770                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72363.656925                       # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78310.870577                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78777.568922                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74653.440510                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76292.721671                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76001.212021                       # average ReadReq miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     0.230621                       # average WriteInvalidateReq miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     0.230621                       # average WriteInvalidateReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.152322                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.152322                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 59874.750000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 59874.750000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74102.291918                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74102.291918                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78310.870577                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78777.568922                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74653.440510                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74870.215638                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74886.487315                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78310.870577                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78777.568922                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74653.440510                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74870.215638                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74886.487315                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -924,104 +956,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       479499                       # number of writebacks
-system.cpu.l2cache.writebacks::total           479499                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6840                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker        12348                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        64878                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       275571                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       359637                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total        32886                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  22213192518                       # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  31086027509                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    329042883                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    329042883                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total  54713316577                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1135338                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2248902500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5288238001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7537140501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5166002500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5166002500                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2248902500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10454240501                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12703143001                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.021407                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.050650                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.004808                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.043949                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017693                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.773406                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.773406                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10454004000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12702906500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011216                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017188                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005692                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.041978                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017609                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.413551                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.413551                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783332                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783332                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283741                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283741                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.021407                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.050650                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004808                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.100891                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.041011                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.021407                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.050650                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004808                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.100891                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.041011                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65835.195983                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61238.551820                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61644.685954                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61765.592856                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.561120                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.561120                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58658.660348                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58658.660348                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65835.195983                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61238.551820                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59650.507352                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59881.575604                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65835.195983                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61238.551820                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59650.507352                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59881.575604                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.246582                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.246582                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017188                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005692                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091032                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.038711                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005692                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091032                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.038711                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1031,312 +1067,203 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9444412                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.969639                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           292228081                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9444924                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             30.940226                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3093156250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.969639                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999941                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          381                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1216524124                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1216524124                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    148096939                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       148096939                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    136359357                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      136359357                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       375583                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        375583                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data      1554140                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total      1554140                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3367107                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3367107                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3654437                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3654437                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     284456296                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        284456296                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    284831879                       # number of overall hits
-system.cpu.dcache.overall_hits::total       284831879                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4902764                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4902764                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2016394                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2016394                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1154103                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1154103                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       288962                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       288962                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      6919158                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        6919158                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      8073261                       # number of overall misses
-system.cpu.dcache.overall_misses::total       8073261                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  76779469503                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  76779469503                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  60928492192                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  60928492192                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4073605250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4073605250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        53002                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        53002                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 137707961695                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 137707961695                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 137707961695                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 137707961695                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    152999703                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    152999703                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    138375751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    138375751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1529686                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1529686                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1554140                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1554140                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3656069                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3656069                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3654439                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3654439                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    291375454                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    291375454                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    292905140                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    292905140                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032044                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032044                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014572                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.014572                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.754471                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.754471                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079036                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079036                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023747                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023747                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027563                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027563                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15660.445721                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15660.445721                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30216.560946                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30216.560946                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14097.373530                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14097.373530                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        26501                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19902.416117                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19902.416117                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17057.290938                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17057.290938                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                 1554140                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      6407423                       # number of writebacks
-system.cpu.dcache.writebacks::total           6407423                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         5098                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         5098                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21192                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21192                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69202                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69202                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        26290                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        26290                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        26290                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        26290                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4897666                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      4897666                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1995202                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1995202                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1152860                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1152860                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       219760                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       219760                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      6892868                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      6892868                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8045728                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8045728                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  66593476247                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  66593476247                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  56238194808                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  56238194808                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  17420344250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  17420344250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  50499536991                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  50499536991                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2639848250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2639848250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        48998                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        48998                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 122831671055                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 122831671055                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 140252015305                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 140252015305                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5728170249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5728170249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5573361000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5573361000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11301531249                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11301531249                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014419                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014419                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753658                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753658                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060108                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060108                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023656                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023656                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027469                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027469                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13596.981960                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13596.981960                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.717339                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.717339                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15110.546163                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15110.546163                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12012.414680                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12012.414680                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        24499                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17820.110737                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17820.110737                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17431.861393                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17431.861393                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       20761818                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      20753624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      6407423                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1660819                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1554140                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        42524                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        42526                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1952681                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1952681                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     27072222                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     26182676                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       601299                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       874780                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          54730977                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    863723604                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1036044256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1950336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2556184                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1904274380                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      465684                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     30748357                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.003758                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.061188                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq       21819690                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      21811671                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      7918344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1338611                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1231947                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        45612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        45616                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2169953                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2169953                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     27799880                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28711563                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       624328                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1010117                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          58145888                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    887008660                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1165125804                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2042816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3064096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2057241376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      474114                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     33215302                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.003479                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.058876                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           30632803     99.62%     99.62% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115554      0.38%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           33099762     99.65%     99.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115540      0.35%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       30748357                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    23350352499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       33215302                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    25772593750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1018500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1282500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20304235714                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20852498735                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13344056707                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14430330552                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     358207000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     369475750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     555725500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     627605250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115481                       # number of replacements
-system.iocache.tags.tagsinuse               10.454792                       # Cycle average of tags in use
+system.iobus.trans_dist::ReadReq                40402                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40402                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231000                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231000                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334432                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334432                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492838                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy          1042392405                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer3.occupancy           179042528                       # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
+system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
+system.iocache.tags.replacements               115480                       # number of replacements
+system.iocache.tags.tagsinuse               10.457351                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115497                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115496                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153677258000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.509713                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.945079                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219357                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434067                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653424                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13153949219000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.511147                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.946204                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219447                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434138                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653584                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039872                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039872                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039857                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039857                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8835                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8872                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8836                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8873                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide            3                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total            3                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8835                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8875                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8836                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8876                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8835                       # number of overall misses
-system.iocache.overall_misses::total             8875                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8836                       # number of overall misses
+system.iocache.overall_misses::total             8876                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1898661362                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1904146362                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1916450860                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1921935860                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28823836017                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28823836017                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1898661362                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1904485362                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1916450860                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1922274860                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1898661362                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1904485362                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1916450860                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1922274860                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8835                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8872                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8836                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8873                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106667                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106667                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8835                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8875                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8836                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8876                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8835                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8875                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8836                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8876                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000028                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000028                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -1344,53 +1271,61 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 214902.248104                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 214624.251803                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 216604.965626                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 214902.248104                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 214589.899944                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 216891.224536                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 216569.948175                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 214902.248104                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 214589.899944                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         51753                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 216891.224536                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 216569.948175                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        223291                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27458                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.426776                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.132093                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106629                       # number of writebacks
+system.iocache.writebacks::total               106629                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8835                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8872                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8836                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8873                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8835                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8875                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8836                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8876                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8835                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8875                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8836                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8876                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1439157862                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1442718862                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1456881862                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1460442862                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6525754202                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6525754202                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23277254071                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23277254071                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1439157862                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1442901862                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1456881862                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1460625862                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1439157862                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1442901862                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1456881862                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1460625862                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
@@ -1398,18 +1333,112 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 162892.797057                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 162614.840171                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 162892.797057                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162580.491493                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 164559.020054                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 162892.797057                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162580.491493                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 164559.020054                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              462201                       # Transaction distribution
+system.membus.trans_dist::ReadResp             462201                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33872                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33872                       # Transaction distribution
+system.membus.trans_dist::Writeback           1241967                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       616132                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       616132                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36293                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36297                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            534513                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           534513                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4139437                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4269627                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4604753                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    163718240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    163888576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14053504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14053504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               177942080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3244                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2814199                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2814199    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             2814199                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106092500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             5680000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy         17856822743                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer2.occupancy         9254301682                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer3.occupancy          186599472                       # Layer occupancy (ticks)
+system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index a57c553a7..72bc2e01a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -1,18 +1,74 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.111167                       # Number of seconds simulated
-sim_ticks                                51111167186000                       # Number of ticks simulated
-final_tick                               51111167186000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.111151                       # Number of seconds simulated
+sim_ticks                                51111150553500                       # Number of ticks simulated
+final_tick                               51111150553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1245007                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1463153                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            64786832406                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 666372                       # Number of bytes of host memory used
-host_seconds                                   788.91                       # Real time elapsed on the host
-sim_insts                                   982202425                       # Number of instructions simulated
-sim_ops                                    1154300154                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1088550                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1279225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            56496360239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 672572                       # Number of bytes of host memory used
+host_seconds                                   904.68                       # Real time elapsed on the host
+sim_insts                                   984789519                       # Number of instructions simulated
+sim_ops                                    1157289961                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker       200576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       185152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3380276                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         37995016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       209984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       187968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2175808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         37325312                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        437696                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             82097788                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3380276                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2175808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5556084                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103277696                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103298276                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         3134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2893                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             93224                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            593685                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3281                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2937                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             33997                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            583208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6839                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1323198                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1613714                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1616287                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3924                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               66136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              743380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4108                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3678                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               42570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              730277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8564                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1606260                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          66136                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          42570                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108706                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2020649                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2021052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2020649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3924                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              66136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             743783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4108                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3678                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              42570                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             730277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8564                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3627311                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -29,435 +85,13 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide        441600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       336512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       497152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3037748                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         46051464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       337024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       478912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2057984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         44726784                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             97965180                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3037748                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2057984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5095732                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65987776                       # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      57990628                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      43345472                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         174150372                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide           6900                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker         5258                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         7768                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             87872                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            719567                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         5266                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         7483                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             32156                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            698856                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1571126                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1031059                       # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           908355                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           677273                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              2723351                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide             8640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          6584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          9727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               59434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              901006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          6594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          9370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               40265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              875088                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1916708                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          59434                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          40265                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              99699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1291064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide          133562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            1134598                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             848063                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3407286                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1291064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide          142202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         6584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         9727                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              59434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2035604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         6594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         9370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              40265                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1723151                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5323994                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              581619                       # Transaction distribution
-system.membus.trans_dist::ReadResp             581619                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33712                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33712                       # Transaction distribution
-system.membus.trans_dist::Writeback           1031059                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq      1689719                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp      1689719                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40044                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40045                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1025076                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1025076                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122798                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      7410857                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      7540367                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       231034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       231034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                7771401                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    264847648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    265017016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7392896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7392896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               272409912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4290786                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4290786    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4290786                       # Request fanout histogram
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                  1249718                       # number of replacements
-system.l2c.tags.tagsinuse                64613.042702                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   29438941                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1311508                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    22.446635                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             13800320247500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36057.882399                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.314219                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   260.482704                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3661.102067                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9854.563004                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   162.816685                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   224.976066                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2766.895079                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11463.010480                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.550200                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002461                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003975                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.055864                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.150369                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002484                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003433                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042219                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.174912                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.985917                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          446                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61344                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          435                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2192                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4810                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53981                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.006805                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.936035                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                284052655                       # Number of tag accesses
-system.l2c.tags.data_accesses               284052655                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       278747                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       141162                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            7094152                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3728500                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       275483                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       137718                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            7094701                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3721109                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               22471572                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7859784                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7859784                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            6010                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5720                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               11730                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           752229                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           739129                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1491358                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        278747                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        141162                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7094152                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4480729                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        275483                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        137718                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7094701                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4460238                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                23962930                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       278747                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       141162                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7094152                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4480729                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       275483                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       137718                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            7094701                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4460238                       # number of overall hits
-system.l2c.overall_hits::total               23962930                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         5258                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         7768                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            44771                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           202781                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         5266                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         7483                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            32156                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           190554                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               496037                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         20061                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         19420                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             39481                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         517033                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         508603                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total            1025636                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         5258                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         7768                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             44771                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            719814                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         5266                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         7483                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             32156                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            699157                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1521673                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         5258                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         7768                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            44771                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           719814                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         5266                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         7483                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            32156                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           699157                       # number of overall misses
-system.l2c.overall_misses::total              1521673                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       284005                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       148930                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst        7138923                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        3931281                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       280749                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       145201                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst        7126857                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data        3911663                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total           22967609                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      7859784                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          7859784                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        26071                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        25140                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           51211                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1269262                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1247732                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2516994                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       284005                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       148930                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         7138923                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         5200543                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       280749                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       145201                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         7126857                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         5159395                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25484603                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       284005                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       148930                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        7138923                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        5200543                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       280749                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       145201                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        7126857                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        5159395                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25484603                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.018514                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.052159                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.006271                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.051581                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.018757                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.051535                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004512                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.048714                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.021597                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.769476                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.772474                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.770948                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.407349                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.407622                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.407484                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.018514                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.052159                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006271                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.138411                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.018757                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.051535                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004512                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.135511                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.059710                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.018514                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.052159                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006271                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.138411                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.018757                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.051535                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004512                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.135511                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.059710                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1031059                       # number of writebacks
-system.l2c.writebacks::total                  1031059                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq           23429115                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23429115                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33712                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33712                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7859784                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1583055                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1583055                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           51211                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          51212                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2516994                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2516994                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     28617810                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31982832                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       830190                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1657128                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              63087960                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    913182420                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1267567716                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3320760                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6628512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2190699408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          116124                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         35478945                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003256                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.056968                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               35363428     99.67%     99.67% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115517      0.33%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           35478945                       # Request fanout histogram
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29957                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47916                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122798                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353832                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47936                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155928                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492262                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -481,25 +115,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    91814340                       # DTB read hits
-system.cpu0.dtb.read_misses                    108240                       # DTB read misses
-system.cpu0.dtb.write_hits                   84018556                       # DTB write hits
-system.cpu0.dtb.write_misses                    37258                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51122                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    91965302                       # DTB read hits
+system.cpu0.dtb.read_misses                    107321                       # DTB read misses
+system.cpu0.dtb.write_hits                   84365950                       # DTB write hits
+system.cpu0.dtb.write_misses                    37661                       # DTB write misses
+system.cpu0.dtb.flush_tlb                       51121                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              25424                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   56720                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              25055                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    566                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   56687                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4774                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4951                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10954                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                91922580                       # DTB read accesses
-system.cpu0.dtb.write_accesses               84055814                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    11060                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                92072623                       # DTB read accesses
+system.cpu0.dtb.write_accesses               84403611                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        175832896                       # DTB hits
-system.cpu0.dtb.misses                         145498                       # DTB misses
-system.cpu0.dtb.accesses                    175978394                       # DTB accesses
+system.cpu0.dtb.hits                        176331252                       # DTB hits
+system.cpu0.dtb.misses                         144982                       # DTB misses
+system.cpu0.dtb.accesses                    176476234                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -521,269 +155,275 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   492376635                       # ITB inst hits
-system.cpu0.itb.inst_misses                     70812                       # ITB inst misses
+system.cpu0.itb.inst_hits                   493804573                       # ITB inst hits
+system.cpu0.itb.inst_misses                     70785                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51122                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                       51121                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              25424                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40507                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              25055                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    566                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   40296                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               492447447                       # ITB inst accesses
-system.cpu0.itb.hits                        492376635                       # DTB hits
-system.cpu0.itb.misses                          70812                       # DTB misses
-system.cpu0.itb.accesses                    492447447                       # DTB accesses
-system.cpu0.numCycles                     98037034508                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               493875358                       # ITB inst accesses
+system.cpu0.itb.hits                        493804573                       # DTB hits
+system.cpu0.itb.misses                          70785                       # DTB misses
+system.cpu0.itb.accesses                    493875358                       # DTB accesses
+system.cpu0.numCycles                     98036815347                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  492157902                       # Number of instructions committed
-system.cpu0.committedOps                    578109926                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            529630902                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                450855                       # Number of float alu accesses
-system.cpu0.num_func_calls                   28493711                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     76041471                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   529630902                       # number of integer instructions
-system.cpu0.num_fp_insts                       450855                       # number of float instructions
-system.cpu0.num_int_register_reads          782881083                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         420743584                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              732582                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             369632                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           132702849                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          132381135                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    175956600                       # number of memory refs
-system.cpu0.num_load_insts                   91908955                       # Number of load instructions
-system.cpu0.num_store_insts                  84047645                       # Number of store instructions
-system.cpu0.num_idle_cycles              96929537952.996140                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1107496555.003859                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011297                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988703                       # Percentage of idle cycles
-system.cpu0.Branches                        110099418                       # Number of branches fetched
+system.cpu0.committedInsts                  493589418                       # Number of instructions committed
+system.cpu0.committedOps                    579610206                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            531010156                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                454321                       # Number of float alu accesses
+system.cpu0.num_func_calls                   28538505                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     76169999                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   531010156                       # number of integer instructions
+system.cpu0.num_fp_insts                       454321                       # number of float instructions
+system.cpu0.num_int_register_reads          784912346                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         421695474                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              742936                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             362460                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           132983142                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          132661017                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    176454648                       # number of memory refs
+system.cpu0.num_load_insts                   92059270                       # Number of load instructions
+system.cpu0.num_store_insts                  84395378                       # Number of store instructions
+system.cpu0.num_idle_cycles              96925999292.039536                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1110816054.960464                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.011331                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.988669                       # Percentage of idle cycles
+system.cpu0.Branches                        110347037                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                401202102     69.36%     69.36% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1174212      0.20%     69.56% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49936      0.01%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             53534      0.01%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::MemRead                91908955     15.89%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               84047645     14.53%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                402205176     69.35%     69.35% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1169973      0.20%     69.56% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    50634      0.01%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             52759      0.01%     69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.57% # Class of executed instruction
+system.cpu0.op_class::MemRead                92059270     15.87%     85.45% # Class of executed instruction
+system.cpu0.op_class::MemWrite               84395378     14.55%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 578436384                       # Class of executed instruction
+system.cpu0.op_class::total                 579933190                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   16775                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements         14265263                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          968528346                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         14265775                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.891744                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6061930000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   268.596875                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   243.387725                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.524603                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.475367                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        997059906                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       997059906                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    485302312                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    483226034                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      968528346                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    485302312                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    483226034                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       968528346                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    485302312                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    483226034                       # number of overall hits
-system.cpu0.icache.overall_hits::total      968528346                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      7138923                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      7126857                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     14265780                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      7138923                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      7126857                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      14265780                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      7138923                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      7126857                       # number of overall misses
-system.cpu0.icache.overall_misses::total     14265780                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    492441235                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    490352891                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    982794126                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    492441235                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    490352891                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    982794126                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    492441235                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    490352891                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    982794126                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014497                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014534                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014497                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014534                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014516                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014497                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014534                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014516                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements         11606183                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          339855525                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         11606695                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            29.280990                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements         11615783                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999718                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          340859093                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         11616295                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            29.343185                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   263.642084                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   248.357636                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.514926                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.485074                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   265.932740                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   246.066978                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.519400                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.480600                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1417455640                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1417455640                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     85601256                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     85509652                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      171110908                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     79544795                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     79528789                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     159073584                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209342                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       214988                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       424330                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       905782                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       677273                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total      1583055                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2149143                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      2154415                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      4303558                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2275069                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2280579                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4555648                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165146051                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    165038441                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       330184492                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    165355393                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    165253429                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      330608822                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3016346                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2986822                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6003168                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1295333                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1272872                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2568205                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       788110                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       797772                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1585882                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       126825                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       127069                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       253894                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1421517922                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1421517922                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     85766676                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     85839710                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      171606386                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     79896763                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     79669373                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     159566136                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       208546                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       215430                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       423976                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       146337                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       191461                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       337798                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2132895                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      2177393                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      4310288                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2256573                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2306673                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4563246                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    165663439                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    165509083                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       331172522                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    165871985                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    165724513                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      331596498                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3019403                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      2994182                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6013585                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1302154                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1267314                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2569468                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       789306                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       795194                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1584500                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       766302                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       478957                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total      1245259                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       124586                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       130174                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       254760                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4311679                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4259694                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       8571373                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5099789                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5057466                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     10157255                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     88617602                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     88496474                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    177114076                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     80840128                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     80801661                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    161641789                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       997452                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data      1012760                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      2010212                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       905782                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       677273                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1583055                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2275968                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2281484                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4557452                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2275069                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2280580                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4555649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    169457730                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    169298135                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    338755865                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    170455182                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    170310895                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    340766077                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034038                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033751                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033894                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016023                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015753                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015888                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.790123                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.787721                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788913                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055724                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055696                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055710                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_misses::cpu0.data      4321557                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      4261496                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       8583053                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5110863                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      5056690                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     10167553                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     88786079                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     88833892                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    177619971                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     81198917                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     80936687                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    162135604                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       997852                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data      1010624                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      2008476                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       912639                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       670418                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1583057                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2257481                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2307567                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4565048                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2256573                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2306674                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4563247                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    169984996                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    169770579                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    339755575                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    170982848                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    170781203                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    341764051                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034008                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033705                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033856                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016037                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015658                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.015848                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.791005                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.786835                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788907                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.839655                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.714415                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786617                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055188                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056412                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055807                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025444                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025161                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.025303                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029919                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029695                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029807                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025423                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025101                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025262                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029891                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029609                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029750                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                1583055                       # number of fast writes performed
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7859784                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7859784                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      8923646                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8923646                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements         14287218                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          971093500                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         14287730                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.966955                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6061930000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   267.813987                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   244.170612                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.523074                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.476896                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses        999668970                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       999668970                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    486710504                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    484382996                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      971093500                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    486710504                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    484382996                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       971093500                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    486710504                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    484382996                       # number of overall hits
+system.cpu0.icache.overall_hits::total      971093500                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      7158773                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      7128962                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     14287735                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      7158773                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      7128962                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      14287735                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      7158773                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      7128962                       # number of overall misses
+system.cpu0.icache.overall_misses::total     14287735                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    493869277                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    491511958                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    985381235                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    493869277                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    491511958                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    985381235                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    493869277                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    491511958                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    985381235                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014495                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014504                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014500                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014495                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014504                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014500                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014495                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014504                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014500                       # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -807,25 +447,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    91711295                       # DTB read hits
-system.cpu1.dtb.read_misses                    106129                       # DTB read misses
-system.cpu1.dtb.write_hits                   83753398                       # DTB write hits
-system.cpu1.dtb.write_misses                    37024                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51111                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    92072581                       # DTB read hits
+system.cpu1.dtb.read_misses                    106555                       # DTB read misses
+system.cpu1.dtb.write_hits                   83907281                       # DTB write hits
+system.cpu1.dtb.write_misses                    36757                       # DTB write misses
+system.cpu1.dtb.flush_tlb                       51112                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              24347                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   56316                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              24716                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    573                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   56101                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4760                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4637                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10697                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                91817424                       # DTB read accesses
-system.cpu1.dtb.write_accesses               83790422                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10591                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                92179136                       # DTB read accesses
+system.cpu1.dtb.write_accesses               83944038                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        175464693                       # DTB hits
-system.cpu1.dtb.misses                         143153                       # DTB misses
-system.cpu1.dtb.accesses                    175607846                       # DTB accesses
+system.cpu1.dtb.hits                        175979862                       # DTB hits
+system.cpu1.dtb.misses                         143312                       # DTB misses
+system.cpu1.dtb.accesses                    176123174                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -847,136 +487,185 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   490289476                       # ITB inst hits
-system.cpu1.itb.inst_misses                     69341                       # ITB inst misses
+system.cpu1.itb.inst_hits                   491448225                       # ITB inst hits
+system.cpu1.itb.inst_misses                     69790                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51111                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                       51112                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              24347                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40524                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              24716                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    573                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   40454                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               490358817                       # ITB inst accesses
-system.cpu1.itb.hits                        490289476                       # DTB hits
-system.cpu1.itb.misses                          69341                       # DTB misses
-system.cpu1.itb.accesses                    490358817                       # DTB accesses
-system.cpu1.numCycles                     97462079825                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               491518015                       # ITB inst accesses
+system.cpu1.itb.hits                        491448225                       # DTB hits
+system.cpu1.itb.misses                          69790                       # DTB misses
+system.cpu1.itb.accesses                    491518015                       # DTB accesses
+system.cpu1.numCycles                     97463256917                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  490044523                       # Number of instructions committed
-system.cpu1.committedOps                    576190228                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            528250346                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                430494                       # Number of float alu accesses
-system.cpu1.num_func_calls                   28340448                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     75582064                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   528250346                       # number of integer instructions
-system.cpu1.num_fp_insts                       430494                       # number of float instructions
-system.cpu1.num_int_register_reads          777877517                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         419772646                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              687185                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             378928                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           131315601                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          131059540                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    175582943                       # number of memory refs
-system.cpu1.num_load_insts                   91803462                       # Number of load instructions
-system.cpu1.num_store_insts                  83779481                       # Number of store instructions
-system.cpu1.num_idle_cycles              96357524268.359177                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1104555556.640824                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011333                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988667                       # Percentage of idle cycles
-system.cpu1.Branches                        109434059                       # Number of branches fetched
+system.cpu1.committedInsts                  491200101                       # Number of instructions committed
+system.cpu1.committedOps                    577679755                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            529688376                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                426452                       # Number of float alu accesses
+system.cpu1.num_func_calls                   28536988                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     75796446                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   529688376                       # number of integer instructions
+system.cpu1.num_fp_insts                       426452                       # number of float instructions
+system.cpu1.num_int_register_reads          779402047                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         420937852                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              676063                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             385332                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           131460069                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          131204494                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    176098133                       # number of memory refs
+system.cpu1.num_load_insts                   92164972                       # Number of load instructions
+system.cpu1.num_store_insts                  83933161                       # Number of store instructions
+system.cpu1.num_idle_cycles              96357264034.410416                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1105992882.589586                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.011348                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.988652                       # Percentage of idle cycles
+system.cpu1.Branches                        109788123                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                399630543     69.32%     69.32% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1180172      0.20%     69.53% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    50607      0.01%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             54288      0.01%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::MemRead                91803462     15.92%     85.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite               83779481     14.53%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                400601727     69.31%     69.31% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1185429      0.21%     69.51% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    51217      0.01%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             55063      0.01%     69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.53% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.53% # Class of executed instruction
+system.cpu1.op_class::MemRead                92164972     15.95%     85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite               83933161     14.52%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 576498596                       # Class of executed instruction
+system.cpu1.op_class::total                 577991612                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iocache.tags.replacements               115459                       # number of replacements
-system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
+system.iobus.trans_dist::ReadReq                40296                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40296                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              29957                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122798                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47936                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155928                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492270                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements               115460                       # number of replacements
+system.iocache.tags.tagsinuse               10.407109                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115476                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13082113302009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet     3.554601                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.852508                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.222163                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.428282                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.650444                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039650                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
+system.iocache.tags.tag_accesses              1039659                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039659                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8814                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8851                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
+system.iocache.overall_misses::total             8854                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -989,8 +678,333 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                     106664                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.l2c.tags.replacements                  1726938                       # number of replacements
+system.l2c.tags.tagsinuse                65261.456077                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   30061688                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1789677                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    16.797270                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   37843.446470                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   133.851039                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   182.256334                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3658.181664                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9398.442867                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   138.187628                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   187.456005                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2615.769048                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11103.865022                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.577445                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::4        54021                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003754                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.953568                       # Percentage of cache occupancy per task id
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+system.l2c.UpgradeReq_misses::cpu0.data         19998                       # number of UpgradeReq misses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.010949                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.019253                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.007002                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.045280                       # miss rate for ReadReq accesses
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+system.l2c.WriteInvalidateReq_miss_rate::total     0.440024                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.779254                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782531                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.780890                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::cpu0.data     0.325924                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.336281                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.331031                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.010949                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.019253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.007002                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.114043                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.011654                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.019925                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004771                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.113139                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.049931                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.010949                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.019253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.007002                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.114043                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.011654                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.019925                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004771                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.113139                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.049931                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks             1507083                       # number of writebacks
+system.l2c.writebacks::total                  1507083                       # number of writebacks
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              526435                       # Transaction distribution
+system.membus.trans_dist::ReadResp             526435                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33712                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33712                       # Transaction distribution
+system.membus.trans_dist::Writeback           1613714                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       654603                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       654603                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40598                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40599                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            833044                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           833044                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122798                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5323323                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5452833                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337667                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       337667                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5790500                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    213243872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    213413240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14217344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               227630584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3591663                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3591663    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::total             3591663                       # Request fanout histogram
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
+system.realview.ethernet.totBytes                 966                       # Total Bytes
+system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq           23461417                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23461417                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33712                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33712                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          8923646                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1245259                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1245259                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           51262                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          51263                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2518206                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2518206                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     28661720                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32393430                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       832700                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1655510                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              63543360                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    914587540                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1314747172                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3330800                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6622040                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2239287552                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          116335                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         36238577                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003188                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.056370                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               36123059     99.68%     99.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115518      0.32%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           36238577                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 2aea37e39..42cd6a730 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,87 +1,84 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.112155                       # Number of seconds simulated
-sim_ticks                                5112155173500                       # Number of ticks simulated
-final_tick                               5112155173500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.112156                       # Number of seconds simulated
+sim_ticks                                5112155738500                       # Number of ticks simulated
+final_tick                               5112155738500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1977176                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4047982                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            50529549296                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 594968                       # Number of bytes of host memory used
-host_seconds                                   101.17                       # Real time elapsed on the host
-sim_insts                                   200033988                       # Number of instructions simulated
-sim_ops                                     409540726                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1511003                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3093560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38615908446                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 595640                       # Number of bytes of host memory used
+host_seconds                                   132.38                       # Real time elapsed on the host
+sim_insts                                   200033669                       # Number of instructions simulated
+sim_ops                                     409539941                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            852288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10678208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            852224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10636736                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11559232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       852288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          852288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6294336                       # Number of bytes written to this memory
-system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9284416                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11517696                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       852224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          852224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9281152                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9281152                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              13317                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             166847                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              13316                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             166199                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180613                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           98349                       # Number of write requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               145069                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                179964                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          145018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               145018                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               166718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2088788                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               166705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2080675                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2261127                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          166718                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             166718                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1231249                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       584896                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1816145                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1231249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 2253002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          166705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             166705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1815507                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1815507                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1815507                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              166718                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2088788                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       590442                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4077272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              166705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2080675                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4068508                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10224314318                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224315447                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   200033988                       # Number of instructions committed
-system.cpu.committedOps                     409540726                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374550150                       # Number of integer alu accesses
+system.cpu.committedInsts                   200033669                       # Number of instructions committed
+system.cpu.committedOps                     409539941                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374549395                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2308777                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39994865                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374550150                       # number of integer instructions
+system.cpu.num_func_calls                     2308749                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     39994798                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374549395                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           682630172                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          323525861                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           682628451                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          323525110                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            233820803                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           157313619                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      35680563                       # number of memory refs
-system.cpu.num_load_insts                    27249389                       # Number of load instructions
-system.cpu.num_store_insts                    8431174                       # Number of store instructions
-system.cpu.num_idle_cycles               9770366809.410368                       # Number of idle cycles
-system.cpu.num_busy_cycles               453947508.589632                       # Number of busy cycles
+system.cpu.num_cc_register_reads            233820400                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           157313425                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      35680406                       # number of memory refs
+system.cpu.num_load_insts                    27249300                       # Number of load instructions
+system.cpu.num_store_insts                    8431106                       # Number of store instructions
+system.cpu.num_idle_cycles               9770368815.449127                       # Number of idle cycles
+system.cpu.num_busy_cycles               453946631.550873                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.044399                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955601                       # Percentage of idle cycles
-system.cpu.Branches                          43145769                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                175400      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                 373418196     91.18%     91.22% # Class of executed instruction
-system.cpu.op_class::IntMult                   144548      0.04%     91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv                    123054      0.03%     91.29% # Class of executed instruction
+system.cpu.Branches                          43145649                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                175370      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                 373417675     91.18%     91.22% # Class of executed instruction
+system.cpu.op_class::IntMult                   144551      0.04%     91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                    122974      0.03%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     91.29% # Class of executed instruction
@@ -108,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 27249389      6.65%     97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8431174      2.06%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 27249300      6.65%     97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8431106      2.06%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  409541761                       # Class of executed instruction
+system.cpu.op_class::total                  409540976                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements           1623441                       # number of replacements
+system.cpu.dcache.tags.replacements           1623460                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999462                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20193263                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1623953                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.434635                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            20193083                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1623972                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.434379                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle           7549500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999462                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -129,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          233
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88892882                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88892882                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12028464                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12028464                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8103633                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8103633                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        58902                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         58902                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20132097                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20132097                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20190999                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20190999                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       905998                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        905998                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       317173                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       317173                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       403059                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       403059                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1223171                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1223171                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1626230                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1626230                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     12934462                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12934462                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8420806                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8420806                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          88892257                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88892257                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12028370                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12028370                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8103548                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8103548                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        58901                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         58901                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      20131918                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20131918                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20190819                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20190819                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       906001                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        906001                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       317188                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       317188                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       403060                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       403060                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1223189                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1223189                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1626249                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1626249                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     12934371                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12934371                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8420736                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8420736                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       461961                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total       461961                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21355268                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21355268                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21817229                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21817229                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070045                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070045                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037665                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037665                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872496                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.872496                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.057277                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.057277                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074539                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074539                       # miss rate for overall accesses
+system.cpu.dcache.demand_accesses::cpu.data     21355107                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21355107                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21817068                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21817068                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070046                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070046                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037667                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037667                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872498                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.872498                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057279                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057279                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074540                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074540                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -179,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1536849                       # number of writebacks
-system.cpu.dcache.writebacks::total           1536849                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1536867                       # number of writebacks
+system.cpu.dcache.writebacks::total           1536867                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         8174                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.013947                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12516                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.013943                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        12520                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.sampled_refs         8188                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.528578                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013947                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313372                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313372                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.avg_refs     1.529067                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013943                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313371                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313371                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        53153                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        53153                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12517                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12517                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12517                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12517                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12517                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12517                       # number of overall hits
+system.cpu.dtb_walker_cache.tags.tag_accesses        53161                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53161                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12521                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12521                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12521                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12521                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12521                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12521                       # number of overall hits
 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9373                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total         9373                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9373                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total         9373                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9373                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total         9373                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21890                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21890                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21890                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21890                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21890                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21890                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.428186                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.428186                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.428186                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21894                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21894                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21894                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21894                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.428108                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.428108                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.428108                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.428108                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.428108                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.428108                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -233,11 +230,11 @@ system.cpu.dtb_walker_cache.cache_copies            0                       # nu
 system.cpu.dtb_walker_cache.writebacks::writebacks         2794                       # number of writebacks
 system.cpu.dtb_walker_cache.writebacks::total         2794                       # number of writebacks
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            791952                       # number of replacements
+system.cpu.icache.tags.replacements            791846                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.663108                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           243645979                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            792464                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            307.453687                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           243645674                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            792358                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            307.494433                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      148876575500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.663108                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997389                       # Average percentage of cache occupancy
@@ -248,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          134
 system.cpu.icache.tags.age_task_id_blocks_1024::2          289                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         245230921                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        245230921                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    243645979                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243645979                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243645979                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243645979                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243645979                       # number of overall hits
-system.cpu.icache.overall_hits::total       243645979                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       792471                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        792471                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       792471                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         792471                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       792471                       # number of overall misses
-system.cpu.icache.overall_misses::total        792471                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244438450                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244438450                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244438450                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244438450                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244438450                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244438450                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         245230404                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        245230404                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    243645674                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243645674                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243645674                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243645674                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243645674                       # number of overall hits
+system.cpu.icache.overall_hits::total       243645674                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       792365                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        792365                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       792365                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         792365                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       792365                       # number of overall misses
+system.cpu.icache.overall_misses::total        792365                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244438039                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244438039                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244438039                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244438039                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244438039                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244438039                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003242                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.003242                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003242                       # miss rate for demand accesses
@@ -284,12 +281,12 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3702                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.026453                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.026443                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7640                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.tags.sampled_refs         3715                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.tags.avg_refs     2.056528                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026453                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026443                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189153                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.189153                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
@@ -339,17 +336,17 @@ system.cpu.itb_walker_cache.cache_copies            0                       # nu
 system.cpu.itb_walker_cache.writebacks::writebacks          802                       # number of writebacks
 system.cpu.itb_walker_cache.writebacks::total          802                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           106197                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64825.457913                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3461872                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           170308                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            20.327125                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           106199                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64825.456332                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3461789                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           170310                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            20.326399                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132278                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.291417                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132276                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.288805                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.792099                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -360,32 +357,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024        64111
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3498                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20716                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39582                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20721                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39577                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978256                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32246059                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32246059                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         32245523                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32245523                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7331                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3337                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       779141                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1276184                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2065993                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1540445                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1540445                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       779035                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1276188                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2065891                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1540463                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1540463                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           22                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           22                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       180006                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       180006                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       180020                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       180020                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         7331                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3337                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       779141                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1456190                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2245999                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       779035                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1456208                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2245911                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         7331                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3337                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       779141                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1456190                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2245999                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       779035                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1456208                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2245911                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.inst        13317                       # number of ReadReq misses
@@ -393,58 +390,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data        32232                       #
 system.cpu.l2cache.ReadReq_misses::total        45555                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         1813                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         1813                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134898                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       134898                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       134899                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       134899                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.inst        13317                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       167130                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        180453                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       167131                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        180454                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.inst        13317                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       167130                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       180453                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       167131                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       180454                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7332                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3342                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       792458                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1308416                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2111548                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1540445                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1540445                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       792352                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1308420                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2111446                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1540463                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1540463                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1835                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1835                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314904                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314904                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314919                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314919                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7332                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3342                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       792458                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1623320                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2426452                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       792352                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1623339                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2426365                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7332                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         3342                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       792458                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1623320                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2426452                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       792352                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1623339                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2426365                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001496                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016807                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024634                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021574                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021575                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988011                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988011                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428378                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.428378                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428361                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.428361                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001496                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016805                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102956                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.074369                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016807                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102955                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.074372                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001496                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016805                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102956                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074369                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016807                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102955                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074372                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -453,42 +450,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98349                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98349                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98351                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98351                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       15972786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      15972786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       15972684                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      15972684                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13911                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13911                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1540445                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1540463                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2264                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2264                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       314909                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       314909                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1584942                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32531741                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       314924                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       314924                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1584730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32531797                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9962                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        21540                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          34148185                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50718144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227716857                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          34148029                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50711360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227719225                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       344448                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       778688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          279558137                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          279553721                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       48008                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4020727                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      4020658                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        3.011846                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.108191                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.108192                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            3973099     98.82%     98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            3973030     98.82%     98.82% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4              47628      1.18%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4020727                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        4020658                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq             10012030                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            10012030                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57692                       # Transaction distribution
@@ -545,12 +542,12 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                 13062804                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                47573                       # number of replacements
-system.iocache.tags.tagsinuse                0.042448                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.042450                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47589                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         4994875221009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042448                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042450                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -558,10 +555,10 @@ system.iocache.tags.age_task_id_blocks_1023::2           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               428652                       # Number of tag accesses
 system.iocache.tags.data_accesses              428652                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
 system.iocache.ReadReq_misses::pc.south_bridge.ide          908                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              908                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::pc.south_bridge.ide          908                       # number of demand (read+write) misses
 system.iocache.demand_misses::total               908                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          908                       # number of overall misses
@@ -576,6 +573,8 @@ system.iocache.overall_accesses::pc.south_bridge.ide          908
 system.iocache.overall_accesses::total            908                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
@@ -586,52 +585,54 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      46720                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq            13903768                       # Transaction distribution
 system.membus.trans_dist::ReadResp           13903768                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13911                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13911                       # Transaction distribution
-system.membus.trans_dist::Writeback             98349                       # Transaction distribution
+system.membus.trans_dist::Writeback            145018                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             2525                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            2096                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            134620                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           134615                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            134621                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134616                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1696                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1696                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20044188                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      7698244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463315                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28205747                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95256                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        95256                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28304395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463319                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28205751                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141923                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141923                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28351066                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10028212                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio     15396485                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17825216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43249913                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3048192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3048192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                46304889                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17825408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43250105                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6034880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6034880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                49291769                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            328677                       # Request fanout histogram
+system.membus.snoop_fanout::samples            375347                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  328677    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  375347    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              328677                       # Request fanout histogram
+system.membus.snoop_fanout::total              375347                       # Request fanout histogram
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index f23e1bb1d..e0cd774db 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,123 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.194411                       # Number of seconds simulated
-sim_ticks                                5194410635000                       # Number of ticks simulated
-final_tick                               5194410635000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.196466                       # Number of seconds simulated
+sim_ticks                                5196466347000                       # Number of ticks simulated
+final_tick                               5196466347000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1318005                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2540682                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            53310327218                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 594964                       # Number of bytes of host memory used
-host_seconds                                    97.44                       # Real time elapsed on the host
-sim_insts                                   128422722                       # Number of instructions simulated
-sim_ops                                     247557000                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 596082                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1149061                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24120553188                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 596696                       # Number of bytes of host memory used
+host_seconds                                   215.44                       # Real time elapsed on the host
+sim_insts                                   128418244                       # Number of instructions simulated
+sim_ops                                     247550593                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            829440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9099264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            828416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9035072                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9957440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       829440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          829440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5149824                       # Number of bytes written to this memory
-system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8139904                       # Number of bytes written to this memory
+system.physmem.bytes_read::total              9892224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       828416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          828416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8113920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8113920                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12960                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12944                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141173                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                155585                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           80466                       # Number of write requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               127186                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                154566                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126780                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               126780                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               159679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1751741                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1916953                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          159679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             159679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            991416                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       575634                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1567051                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            991416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               159419                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1738695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5456                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1903644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          159419                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             159419                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1561430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1561430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1561430                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              159679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1751741                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       581092                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3484003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        155585                       # Number of read requests accepted
-system.physmem.writeReqs                       127186                       # Number of write requests accepted
-system.physmem.readBursts                      155585                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     127186                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9942720                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     14720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8138624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9957440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8139904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      230                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1629                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10087                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9924                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10111                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9612                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10046                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9507                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9544                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9545                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9177                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                9299                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9268                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9485                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9621                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9970                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10158                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10001                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8060                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7801                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7998                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7765                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8116                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7896                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7662                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7717                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7519                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7838                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7675                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7654                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8493                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8626                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8402                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7944                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              159419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1738695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3465075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        154566                       # Number of read requests accepted
+system.physmem.writeReqs                       173500                       # Number of write requests accepted
+system.physmem.readBursts                      154566                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     173500                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9886080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10951744                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9892224                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11104000                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2352                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           1595                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9833                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9504                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9844                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9497                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9570                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9679                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9540                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9680                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9214                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9453                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9241                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9575                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9600                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10182                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10246                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9812                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10679                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10594                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10884                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10241                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10237                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10759                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10579                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10814                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10762                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               11220                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10499                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10145                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              11054                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11426                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10852                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10376                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5194410571500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5196466283500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  155585                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154566                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 127186                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151951                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2969                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 173500                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151257                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2780                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        62                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
@@ -159,183 +156,207 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        55971                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      323.047292                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     191.702498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.763320                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19466     34.78%     34.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13850     24.74%     59.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5737     10.25%     69.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3527      6.30%     76.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2331      4.16%     80.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1635      2.92%     83.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1137      2.03%     85.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          981      1.75%     86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7307     13.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          55971                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5932                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.188806                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      621.686791                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5931     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     5142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     9871                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    10255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    11236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12575                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    12144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    11495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10962                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      348                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::38                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58532                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      356.006287                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     207.370190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.892439                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19432     33.20%     33.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13728     23.45%     56.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5812      9.93%     66.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3460      5.91%     72.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2276      3.89%     76.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1654      2.83%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1160      1.98%     81.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1010      1.73%     82.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10000     17.08%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58532                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6314                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.461831                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      602.615488                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6313     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5932                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5932                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.437289                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.381245                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.855005                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4878     82.23%     82.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              44      0.74%     82.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              36      0.61%     83.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             295      4.97%     88.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             297      5.01%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.34%     93.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              18      0.30%     94.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.24%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              21      0.35%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               5      0.08%     94.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.02%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.05%     94.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             234      3.94%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.05%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.07%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.07%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               9      0.15%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              12      0.20%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             5      0.08%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             8      0.13%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.03%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.17%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5932                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1472209750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4385116000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    776775000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9476.42                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6314                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6314                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.101837                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       21.618222                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       26.504313                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4900     77.61%     77.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              45      0.71%     78.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              20      0.32%     78.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             269      4.26%     82.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             162      2.57%     85.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              59      0.93%     86.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              31      0.49%     86.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              30      0.48%     87.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             184      2.91%     90.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.16%     90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              13      0.21%     90.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.14%     90.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              33      0.52%     91.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              21      0.33%     91.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              17      0.27%     91.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              41      0.65%     92.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              96      1.52%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               7      0.11%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               8      0.13%     94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              18      0.29%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             170      2.69%     97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.08%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            12      0.19%     97.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             4      0.06%     97.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            20      0.32%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.06%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             7      0.11%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             6      0.10%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            38      0.60%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             9      0.14%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.05%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.11%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            12      0.19%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.05%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.05%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             7      0.11%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             4      0.06%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.03%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             4      0.06%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             3      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             2      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6314                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1460181000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4356493500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    772350000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9452.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28226.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.91                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28202.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     127796                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98753                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        21.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     127064                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    139994                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.26                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18369672.18                       # Average gap between requests
-system.physmem.pageHitRate                      80.18                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4972956663750                       # Time in different power states
-system.physmem.memoryStateTime::REF      173452760000                       # Time in different power states
+system.physmem.writeRowHitRate                  81.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15839697.75                       # Average gap between requests
+system.physmem.pageHitRate                      82.02                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4974958806500                       # Time in different power states
+system.physmem.memoryStateTime::REF      173521400000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       48001096250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       47986025500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 211543920                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 211596840                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 115425750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 115454625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                611332800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                600428400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               408337200                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               415698480                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          339273598560                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          339273598560                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          134393532390                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          134240531850                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2998756974750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2998891185750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3473770745370                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3473748494505                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.751736                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.747452                       # Core power per rank (mW)
+system.physmem.actEnergy::0                 218272320                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 224229600                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 119097000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 122347500                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                601746600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                603111600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               549419760                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               559444320                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          339407858400                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          339407858400                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          134224004700                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          134453555955                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          3000139025250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2999937664500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3475259424030                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3475308211875                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.773676                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.783065                       # Core power per rank (mW)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10388821270                       # number of cpu cycles simulated
+system.cpu.numCycles                      10392932694                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128422722                       # Number of instructions committed
-system.cpu.committedOps                     247557000                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             232138334                       # Number of integer alu accesses
+system.cpu.committedInsts                   128418244                       # Number of instructions committed
+system.cpu.committedOps                     247550593                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             232131886                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2301199                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23183159                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    232138334                       # number of integer instructions
+system.cpu.num_func_calls                     2300917                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23183149                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    232131886                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           434808798                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197991574                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434791523                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197987761                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132893231                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95600147                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22258678                       # number of memory refs
-system.cpu.num_load_insts                    13887993                       # Number of load instructions
-system.cpu.num_store_insts                    8370685                       # Number of store instructions
-system.cpu.num_idle_cycles               9791802498.998116                       # Number of idle cycles
-system.cpu.num_busy_cycles               597018771.001885                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.057467                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.942533                       # Percentage of idle cycles
-system.cpu.Branches                          26323220                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                174807      0.07%      0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu                 224862012     90.83%     90.90% # Class of executed instruction
-system.cpu.op_class::IntMult                   139985      0.06%     90.96% # Class of executed instruction
-system.cpu.op_class::IntDiv                    123095      0.05%     91.01% # Class of executed instruction
+system.cpu.num_cc_register_reads            132892118                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95599960                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22255642                       # number of memory refs
+system.cpu.num_load_insts                    13887148                       # Number of load instructions
+system.cpu.num_store_insts                    8368494                       # Number of store instructions
+system.cpu.num_idle_cycles               9795963958.998116                       # Number of idle cycles
+system.cpu.num_busy_cycles               596968735.001885                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.057440                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.942560                       # Percentage of idle cycles
+system.cpu.Branches                          26322824                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                174818      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 224858584     90.83%     90.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   140018      0.06%     90.96% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123105      0.05%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     91.01% # Class of executed instruction
@@ -362,150 +383,150 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.01% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.01% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.01% # Class of executed instruction
-system.cpu.op_class::MemRead                 13887993      5.61%     96.62% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8370685      3.38%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 13887148      5.61%     96.62% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8368494      3.38%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  247558577                       # Class of executed instruction
+system.cpu.op_class::total                  247552167                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements           1622351                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996907                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20038370                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1622863                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.347543                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1622836                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996904                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20034858                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1623348                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.341690                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          51171250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996907                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996904                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           77                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88306374                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88306374                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11941774                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11941774                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8035174                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8035174                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        59224                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         59224                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19976948                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19976948                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20036172                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20036172                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       907115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        907115                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       325077                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       325077                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       402500                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       402500                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1232192                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1232192                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1634692                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1634692                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12725992750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12725992750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11362158354                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11362158354                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  24088151104                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24088151104                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  24088151104                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24088151104                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12848889                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12848889                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8360251                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8360251                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       461724                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       461724                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21209140                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21209140                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21670864                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21670864                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070599                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070599                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038884                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.038884                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871733                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.871733                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.058097                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.058097                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.075433                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.075433                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19549.024100                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14735.590010                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         7616                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88294796                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88294796                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11940626                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11940626                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8032822                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8032822                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59222                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59222                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19973448                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19973448                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20032670                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20032670                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       907502                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        907502                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       325247                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       325247                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402429                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402429                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1232749                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1232749                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1635178                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1635178                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12738871000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12738871000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11339051069                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11339051069                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24077922069                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24077922069                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24077922069                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24077922069                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12848128                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12848128                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8358069                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8358069                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461651                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461651                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21206197                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21206197                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21667848                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21667848                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070633                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070633                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038914                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.038914                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871717                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.871717                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.058132                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.058132                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075466                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075466                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14037.292480                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14037.292480                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34862.892107                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19531.893410                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14724.954757                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6197                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                81                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                83                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    94.024691                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    74.662651                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1538923                       # number of writebacks
-system.cpu.dcache.writebacks::total           1538923                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          288                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          288                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9252                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         9252                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         9540                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         9540                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         9540                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         9540                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906827                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       906827                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315825                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       315825                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402464                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402464                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1222652                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1222652                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1625116                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1625116                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10904887500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10904887500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10229869846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10229869846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5337291000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5337291000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21134757346                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21134757346                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26472048346                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26472048346                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1539435                       # number of writebacks
+system.cpu.dcache.writebacks::total           1539435                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          291                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          291                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9259                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         9259                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9550                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9550                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9550                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9550                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907211                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       907211                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315988                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315988                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402393                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402393                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1223199                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1223199                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1625592                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1625592                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10916933250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10916933250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10204146879                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10204146879                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5337559000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5337559000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21121080129                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21121080129                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26458639129                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26458639129                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94240373000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94240373000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2561690500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2561690500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96802063500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96802063500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037777                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037777                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871655                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871655                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057647                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057647                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074991                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2561805000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2561805000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96802178000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96802178000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070610                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070610                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037806                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037806                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871639                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871639                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057681                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057681                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075023                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.075023                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -513,58 +534,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         7576                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.056356                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        13259                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         7591                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.746674                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.056356                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316022                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316022                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements         7764                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.069200                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13087                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7779                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.682350                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.069200                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316825                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316825                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        52917                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        52917                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13260                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13260                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13260                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13260                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13260                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13260                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8799                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8799                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8799                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8799                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8799                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8799                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     94478000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     94478000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     94478000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     94478000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     94478000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     94478000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22059                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        22059                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22059                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        22059                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22059                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        22059                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.398885                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.398885                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.398885                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses        53125                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53125                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13088                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13088                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13088                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13088                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13088                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13088                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8983                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8983                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8983                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8983                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8983                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8983                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     95259000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     95259000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     95259000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     95259000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     95259000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     95259000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22071                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22071                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22071                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22071                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22071                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22071                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.407005                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.407005                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.407005                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.407005                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.407005                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.407005                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -573,86 +594,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         3010                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         3010                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8799                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8799                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8799                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         8799                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8799                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         8799                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     76879500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     76879500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     76879500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.398885                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.398885                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.398885                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8737.299693                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8737.299693                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8737.299693                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3015                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3015                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8983                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8983                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8983                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8983                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8983                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8983                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     77292500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     77292500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     77292500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     77292500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     77292500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     77292500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.407005                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.407005                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.407005                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.407005                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.407005                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.407005                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8604.308138                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8604.308138                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8604.308138                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8604.308138                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8604.308138                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8604.308138                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            791372                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.348934                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144679417                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            791884                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.702791                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            791291                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.349956                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144673577                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791803                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.714106                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      161114367250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.348934                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996775                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996775                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.349956                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996777                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          294                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146263199                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146263199                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144679417                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144679417                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144679417                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144679417                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144679417                       # number of overall hits
-system.cpu.icache.overall_hits::total       144679417                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791891                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791891                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791891                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791891                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791891                       # number of overall misses
-system.cpu.icache.overall_misses::total        791891                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11123124618                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11123124618                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11123124618                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11123124618                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11123124618                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11123124618                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145471308                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145471308                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145471308                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145471308                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145471308                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145471308                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005444                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005444                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005444                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005444                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005444                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005444                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14046.282403                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14046.282403                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146257197                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146257197                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144673577                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144673577                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144673577                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144673577                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144673577                       # number of overall hits
+system.cpu.icache.overall_hits::total       144673577                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791810                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791810                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791810                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791810                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791810                       # number of overall misses
+system.cpu.icache.overall_misses::total        791810                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11120002617                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11120002617                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11120002617                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11120002617                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11120002617                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11120002617                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145465387                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145465387                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145465387                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145465387                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145465387                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145465387                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005443                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005443                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005443                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005443                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005443                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005443                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14043.776432                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14043.776432                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -661,88 +682,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791891                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       791891                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       791891                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       791891                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       791891                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       791891                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9534445382                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9534445382                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9534445382                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9534445382                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9534445382                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9534445382                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005444                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005444                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005444                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791810                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       791810                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       791810                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       791810                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       791810                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       791810                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9531495383                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9531495383                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9531495383                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9531495383                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9531495383                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9531495383                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005443                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005443                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005443                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12037.604202                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12037.604202                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12037.604202                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12037.604202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12037.604202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12037.604202                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         3756                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.071335                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7599                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         3768                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.016720                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.071335                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191958                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.191958                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements         3671                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.091001                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7743                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3683                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.102362                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.091001                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.193188                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.193188                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        29071                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        29071                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7599                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7599                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        29095                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        29095                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7743                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7743                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7601                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7601                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7601                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7601                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4623                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4623                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4623                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4623                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4623                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4623                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     47504750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     47504750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     47504750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     47504750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     47504750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     47504750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12222                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12222                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7745                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7745                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7745                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7745                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4535                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4535                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4535                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4535                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4535                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4535                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     45208750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     45208750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     45208750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     45208750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     45208750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     45208750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12278                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12278                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12224                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12224                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12224                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12224                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.378252                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.378252                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.378190                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.378190                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.378190                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.378190                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12280                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12280                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12280                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12280                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.369360                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.369360                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.369300                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.369300                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.369300                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.369300                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9968.853363                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9968.853363                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9968.853363                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9968.853363                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9968.853363                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9968.853363                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -751,177 +772,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          825                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          825                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4623                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4623                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4623                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4623                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4623                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4623                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     38257250                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     38257250                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     38257250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     38257250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     38257250                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     38257250                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.378252                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.378252                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.378190                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.378190                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.378190                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.378190                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8275.416396                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8275.416396                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8275.416396                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          782                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          782                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4535                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4535                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4535                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4535                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4535                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4535                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     36137250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     36137250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     36137250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     36137250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     36137250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     36137250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.369360                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.369360                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.369300                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.369300                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.369300                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.369300                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7968.522602                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7968.522602                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7968.522602                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7968.522602                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7968.522602                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7968.522602                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            87384                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64746.924059                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3489247                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           152088                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            22.942290                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87090                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64747.295038                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3489215                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs            22.978340                       # Average number of references to valid blocks.
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69178.883111                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        70150                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73467.883353                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70310.755016                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70574.451288                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        70150                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73467.883353                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70310.755016                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70574.451288                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -930,90 +951,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        80466                       # number of writebacks
-system.cpu.l2cache.writebacks::total            80466                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        80112                       # number of writebacks
+system.cpu.l2cache.writebacks::total            80112                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12960                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28635                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        41601                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1351                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1351                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113819                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113819                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12945                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28645                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        41596                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1332                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1332                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       113458                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12960                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       142454                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       155420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12945                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       142103                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       155054                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12960                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       142454                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       155420                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12945                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       142103                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       155054                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       287750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    790892250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1774999000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2566255250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     13524351                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     13524351                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6458128028                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6458128028                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    788869250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1783855500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2573088750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14201815                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14201815                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6430736280                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6430736280                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       287750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    790892250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8233127028                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9024383278                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    788869250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8214591780                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9003825030                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        76250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       287750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    790892250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8233127028                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9024383278                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    788869250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8214591780                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9003825030                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86680074500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86680074500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2394893500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2394893500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89074968000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89074968000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2395003500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2395003500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89075078000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89075078000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021885                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019715                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808014                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808014                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362918                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362918                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001681                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016349                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021886                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019712                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800962                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.800962                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361567                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361567                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087822                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.064124                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001681                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016349                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087578                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063968                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087822                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.064124                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001681                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016349                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087578                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063968                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1021,57 +1042,57 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2697012                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2696490                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1542758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46721                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2211                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2211                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       313627                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       313627                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583769                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5979028                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8638                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18387                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7589822                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50680192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203991823                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       256960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       613632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          255542607                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       52938                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4020768                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.011831                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.108123                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        2697337                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2696818                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13890                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13890                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1543232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2201                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2201                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       313800                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       313800                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583607                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5980523                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8291                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18581                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7591002                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50675008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204057491                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       240384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       614272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          255587155                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       53212                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4021729                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.011827                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.108106                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            3973200     98.82%     98.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47568      1.18%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            3974165     98.82%     98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47564      1.18%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4020768                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3834027500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4021729                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3834985000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       487500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1190285118                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1190158617                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3054401379                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3054984845                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       6935250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6803250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13198750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13474750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               230267                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              230267                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57693                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57694                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq            1                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               230264                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              230264                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57694                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              10974                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
 system.iobus.trans_dist::MessageReq              1655                       # Transaction distribution
 system.iobus.trans_dist::MessageResp             1655                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
@@ -1093,11 +1114,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       480788                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95134                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3310                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3310                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  579232                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  579226                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -1117,11 +1138,11 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       246674                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027296                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027296                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6620                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3280614                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3280590                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy              3947664                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
@@ -1158,161 +1179,169 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           421906845                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           448397612                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           469814000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52234501                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52228501                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy             1655000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47512                       # number of replacements
-system.iocache.tags.tagsinuse                0.118180                       # Cycle average of tags in use
+system.iocache.tags.replacements                47510                       # number of replacements
+system.iocache.tags.tagsinuse                0.132770                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47528                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47526                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5045851318000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.118180                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007386                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007386                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5045851378000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.132770                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008298                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.008298                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428111                       # Number of tag accesses
-system.iocache.tags.data_accesses              428111                       # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide          847                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              847                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide            1                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total            1                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          847                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               847                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          847                       # number of overall misses
-system.iocache.overall_misses::total              847                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141540186                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    141540186                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    141540186                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    141540186                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    141540186                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    141540186                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          847                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            847                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46721                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46721                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          847                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             847                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          847                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            847                       # number of overall (read+write) accesses
+system.iocache.tags.tag_accesses               428076                       # Number of tag accesses
+system.iocache.tags.data_accesses              428076                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          844                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              844                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          844                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               844                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          844                       # number of overall misses
+system.iocache.overall_misses::total              844                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    143496186                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    143496186                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12353940925                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  12353940925                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    143496186                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    143496186                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    143496186                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    143496186                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          844                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            844                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          844                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             844                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          844                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            844                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide     0.000021                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total     0.000021                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167107.657615                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167107.657615                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167107.657615                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 170019.177725                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 170019.177725                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 170019.177725                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         70456                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9155                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.695904                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                      46720                       # number of fast writes performed
+system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          847                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          847                       # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          847                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          847                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          847                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          847                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     97471186                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2827609160                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2827609160                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     97471186                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     97471186                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           46668                       # number of writebacks
+system.iocache.writebacks::total                46668                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          844                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          844                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          844                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          844                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          844                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          844                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     99583186                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     99583186                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9924498927                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9924498927                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     99583186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     99583186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     99583186                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     99583186                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 117989.556872                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 117989.556872                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              624009                       # Transaction distribution
-system.membus.trans_dist::ReadResp             624009                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13889                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13889                       # Transaction distribution
-system.membus.trans_dist::Writeback             80466                       # Transaction distribution
+system.membus.trans_dist::ReadReq              624001                       # Transaction distribution
+system.membus.trans_dist::ReadResp             624001                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13890                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13890                       # Transaction distribution
+system.membus.trans_dist::Writeback            126780                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2168                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1629                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            113541                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           113541                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2150                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1612                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            113178                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           113178                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1655                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1655                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3310                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3310                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710112                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394547                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1585447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94730                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94730                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1683487                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710114                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       392754                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1583656                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1728361                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6620                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246674                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420221                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15078912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16745807                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19770859                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              943                       # Total snoops (count)
-system.membus.snoop_fanout::samples            285344                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420225                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14991040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16657939                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6005184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22669743                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1607                       # Total snoops (count)
+system.membus.snoop_fanout::samples            331268                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  285344    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  331268    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              285344                       # Request fanout histogram
+system.membus.snoop_fanout::total              331268                       # Request fanout histogram
 system.membus.reqLayer0.occupancy           257196000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           358105500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           358100000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy             3310000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1311782500                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1728081500                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer0.occupancy            1655000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2622169871                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2618580655                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           54356499                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54329499                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index a15c23d57..c9524dba5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000035                       # Number of seconds simulated
-sim_ticks                                    35024500                       # Number of ticks simulated
-final_tick                                   35024500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    35022500                       # Number of ticks simulated
+final_tick                                   35022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72507                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72491                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              396631772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236200                       # Number of bytes of host memory used
+host_inst_rate                                  71946                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71929                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              393524726                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237176                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst        23296                       # Nu
 system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            973946809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               973946809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       665134406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          665134406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           973946809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              973946809                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            974002427                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               974002427                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       665172389                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          665172389                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           974002427                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              974002427                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        34926000                       # Total gap between requests
+system.physmem.totGap                        34924000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895            1      1.11%     84.44% # By
 system.physmem.bytesPerActivate::896-1023            4      4.44%     88.89% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     11.11%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             90                       # Bytes accessed per row activation
-system.physmem.totQLat                        3928000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13921750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3887500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13881250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7369.61                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7293.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26119.61                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         973.95                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26043.62                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         974.00                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      973.95                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      974.00                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           7.61                       # Data bus utilization in percentage
@@ -216,12 +216,12 @@ system.physmem.readRowHits                        435                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        65527.20                       # Average gap between requests
+system.physmem.avgGap                        65523.45                       # Average gap between requests
 system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
 system.physmem.memoryStateTime::REF           1040000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          30394500                       # Time in different power states
+system.physmem.memoryStateTime::ACT          30393500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
 system.physmem.actEnergy::0                    257040                       # Energy for activate commands per rank (pJ)
 system.physmem.actEnergy::1                    385560                       # Energy for activate commands per rank (pJ)
@@ -234,66 +234,43 @@ system.physmem.writeEnergy::1                       0                       # En
 system.physmem.refreshEnergy::0               2034240                       # Energy for refresh commands per rank (pJ)
 system.physmem.refreshEnergy::1               2034240                       # Energy for refresh commands per rank (pJ)
 system.physmem.actBackEnergy::0              21425445                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              20168595                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1              20164320                       # Energy for active background per rank (pJ)
 system.physmem.preBackEnergy::0                 67500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1               1170000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1               1173750                       # Energy for precharge background per rank (pJ)
 system.physmem.totalEnergy::0                26007075                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                25645770                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1                25645245                       # Total energy per rank (pJ)
 system.physmem.averagePower::0             827.295718                       # Core power per rank (mW)
-system.physmem.averagePower::1             815.802457                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
-system.membus.trans_dist::ReadResp                460                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               533                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     533    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 533                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              618000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4976250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    1959                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1201                       # Number of conditional branches predicted
+system.physmem.averagePower::1             815.785757                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                    1972                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1208                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1551                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     381                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1563                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     385                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             24.564797                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             24.632118                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1368                       # DTB read hits
+system.cpu.dtb.read_hits                         1370                       # DTB read hits
 system.cpu.dtb.read_misses                         11                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1379                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1381                       # DTB read accesses
 system.cpu.dtb.write_hits                         884                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     887                       # DTB write accesses
-system.cpu.dtb.data_hits                         2252                       # DTB hits
+system.cpu.dtb.data_hits                         2254                       # DTB hits
 system.cpu.dtb.data_misses                         14                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2266                       # DTB accesses
-system.cpu.itb.fetch_hits                        2630                       # ITB hits
+system.cpu.dtb.data_accesses                     2268                       # DTB accesses
+system.cpu.itb.fetch_hits                        2642                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2647                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2659                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,68 +284,180 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            70049                       # number of cpu cycles simulated
+system.cpu.numCycles                            70045                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1118                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1109                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              10.945156                       # CPI: cycles per instruction
-system.cpu.ipc                               0.091365                       # IPC: instructions per cycle
-system.cpu.tickCycles                           12515                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           57534                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              10.944531                       # CPI: cycles per instruction
+system.cpu.ipc                               0.091370                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12615                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           57430                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           104.047628                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1973                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.674556                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   104.047628                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.025402                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025402                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4569                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4569                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst         1233                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1233                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst          1973                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1973                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst         1973                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1973                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
+system.cpu.dcache.overall_misses::total           227                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7703250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7703250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8679250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8679250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst     16382500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16382500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst     16382500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16382500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst         1335                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1335                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst         2200                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2200                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst         2200                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2200                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076404                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076404                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.103182                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.103182                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.103182                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.103182                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69434                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        69434                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72169.603524                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72169.603524                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7131000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7131000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5128000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5128000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12259000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12259000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12259000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12259000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.071910                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071910                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076818                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076818                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076818                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076818                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           176.176418                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2265                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           176.126032                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2277                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.205479                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.238356                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   176.176418                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.086024                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.086024                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   176.126032                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085999                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085999                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5625                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5625                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         2265                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2265                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2265                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2265                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2265                       # number of overall hits
-system.cpu.icache.overall_hits::total            2265                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5649                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5649                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         2277                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2277                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2277                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2277                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2277                       # number of overall hits
+system.cpu.icache.overall_hits::total            2277                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25941750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25941750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25941750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25941750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25941750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25941750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2630                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2630                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2630                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2630                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138783                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138783                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.138783                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.138783                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71073.287671                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71073.287671                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25915750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25915750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25915750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25915750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25915750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25915750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2642                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2642                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2642                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2642                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2642                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2642                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138153                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.138153                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.138153                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.138153                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.138153                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.138153                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71002.054795                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71002.054795                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          365
 system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25054250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25054250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25054250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25054250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25054250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25054250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138783                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25028250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25028250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25028250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25028250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25028250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25028250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138153                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.138153                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.138153                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              34176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          534                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                534    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        626250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.917543                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          233.857006                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.917543                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007139                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.857006                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007137                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
@@ -459,14 +520,14 @@ system.cpu.l2cache.demand_misses::cpu.inst          533                       #
 system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31726750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31726750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36791750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     36791750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36791750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     36791750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31686750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     31686750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5053000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5053000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     36739750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36739750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     36739750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36739750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          461                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
@@ -483,14 +544,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127
 system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -507,14 +568,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst          533
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          533                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25964750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25964750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25921750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25921750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4147500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30112250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30112250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30112250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30112250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30069250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30069250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30069250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30069250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
@@ -523,126 +584,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.075920                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1968                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.644970                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   104.075920                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.025409                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025409                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4559                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4559                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst         1228                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1228                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst          1968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1968                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst         1968                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1968                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
-system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7718250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7718250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8705750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8705750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     16424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     16424000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16424000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69646                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        69646                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72352.422907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72352.422907                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7145500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7145500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5139500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5139500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12285000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12285000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              34176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          534                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                534    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        626250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
+system.membus.trans_dist::ReadResp                460                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               533                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     533    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 533                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              606000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4967250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index cff801d36..0513960dd 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    18662000                       # Number of ticks simulated
-final_tick                                   18662000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    18733500                       # Number of ticks simulated
+final_tick                                   18733500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40123                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40110                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              289474844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234892                       # Number of bytes of host memory used
+host_inst_rate                                  41421                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41407                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              299977624                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235900                       # Number of bytes of host memory used
 host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst        14272                       # Nu
 system.physmem.bytes_inst_read::total           14272                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst                308                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1056264066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1056264066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       764762619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          764762619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1056264066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1056264066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1052232631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1052232631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       761843756                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          761843756                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1052232631                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1052232631                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           308                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         308                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        18580000                       # Total gap between requests
+system.physmem.totGap                        18651500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -182,118 +182,95 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           44                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      411.636364                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     270.438338                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.932860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     25.00%     25.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            7     15.91%     40.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            4      9.09%     50.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      6.82%     56.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6     13.64%     70.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            5     11.36%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      6.82%     88.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      2.27%     90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            4      9.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             44                       # Bytes accessed per row activation
-system.physmem.totQLat                        1719250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7494250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           43                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      421.209302                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     281.192017                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     321.893842                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             10     23.26%     23.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            8     18.60%     41.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            3      6.98%     48.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      6.98%     55.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6     13.95%     69.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      9.30%     79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      9.30%     88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      4.65%     93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            3      6.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             43                       # Bytes accessed per row activation
+system.physmem.totQLat                        1958750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7733750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5581.98                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6359.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24331.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1056.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25109.58                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1052.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1056.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1052.23                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           8.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.25                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           8.22                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       8.22                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.27                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        256                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        257                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        60324.68                       # Average gap between requests
-system.physmem.pageHitRate                      83.12                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        60556.82                       # Average gap between requests
+system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
 system.physmem.memoryStateTime::REF            520000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT          15310750                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                     90720                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::0                     83160                       # Energy for activate commands per rank (pJ)
 system.physmem.actEnergy::1                    219240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                     49500                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::0                     45375                       # Energy for precharge commands per rank (pJ)
 system.physmem.preEnergy::1                    119625                       # Energy for precharge commands per rank (pJ)
 system.physmem.readEnergy::0                   795600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  1302600                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                  1294800                       # Energy for read commands per rank (pJ)
 system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
 system.physmem.refreshEnergy::0               1017120                       # Energy for refresh commands per rank (pJ)
 system.physmem.refreshEnergy::1               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              10733670                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::0              10790100                       # Energy for active background per rank (pJ)
 system.physmem.actBackEnergy::1              10507095                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 84000                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::0                 34500                       # Energy for precharge background per rank (pJ)
 system.physmem.preBackEnergy::1                282750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                12770610                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                13448430                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             806.607295                       # Core power per rank (mW)
-system.physmem.averagePower::1             849.419233                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
-system.membus.trans_dist::ReadResp                281                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   19712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               308                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     308    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 308                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              362000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2870500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             15.4                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                     786                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               393                       # Number of conditional branches predicted
+system.physmem.totalEnergy::0                12765855                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1                13440630                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             806.306964                       # Core power per rank (mW)
+system.physmem.averagePower::1             848.926575                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                     793                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               397                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  558                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                  562                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                      58                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             10.394265                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             10.320285                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     139                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          508                       # DTB read hits
+system.cpu.dtb.read_hits                          509                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      515                       # DTB read accesses
+system.cpu.dtb.read_accesses                      516                       # DTB read accesses
 system.cpu.dtb.write_hits                         307                       # DTB write hits
 system.cpu.dtb.write_misses                         6                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     313                       # DTB write accesses
-system.cpu.dtb.data_hits                          815                       # DTB hits
+system.cpu.dtb.data_hits                          816                       # DTB hits
 system.cpu.dtb.data_misses                         13                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                      828                       # DTB accesses
-system.cpu.itb.fetch_hits                         962                       # ITB hits
+system.cpu.dtb.data_accesses                      829                       # DTB accesses
+system.cpu.itb.fetch_hits                         974                       # ITB hits
 system.cpu.itb.fetch_misses                        13                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     975                       # ITB accesses
+system.cpu.itb.fetch_accesses                     987                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,68 +284,180 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            37324                       # number of cpu cycles simulated
+system.cpu.numCycles                            37467                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2585                       # Number of instructions committed
 system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                           635                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                           596                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              14.438685                       # CPI: cycles per instruction
-system.cpu.ipc                               0.069258                       # IPC: instructions per cycle
-system.cpu.tickCycles                            5337                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           31987                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              14.494004                       # CPI: cycles per instruction
+system.cpu.ipc                               0.068994                       # IPC: instructions per cycle
+system.cpu.tickCycles                            5412                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           32055                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            48.468521                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst    48.468521                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.011833                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011833                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              1677                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1677                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst          441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst          251                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst           692                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              692                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst          692                       # number of overall hits
+system.cpu.dcache.overall_hits::total             692                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst           61                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst           43                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst          104                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
+system.cpu.dcache.overall_misses::total           104                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4636500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4636500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3517500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3517500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst      8154000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      8154000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst      8154000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      8154000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst          502                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          502                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst          796                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          796                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst          796                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          796                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.121514                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.121514                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.146259                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.130653                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.130653                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.130653                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.130653                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 78403.846154                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 78403.846154                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           16                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           58                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4302500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4302500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2086500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2086500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6389000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6389000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6389000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6389000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.115538                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115538                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.106784                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.106784                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.106784                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.106784                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           118.813999                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 739                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           118.426247                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 751                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.313901                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.367713                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   118.813999                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.058015                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.058015                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   118.426247                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.057825                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.057825                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2147                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2147                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          739                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             739                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           739                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              739                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          739                       # number of overall hits
-system.cpu.icache.overall_hits::total             739                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              2171                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2171                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst          751                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             751                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           751                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              751                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          751                       # number of overall hits
+system.cpu.icache.overall_hits::total             751                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          223                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           223                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          223                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            223                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
 system.cpu.icache.overall_misses::total           223                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15454750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15454750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15454750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15454750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15454750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15454750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          962                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          962                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          962                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          962                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.231809                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.231809                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.231809                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.231809                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.231809                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.231809                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69303.811659                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69303.811659                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69303.811659                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69303.811659                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69303.811659                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69303.811659                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15431500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15431500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15431500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15431500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15431500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15431500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          974                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          974                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          974                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          974                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          974                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          974                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.228953                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.228953                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.228953                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.228953                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.228953                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.228953                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69199.551570                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69199.551570                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          223
 system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14914250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14914250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14914250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14914250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14914250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14914250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231809                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.231809                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.231809                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66880.044843                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14892500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14892500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14892500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14892500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14892500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14892500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.228953                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.228953                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.228953                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          446                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              19712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          308                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                308    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            308                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        381750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        136250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          146.987026                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          146.486275                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.987026                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004486                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004486                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.486275                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004470                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004470                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          139                       # Occupied blocks per task id
@@ -453,14 +514,14 @@ system.cpu.l2cache.demand_misses::cpu.inst          308                       #
 system.cpu.l2cache.demand_misses::total           308                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          308                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18929750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18929750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      1803250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1803250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20733000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20733000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20733000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20733000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18913000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18913000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2059500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2059500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20972500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     20972500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20972500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     20972500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          281                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          281                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.inst           27                       # number of ReadExReq accesses(hits+misses)
@@ -477,14 +538,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst            1
 system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67365.658363                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67365.658363                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66787.037037                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66787.037037                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.935065                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67314.935065                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.935065                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67314.935065                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -501,14 +562,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst          308
 system.cpu.l2cache.demand_mshr_misses::total          308                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          308                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15410750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15410750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1471750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1471750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16882500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16882500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15398500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15398500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1725500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1725500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17124000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17124000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
@@ -517,126 +578,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54842.526690                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54842.526690                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54509.259259                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54509.259259                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54813.311688                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54813.311688                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54813.311688                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54813.311688                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.699994                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 687                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.082353                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst    48.699994                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.011890                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011890                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1667                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1667                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst          436                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             436                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          251                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst           687                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              687                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst          687                       # number of overall hits
-system.cpu.dcache.overall_hits::total             687                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst           61                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst           43                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          104                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
-system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4631500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4631500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3005500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3005500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst      7637000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7637000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst      7637000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7637000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst          497                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          497                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst          791                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          791                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst          791                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          791                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.122736                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.122736                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.131479                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.131479                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.131479                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.131479                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75926.229508                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75926.229508                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69895.348837                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69895.348837                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73432.692308                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73432.692308                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73432.692308                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73432.692308                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           58                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           27                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4297000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4297000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      1830750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1830750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6127750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6127750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6127750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6127750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.116700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.107459                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.107459                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74086.206897                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74086.206897                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67805.555556                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67805.555556                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72091.176471                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72091.176471                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72091.176471                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72091.176471                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          446                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               616                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              19712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          308                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                308    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            308                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        381000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        137000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
+system.membus.trans_dist::ReadResp                281                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          616                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    616                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   19712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               308                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     308    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 308                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              363000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2868500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             15.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index d08d4e917..1f9a90b5a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,47 +1,47 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    27911000                       # Number of ticks simulated
-final_tick                                   27911000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    27981000                       # Number of ticks simulated
+final_tick                                   27981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   3437                       # Simulator instruction rate (inst/s)
-host_op_rate                                     4023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               20833659                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251612                       # Number of bytes of host memory used
-host_seconds                                     1.34                       # Real time elapsed on the host
+host_inst_rate                                  65720                       # Simulator instruction rate (inst/s)
+host_op_rate                                    76928                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              399296424                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250660                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4604                       # Number of instructions simulated
 sim_ops                                          5390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             26880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26880                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19456                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   420                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            963061159                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               963061159                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       697072839                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          697072839                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           963061159                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              963061159                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           420                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             26944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19520                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            962939137                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               962939137                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       697616240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          697616240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           962939137                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              962939137                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         420                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    26880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    26944                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     26880                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     26944                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                  91                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  51                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  52                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  23                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  43                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  22                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  41                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  36                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  12                       # Per bank write bursts
@@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        27825500                       # Total gap between requests
+system.physmem.totGap                        27895500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     420                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     421                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -87,7 +87,7 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       345                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        68                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,28 +182,28 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           64                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             396                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     274.035894                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.902425                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             10     15.62%     15.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     26.56%     42.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           12     18.75%     60.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7     10.94%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.69%     76.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.12%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      4.69%     84.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     15.62%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             64                       # Bytes accessed per row activation
-system.physmem.totQLat                        2575500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10450500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2100000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6132.14                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      403.301587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     282.308639                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.677686                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              9     14.29%     14.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     25.40%     39.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13     20.63%     60.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7     11.11%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.76%     76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.17%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      4.76%     84.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     15.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
+system.physmem.totQLat                        2478000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10371750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5885.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24882.14                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         963.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24635.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         962.94                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      963.06                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      962.94                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           7.52                       # Data bus utilization in percentage
@@ -211,20 +211,20 @@ system.physmem.busUtilRead                       7.52                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        348                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        350                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.86                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        66251.19                       # Average gap between requests
-system.physmem.pageHitRate                      82.86                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        66260.10                       # Average gap between requests
+system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
 system.physmem.memoryStateTime::IDLE            12000                       # Time in different power states
 system.physmem.memoryStateTime::REF            780000                       # Time in different power states
 system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
 system.physmem.memoryStateTime::ACT          22840500                       # Time in different power states
 system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    302400                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::0                    294840                       # Energy for activate commands per rank (pJ)
 system.physmem.actEnergy::1                    136080                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    165000                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::0                    160875                       # Energy for precharge commands per rank (pJ)
 system.physmem.preEnergy::1                     74250                       # Energy for precharge commands per rank (pJ)
 system.physmem.readEnergy::0                  2090400                       # Energy for read commands per rank (pJ)
 system.physmem.readEnergy::1                   702000                       # Energy for read commands per rank (pJ)
@@ -232,47 +232,24 @@ system.physmem.writeEnergy::0                       0                       # En
 system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
 system.physmem.refreshEnergy::0               1525680                       # Energy for refresh commands per rank (pJ)
 system.physmem.refreshEnergy::1               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              16015860                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              16042365                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                122250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                 99000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                20221590                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                18579375                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             856.166817                       # Core power per rank (mW)
-system.physmem.averagePower::1             786.636676                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 377                       # Transaction distribution
-system.membus.trans_dist::ReadResp                377                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          840                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    840                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               420                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     420    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 420                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3924000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.1                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    1903                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1138                       # Number of conditional branches predicted
+system.physmem.actBackEnergy::0              16099650                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1              15972255                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0                 48750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1                160500                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0                20220195                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1                18570765                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             856.107753                       # Core power per rank (mW)
+system.physmem.averagePower::1             786.272135                       # Core power per rank (mW)
+system.cpu.branchPred.lookups                    1926                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1154                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               341                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1573                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     325                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1596                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     326                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             20.661157                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             20.426065                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     222                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -358,268 +335,44 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            55822                       # number of cpu cycles simulated
+system.cpu.numCycles                            55962                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4604                       # Number of instructions committed
 system.cpu.committedOps                          5390                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1208                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1118                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              12.124674                       # CPI: cycles per instruction
-system.cpu.ipc                               0.082476                       # IPC: instructions per cycle
-system.cpu.tickCycles                           10521                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           45301                       # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           162.201432                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1918                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               321                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.975078                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   162.201432                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.079200                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.079200                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          318                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.155273                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4799                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4799                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1918                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1918                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1918                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1918                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1918                       # number of overall hits
-system.cpu.icache.overall_hits::total            1918                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          321                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           321                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          321                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            321                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          321                       # number of overall misses
-system.cpu.icache.overall_misses::total           321                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     21503250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     21503250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     21503250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     21503250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     21503250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     21503250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2239                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2239                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2239                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2239                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2239                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2239                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143368                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.143368                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.143368                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.143368                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.143368                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.143368                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66988.317757                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66988.317757                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          321                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          321                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          321                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          321                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          321                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          321                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20730750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20730750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20730750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20730750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20730750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20730750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143368                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.143368                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143368                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.143368                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          642                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               934                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              29888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          467                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5                467    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            467                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         233500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        546750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        234242                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          195.957604                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              377                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.103448                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.957604                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005980                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          377                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011505                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4156                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4156                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           39                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           39                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           39                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          385                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          385                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          428                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           428                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          428                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          428                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26169000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     26169000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2824000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2824000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     28993000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     28993000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     28993000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     28993000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          424                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          424                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          467                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          467                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          467                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          467                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.908019                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.908019                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.916488                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.916488                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.916488                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.916488                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          420                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          420                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20974000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20974000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2284000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2284000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23258000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23258000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23258000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23258000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.889151                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889151                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899358                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.899358                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899358                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.899358                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.cpi                              12.155083                       # CPI: cycles per instruction
+system.cpu.ipc                               0.082270                       # IPC: instructions per cycle
+system.cpu.tickCycles                           10640                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           45322                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.665340                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1919                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            86.669090                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1922                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.143836                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.164384                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst    86.665340                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst    86.669090                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.021159                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.021159                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4348                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4348                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst         1051                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1051                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4354                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4354                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst         1054                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1054                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.inst          846                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.inst           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst          1897                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1897                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst         1897                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1897                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.inst          1900                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1900                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst         1900                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1900                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.inst          115                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.inst           67                       # number of WriteReq misses
@@ -628,42 +381,42 @@ system.cpu.dcache.demand_misses::cpu.inst          182                       # n
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6950741                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6950741                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4586500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4586500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     11537241                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11537241                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     11537241                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11537241                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1166                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1166                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6708741                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6708741                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4576500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4576500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst     11285241                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11285241                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst     11285241                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11285241                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst         1169                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1169                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst         2079                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2079                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst         2079                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2079                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.098628                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098628                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.inst         2082                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2082                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst         2082                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2082                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.098375                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098375                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.073384                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.087542                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.087542                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.087542                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087542                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63391.434066                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63391.434066                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.087416                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.087416                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.087416                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087416                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62006.818681                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62006.818681                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -688,30 +441,277 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6257258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6257258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2867000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2867000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      9124258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9124258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      9124258                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9124258                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.088336                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088336                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6015258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6015258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2857500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2857500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      8872758                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8872758                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      8872758                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8872758                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.088109                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088109                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.070226                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.070226                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.070226                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.070226                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.070125                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.070125                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.070125                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.070125                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements                 3                       # number of replacements
+system.cpu.icache.tags.tagsinuse           162.236148                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1919                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.959627                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   162.236148                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079217                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079217                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4804                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4804                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1919                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1919                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1919                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1919                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1919                       # number of overall hits
+system.cpu.icache.overall_hits::total            1919                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          322                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           322                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          322                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            322                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          322                       # number of overall misses
+system.cpu.icache.overall_misses::total           322                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     21729250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     21729250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     21729250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     21729250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     21729250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     21729250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2241                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2241                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2241                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2241                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2241                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2241                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143686                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.143686                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.143686                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.143686                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.143686                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.143686                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67482.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67482.142857                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          322                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          322                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          322                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          322                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          322                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          322                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20954750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20954750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20954750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20954750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20954750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20954750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143686                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143686                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143686                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.143686                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143686                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.143686                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          195.981905                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.103175                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.981905                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005981                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005981                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4165                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4165                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           39                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           39                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           39                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          386                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          429                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          429                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26149000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26149000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     28963500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     28963500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     28963500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     28963500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          425                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          425                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          468                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          468                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          468                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          468                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.908235                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.908235                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.916667                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.916667                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.916667                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          421                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          421                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          421                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20940500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20940500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2273500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2273500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23214000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     23214000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23214000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     23214000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.889412                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889412                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.899573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              29952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          468                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5                468    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            468                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        548250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        234242                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 378                       # Transaction distribution
+system.membus.trans_dist::ReadResp                378                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          842                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    842                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               421                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     421    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 421                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              490000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3936000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             14.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------